Product Specs

47 PWM — Pulse width modulation
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502
NRF_PWM0->PSEL.OUT[0] = (first_pin << PWM_PSEL_OUT_PIN_Pos) |
(PWM_PSEL_OUT_CONNECT_Connected <<
PWM_PSEL_OUT_CONNECT_Pos);
NRF_PWM0->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
NRF_PWM0->MODE
NRF_PWM0->PRESCALER
NRF_PWM0->COUNTERTOP
NRF_PWM0->LOOP
NRF_PWM0->DECODER
= (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos);
= (PWM_PRESCALER_PRESCALER_DIV_1 <<
PWM_PRESCALER_PRESCALER_Pos);
= (16000 << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec
= (1 << PWM_LOOP_CNT_Pos);
= (PWM_DECODER_LOAD_Common << PWM_DECODER_LOAD_Pos) |
(PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);
NRF_PWM0->SEQ[0].PTR = ((uint32_t)(seq0_ram) << PWM_SEQ_PTR_PTR_Pos);
NRF_PWM0->SEQ[0].CNT = ((sizeof(seq0_ram) / sizeof(uint16_t)) <<
PWM_SEQ_CNT_CNT_Pos);
NRF_PWM0->SEQ[0].REFRESH = 1;
NRF_PWM0->SEQ[0].ENDDELAY = 1;
NRF_PWM0->SEQ[1].PTR = ((uint32_t)(seq1_ram) << PWM_SEQ_PTR_PTR_Pos);
NRF_PWM0->SEQ[1].CNT = ((sizeof(seq1_ram) / sizeof(uint16_t)) <<
PWM_SEQ_CNT_CNT_Pos);
NRF_PWM0->SEQ[1].REFRESH = 0;
NRF_PWM0->SEQ[1].ENDDELAY = 0;
NRF_PWM0->TASKS_SEQSTART[0] = 1;
SEQ[0].CNT=2, SEQ[1].CNT=3, SEQ[0].REFRESH=1, SEQ[1].REFRESH=0, SEQ[0].ENDDELAY=1, SEQ[1].ENDDELAY=0, LOOP.CNT=1
(continued below)
SEQSTART[0]
SEQSTARTED[0]
SEQEND[0]
(continuation)
SEQSTARTED[1]
Figure 146: Example using two sequences
SEQEND[1]
LOOPSDONE
The decoder can also be configured to asynchronously load a new PWM duty cycle. If the DECODER.MODE
register is set to NextStep - then the NEXTSTEP task will cause an update of the internal compare registers
on the next PWM period.
The figures below provide an overview of each part of an arbitrary sequence, in various modes
(LOOP.CNT=0 and LOOP.CNT>0). In particular are represented:
• Initial and final duty cycle on the PWM output(s)
• Chaining of SEQ[0] and SEQ[1] if LOOP.CNT>0
• Influence of registers on the sequence
• Events fired during a sequence
• DMA activity (loading of next value and applying it to the output(s))
Note that the single-shot example applies also to SEQ[1], only SEQ[0] is represented for simplicity.
P
SEQ[0].PTR
O
L
P
O
L
Event/Tasks
PWM Clock Period
COMPARE
COMPARE
P
SEQ[1].PTR
O
L
1 PWM period
SEQ[0].ENDDELAY=1
P
O
L
PWM Generation maintains
last played value
Event/Tasks
COMPARE
COMPARE