Product Specs

47 PWM — Pulse width modulation
Page
509
PWM module enable register
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW ENABLE
Enable or disable PWM module
Disabled
0
Disabled
Enabled
1
Enable
47.5.6 MODE
Address offset: 0x504
Selects operating mode of the wave counter
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW UPDOWN
Selects up or up and down as wave counter mode
Up
0
Up counter - edge aligned PWM duty-cycle
UpAndDown
1
Up and down counter - center aligned PWM duty cycle
47.5.7 COUNTERTOP
Address offset: 0x508
Value up to which the pulse generator counter counts
Bit number
Id
Reset 0x000003FF
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
A
0
13
A
0
12
A
0
11
A
0
10
A
0
9
A
1
8
A
1
7
A
1
6
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
1
Id RW Field
Value Id
Value
Description
A RW COUNTERTOP [3..32767] Value up to which the pulse generator counter counts. This register is
ignored when DECODER.MODE=WaveForm and onlyvalues
from RAM will be used.
47.5.8 PRESCALER
Address offset: 0x50C
Configuration for PWM_CLK
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW PRESCALER
Pre-scaler of PWM_CLK
DIV_1
0
Divide by 1 (16MHz)
DIV_2
1
Divide by 2 ( 8MHz)
DIV_4
2
Divide by 4 ( 4MHz)
DIV_8
3
Divide by 8 ( 2MHz)
DIV_16
4
Divide by 16 ( 1MHz)
DIV_32
5
Divide by 32 ( 500kHz)
DIV_64
6
Divide by 64 ( 250kHz)
DIV_128
7
Divide by 128 ( 125kHz)
47.5.9 DECODER
Address offset: 0x510
Configuration of the decoder