Product Specs

13 FICR — Factory information configuration
registers
Page 51
Bit number
Id
Reset 0x00003E10
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
A
1
12
A
1
11
A
1
10
A
1
9
A
1
8
A
0
7
A
0
6
A
0
5
A
0
4
A
1
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A R B B (y-intercept)
13.1.33 TEMP.T0
Address offset: 0x434
Segment end T0.
Bit number
Id
Reset 0x000000E2
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
A
1
6
A
1
5
A
1
4
A
0
3
A
0
2
A
0
1
A
1
0
A
0
Id RW Field
Value Id
Value
Description
A R T T (segment end)register.
13.1.34 TEMP.T1
Address offset: 0x438
Segment end T1.
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
A
0
6
A
0
5
A
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A R T T (segment end)register.
13.1.35 TEMP.T2
Address offset: 0x43C
Segment end T2.
Bit number
Id
Reset 0x00000014
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
A
0
6
A
0
5
A
0
4
A
1
3
A
0
2
A
1
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A R T T (segment end)register.
13.1.36 TEMP.T3
Address offset: 0x440
Segment end T3.
Bit number
Id
Reset 0x00000019
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
A
0
6
A
0
5
A
0
4
A
1
3
A
1
2
A
0
1
A
0
0
A
1
Id RW Field
Value Id
Value
Description
A R T T (segment end)register.
13.1.37 TEMP.T4
Address offset: 0x444
Segment end T4.