Product Specs

53 Reference circuitry
Page
552
matching circuitry (components between device pin ANT and the antenna) to reduce the stray capacitances
that influence RF performance.
A matching network is needed between the RF pin ANT and the antenna, to match the antenna impedance
(normally 50 ohm) to the optimum RF load impedance for the chip. For optimum performance, the
impedance for the matching network should be set as described in the recommended package reference
circuitry in Reference circuitry on page 546 above.
The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF
capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the
chip should be filtered and routed separately from the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD
bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground
plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground
plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via
hole should be used for each VSS pin.
Fast switching digital signals should not be routed close to the crystal or the power supply lines. Capacitive
loading of fast switching digital output lines should be minimized in order to avoid radio interference.
53.8 PCB layout example
The PCB layout shown below is a reference layout for the QFN package with internal LDO setup.
Important: Pay attention to how the capacitor C3 is grounded. It is not directly connected to the
ground plane, but grounded via VSS pin 31. This is done to create additional filtering of harmonic
components.
For all available reference layouts, see Reference layout nRF52 Series.
Figure 175: Top silk layer