EM78P458/459 OTP ROM EM78P458/459 8-BIT MICRO-CONTROLLER Version 1.3 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C.
EM78P458/459 OTP ROM Specification Revision History Version Content 1.0 Initial version 1.1 Modify ERC frequency 2003/03/06 1.2 Add AD & OP spec 2003/05/07 1.
EM78P458/459 OTP ROM 1. GENERAL DESCRIPTION EM78P458 and EM78P459 are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. It is equipped with a 4K*13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). With its OTP-ROM feature, it is able to offer a convenient way of developing and verifying user’s programs. Moreover, user can take advantage of EMC Writer to easily program his development code.
EM78P458/459 OTP ROM 2. FEATURES • Operating voltage range: 2.3V~5.5V • Operating temperature range: 0°C~70°C • Operating frequency range(base on 2 clocks): * Crystal mode: DC ~ 20MHz/2clks,5V; DC ~ 8MHz/2clks,3V * RC mode: DC ~ 4MHz/2clks,5V; DC ~ 4MHz/2clks,3V • Low power consumption: * Less than 1.
EM78P458/459 OTP ROM • Package types: * 20 pin DIP 300mil : EM78P458AP * 20 pin SOP 300mil : EM78P458AM * 24 pin skinny DIP 300mil : EM78P459AK * 24 pin SOP 300mil : EM78P459AM • Power on voltage detector available (2.0V± 0.15V) This specification is subject to change without prior notice. 5 07.01.2003 (V1.
EM78P458/459 OTP ROM 3.
EM78P458/459 OTP ROM PWM2 VREF 15 I 20, 1,2 I O TCC 19 I VSS 5 - CIN-, CIN+, CO * Defined by PWMCON (IOC51)<6, 7> * External reference voltage for ADC * Defined by AD-CMPCON (IOCA0)<7>. * “-“ -> the input pin of Vin- of the comparator. * “+”-> the input pin of Vin+ of the comparator. * Pin CO is the output of the comparator. * Defined by AD-CMPCON (IOCA0) <5, 6> * Real time clock/counter with Schmitt trigger input pin; it must be tied to VDD or VSS if it is not in use. Ground.
EM78P458/459 OTP ROM 4. FUNCTION DESCRIPTION WDT Timer WDT Time-out STACK 0 PC STACK 1 Prescaler STACK 2 Oscillator/ Timming Control /INT STACK 3 ROM STACK 4 STACK 5 ENTCC Interrupt Control R1(TCC) Instruction Register STACK 6 STACK 7 Sleep & Wake Up Control ALU Instruction Decoder RAM R3 R4 ACC DATA & CONTROL BUS Comparators IOC5 R5 2 PWMs P P P P PP P P 5555 55 55 0123 45 67 8 ADC IOC6 R6 P PPPPPP P 66666666 01234567 Fig. 2 The Functional Block Diagram of EM78P458/459 4.
EM78P458/459 OTP ROM • The contents of R2 are set to all "0"s upon a RESET condition. • "JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. • "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. • "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack.
EM78P458/459 OTP ROM 4. R3 (Status Register) 7 CMPOUT 6 PS1 5 PS0 4 T 3 P 2 Z 1 DC 0 C • Bit 7 (CMPOUT) the result of the comparator output. • Bit 6 (PS1) ~ 5 (PS0) Page select bits. PS0~PS1 are used to select a program memory page. When executing a "JMP", "CALL", or other instructions which cause the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages.
EM78P458/459 OTP ROM 00 R0 01 R1 (TCC) 02 R2 (PC) STACK 0 03 R3 (Status) STACK 1 04 R4 (RSR) STACK 2 05 R5 (Port 5) STACK 3 IOC50 IOC51 (PWMCON) 06 R6 (Port 6) STACK 4 IOC60 IOC61 (DT1L) 07 R7 STACK 5 IOC71 (DT1H) 08 R8 STACK 6 IOC81 (PRD1) 09 R9 (ADCON) STACK 7 IOC90 (GCON) IOC91 (DT2L) 0A RA (ADDATA) IOCA0 (AD-CMPCON) IOCA1 (DT2H) 0B RB (TMR1L) IOCB0 IOCB1 (PRD2) 0C RC (TMR1H) IOCC0 IOCC1 (DL1L) 0D RD (TMR2L) IOCD0 IOCD1 (DL1H) 0E RE (TMR2H) IOCE0 IO
EM78P458/459 OTP ROM 8. R9 (ADCON: Analog to Digital Control) 7 - 6 - 5 IOCS 4 ADRUN 3 ADPD 2 ADIS2 1 ADIS1 0 ADIS0 • Bit 7:Bit 6 Unemployed, read as ‘0’; • Bit 5(IOCS): Select the Segment of IO control register. 1 = Segment 1 ( IOC51~IOCF1 ) selected; 0 = Segment 0 ( IOC50~IOCF0 ) selected; • Bit 4 (ADRUN): ADC starts to RUN. 1 = an A/D conversion is started. This bit can be set by software; 0 = reset on completion of the conversion.
EM78P458/459 OTP ROM An 8-bit general-purpose register. 13. RE A 2-bit, Bit 0 and Bit 1 register. 14. RF (Interrupt Status Register) 7 - 6 CMPIF 5 PWM2IF 4 PWM1IF 3 ADIF 2 EXIF 1 ICIF 0 TCIF “1” means interrupt request, and “0” means no interrupt occurs. • Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software. • Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by software. • Bit 2 (EXIF) External interrupt flag.
EM78P458/459 OTP ROM 2. CONT (Control Register) 7 INTE 6 INT 5 TS 4 TE 3 PAB 2 PSR2 1 PSR1 0 PSR0 • Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits. PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 • Bit 3 (PAB) Prescaler assignment bit. 0: TCC; 1: WDT.
EM78P458/459 OTP ROM 4. IOC90 (GCON: I/O Configuration & Control of ADC ) 7 OP2E 6 OP1E 5 G22 4 G21 3 G20 2 G12 1 G11 0 G10 • Bit 7 ( OP2E ) Enable the gain amplifier which input is connected to P64 and output is connected to the 8-1 analog switch. 0 = OP2 is off ( default value ), and bypasses the input signal to the ADC; 1 = OP2 is on. • Bit 6 ( OP1E ) Enable the gain amplifier whose input is connected to P60 and output is connected to the 8-1 analog switch.
EM78P458/459 OTP ROM 1 = The Vref of the ADC is connected to P53/VREF. • Bit 6 (CE): Comparator enable bit 0 = Comparator is off (default value); 1 = Comparator is on. • Bit 5 ( COE ): Set P57 as the output of the comparator 0 = the comparator acts as an OP if CE=1. 1 = act as a comparator if CE=1. • Bit4:Bit2 (IMS2:IMS0): Input Mode Select. ADC configuration definition bit. The following Table describes how to define the characteristic of each pin of R6.
EM78P458/459 OTP ROM • Bit 4 (/PD4) Control bit is used to enable the pull-down of the P64 pin. • Bit 5 (/PD5) Control bit is used to enable the pull-down of the P65 pin. • Bit 6 (/PD6) Control bit is used to enable the pull-down of the P66 pin. • Bit 7 (/PD7) Control bit is used to enable the pull-down of the P67 pin. • IOCB0 register is both readable and writable. 7.
EM78P458/459 OTP ROM 9. IOCE0 (WDT Control Register) 7 WDTE 6 EIS 5 - 4 - 3 - 2 - 1 - 0 - • Bit 7 (WDTE) Control bit is used to enable Watchdog Timer. 0: Disable WDT; 1: Enable WDT. WDTE is both readable and writable • Bit 6 (EIS) Control bit is used to define the function of the P50 (/INT) pin. 0: P50, input pin only; 1: /INT, external interrupt pin. In this case, the I/O control bit of P50 (bit 0 of IOC50) must be set to "1". When EIS is "0", the path of /INT is masked.
EM78P458/459 OTP ROM • Bit 5 (PWM2IE) PWM2IF interrupt enable bit. 0: disable PWM2 interrupt 1: enable PWM2 interrupt • Bit 6 (CMPIE) CMPIF interrupt enable bit. 0: disable CMPIF interrupt 1: enable CMPIF interrupt • Bit 7: Unimplemented, read as ‘0’. Individual interrupt is enabled by setting its associated control bit in the IOCF0 to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 11. IOCF0 register is both readable and writable. 11.
EM78P458/459 OTP ROM • Bit 1 : Bit 0 ( T1P1:T1P0 ): TMR1 clock prescale option bits. T1P1 0 0 1 1 T1P0 0 1 0 1 Prescale 1:2(Default) 1:8 1:32 1:64 12. IOC61 ( DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1 ) A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1. 13.
EM78P458/459 OTP ROM 0 = Calibration disable; 1 = Calibration enable. • Bit 6 (SIGN2): Polarity bit of offset voltage 0 = Negative voltage; 1 = Positive voltage. • Bit 5:Bit 3 (VOF2[2]:VOF2[0]): Offset voltage bits • Bit 1:Bit 0 (PWM2[9]:PWM2[8]): The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM2 output to stay at high until the value matches with TMR2. 17. IOCB1 ( PRD2: Period of PWM2 ) The content of IOCB1 is a period (time base) of PWM2.
EM78P458/459 OTP ROM 4.3 TCC/WDT & Prescaler An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT only at any given time, and the PAB bit of CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the prescale ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the WDTC or SLEP instructions. Fig.
EM78P458/459 OTP ROM CLK (Fosc/2 or Fosc/4) DATA BUS 0 TCC Pin 1 TE 1 M U X M U X 0 TS 1 M U X 8-bit Counter PAB 8-to-1 MUX 0 WDTE (in IOCE) TCC (R1) TCC overflow interrupt PAB 0 WDT SYNC 2 cycles PSR0 ~ PSR2 1 MUX PAB WDT timeout Fig. 5 Block Diagram of TCC and WDT 4.4 I/O Ports Port 5, Port 6, and the I/O registers are bi-directional tri-state I/O ports. The function of Pull-high, Pull-down, and Open-drain can be set internally by IOCB0, IOCC0, and IOCD0, respectively.
EM78P458/459 OTP ROM PCRD Q D _ PORT CLK Q C L Q P R _ CLK Q PCWR IOD D PDWR C L PDRD M U X 0 1 NOTE: Pull-down is not shown in the figure. Fig. 6 The Ccircuit of I/O Port and I/O Control Register for Port 5 PCRD Q _ P R D CLK Q PCWR C L P50, /INT PORT Q P R _ CLK Q D IOD PDWR C L Bit 6 of IOCE0 D P R CLK C L 0 Q 1 _ M U X Q PDRD TI 0 D P R CLK C L Q _ Q INT NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig.
EM78P458/459 OTP ROM PCRD Q P R _ CLK Q D PCWR C L P60 ~ P67 Q PORT _ Q 0 P R IOD D CLK PDWR C L M U X 1 PDRD TI n D P R CLK C L Q _ Q NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 8 The Circuit of I/O Port and I/O Control Register for P60~P67 IOCE.1 D P R Q Interrupt CLK _ C Q L RE.
EM78P458/459 OTP ROM Table 4 Usage of Port 6 Input Changed Wake-up/Interrupt Function Usage of Port 6 Input Status Changed Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (II) Port 6 Input Status Change Interrupt (a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6) 1. Disable WDT 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF0.1) 3. Execute "ENI" or "DISI" 4. IF Port 6 changed (interrupt) 4. Enable interrupt (Set IOCF0.1) → Interrupt vector (008H) 5.
EM78P458/459 OTP ROM (1) External reset input on /RESET pin. (2) WDT time-out (if enabled). (3) Port 6 input status change (if enabled). (4) Comparator high. The first two cases will cause the EM78P458/459 to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Case 3 is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up.
EM78P458/459 OTP ROM IOW RF ENI (or DISI) ; Enable (or disable) global interrupt SLEP ; Sleep NOP Similarly, if the Comparator High Interrupt is used to wake up the EM78P458/459 (as in Case [c] above), the following instructions must be executed before SLEP: MOV A, @0Bxx000110 ; Select internal TCC clock CONTW CLR R1 ; Clear TCC and prescaler MOV A, @0Bxxxx1110 ; Select WDT prescaler CONTW WDTC ; Clear WDT and prescaler MOV A, @0B0xxxxxxx ; Disable WDT IOW RE MOV A, @0B01xxxxxx ; Enable com
EM78P458/459 OTP ROM Table 5 The Values of RST, T, and P after RESET Reset Type Power-on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-up on pin change during SLEEP mode T P 1 *P 1 0 0 1 1 *P 0 *P 0 0 *P: Previous status before reset Table 6 The Status of RST, T and P being Affected by Events Event Power-on WDTC instruction WDT time-out SLEP instruction Wake-up on pin changed during SLEEP mode T P 1 1 0 1 1 1 1 *P 0 0 *P
EM78P458/459 OTP ROM 4.6 Interrupt The EM78P458/459 has six interrupts as listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change Interrupt (3) External interrupt [(P50, /INT) pin]. (4) Analog to Digital conversion completed. (5) When TMR1/TMR2 matches with PRD1/PRD2 respectively in PWM. (6) When the comparators output change. Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is necessary.
EM78P458/459 OTP ROM Fig. 11 Interrupt Input Circuit 4.7 Analog-To-Digital Converter (ADC) The analog-to-digital circuitry consists of an 8-bit analog multiplexer, three control registers (ADCON/R9, AD-CMP-CON/IOCA0, GCON/IOC90), one data register (ADDATA/RA) and an ADC with 8-bit resolution. The functional block diagram of the ADC is shown in Fig. 12. The analog reference voltage (Vref) and analog ground are connected via separate input pins.
EM78P458/459 OTP ROM 1. ADC Control Register (ADCON/R9, AD-CMP-CON/IOCA0, GCON/IOC90) 1.1 ADCON/R9 The ADCON register controls the operation of the A/D conversion and decides which pin should be currently active. BIT SYMBOL *Init_Value 7 0 6 0 5 IOCS 0 4 ADRUN 0 3 ADPD 0 2 ADIS2 0 1 ADIS1 0 0 ADIS0 0 *Init_Value: Initial value at power on reset • ADRUN (bit 4): ADC starts to RUN. 1 = an A/D conversion is started. This bit can be set by software. 0 = reset on completion of the conversion.
EM78P458/459 OTP ROM 0 = The Vref of the ADC is connected to Vdd (default value), and the P53/VREF pin carries out the function of P53; 1 = The Vref of the ADC is connected to P53/VREF. • CE (Bit 6): Control bit used to enable comparator. 0 = Disable comparator 1 = Enable comparator • COE (Bit 5): Set P57 as the output of the comparator 0 = the comparator acts as an OP if CE=1. 1 = act as a comparator if CE=1. • IMS2~IMS0 (Bit 4 ~ Bit 2): ADC configuration definition bit.
EM78P458/459 OTP ROM When the A/D conversion is complete, the result is loaded to the ADDATA. The START/END bit is clear, and the ADIF is set. 3. A/D Sampling Time The accuracy, linearity, and speed of the successive approximation A/D converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor.
EM78P458/459 OTP ROM (1) Write to the three bits (IMS2:IMS0) on the AD-CMP-CON1 register to define the characteristics of R6: Digital I/O, analog channels, and voltage reference pin; (2) Write to the ADCON register to configure AD module: (a) Select A/D input channel ( ADAS2:ADAS0 ); (b) Select the proper gains by writing to the GCON register ( optional ); (c) Define A/D conversion clock rate ( CKR1:CKR0 ); (d) Set the ADPD bit to 1 to begin sampling.
EM78P458/459 OTP ROM ;ADC Control Registers ADDATA == 0xA ; The contents are the results of ADC ADCON R== 0x9 ; 7 6 ; - - ADCONC== 0xA GCON == 0x9 5 4 2 1 0 IOCS ADRUN ADPD ADIS2 ADIS1 ADIS0 ; 7 6 5 ; VREFS X X ; 7 6 ; OPE2 3 4 3 IMS2 IMS1 5 OPE1 G22 4 G21 3 G20 2 1 0 IMS0 CKR1 CKR0 2 G12 1 0 G11 G10 ;To define bits ;In ADCONR ADRUN == 0x4 ; ADC is executed as the bit is set ADPD == 0x3 ; Power Mode of ADC ORG 0 ; Initial address JMP INITIAL ; ORG 0x08 ; Inte
EM78P458/459 OTP ROM CONTW MOV A, @0B00000000 ; To employ Vdd as the reference voltage, to define P60 as IOW ADCONC ; an analog input and set clock rate at fosc/4 En_ADC: MOV A, @0BXXXXXXX1 ; To define P60 as an input pin, and the others are dependent IOW PORT6 ; on applications MOV A, @0B01000101 ; To enable the OP1, and set the gain as 32 IOW GCON BS ADCONR, ADPD ; To disable the power-down mode of ADC ENI ; Enable the interrupt function BS ADCONR, ADRUN ; Start to run the ADC ; If the in
EM78P458/459 OTP ROM DL1H + DL1L DT1H + DT1L Fosc 1:2 1:8 1:32 1:64 latch To PW M 1IF Duty Cycle M atch Com parator PW M 1 M UX R TM R1H + TM R1L reset Q S IOC51 Com parator T1P0 T1P1 T1EN Period M atch PRD1 Data Bus Data Bus DL2H + DL2L DT2H + DT2L T2P0 T2P1 T2EN latch Com parator To PW M 2IF Duty Cycle M atch PW M 2 Fosc 1:2 1:8 1:32 1:64 TM R2H + TM R2L R reset M UX Q S IOC51 Com parator Period M atch PRD2 Fig.
EM78P458/459 OTP ROM 3. PWM Period ( PRDX : PRD1 or PRD2 ) The PWM period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the following events occur on the next increment cycle: • TMRX is cleared. • The PWMX pin is set to 1. • The PWM duty cycle is latched from DT1/DT2 to DTL1/DTL2. < Note > The PWM output will not be set, if the duty cycle is 0; • The PWMXIF pin is set to 1.
EM78P458/459 OTP ROM 4.9 Timer 1. Overview Timer1 (TMR1) and Timer2 (TMR2) (TMRX) are 10-bit clock counters with programmable prescalers, respectively. They are designed for the PWM module as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions. 2. Function description Fig. 15 shows TMRX block diagram.
EM78P458/459 OTP ROM ComparatorX ( Comparator 1 and Comparator 2 ): To reset TMRX while a match occurs and the TMRXIF flag is set at the same time. 3. Programming the Related Registers When defining TMRX, refer to the related registers of its operation as shown in Table 9.It must be noted that the PWMX bits must be disabled if their related TMRXs are employed. That is, bit 7 and bit 6 of the PWMCON register must be set to ‘0’.
EM78P458/459 OTP ROM • The compared result is stored in the CMPOUT of R3. • The comparator outputs is output to P57 by programming bit5 of the AD-CMPCON register to 1. • P57 must be defined as an output if implemented as the comparator output. • Fig. 17 shows the comparator output block diagram. To C0 From OP I/O CMRD EN Q EN D Q D To CMPOUT RESET To CPIF CMRD From other comparator Fig. 17 The Output Configuration of a Comparator 3.
EM78P458/459 OTP ROM • If enabled, the comparator remains active and the interrupt remains functional, even under SLEEP mode. • If a mismatch occurs, the interrupt will wake up the device from SLEEP mode. • The power consumption should be taken into consideration for the benefit of energy conservation. • If the function is unemployed during SLEEP mode, turn off comparator before entering into sleep mode. 4.
EM78P458/459 OTP ROM Address Name N/A IOC71 (DT1H) N/A IOC81 (PRD1) N/A IOC91 (DT2L) N/A IOCA1 (DT2H) N/A IOCB1 (PRD2) N/A IOCC1 (DL1L) N/A IOCD1 (DL1H) N/A IOCE1 (DL2L) N/A IOCF1 (DL2H) N/A CONT 0x00 R0(IAR) 0x01 R1(TCC) 0x02 R2(PC) 0x03 R3(SR) 0x04 R4(RSR) Reset Type Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Po
EM78P458/459 OTP ROM Address Name 0x05 P5 0x06 P6 0x7~0x8 R7~R8 0x9 R9 (ADCON) 0xA RA (ADDDATA) 0xB RB (TMR1L) 0xC RC (TMR1H) 0xD RD (TMR2L) 0xE RE (TMR2H) 0xF RF (ISR) 0x10~0x3F R10~R3F Reset Type Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT
EM78P458/459 OTP ROM MASK Option. The up-limited operation frequency of crystal/resonator on the different VDDs is listed in Table 11 Table 12 The Summary of Maximum Operating Speeds Conditions Two clocks VDD 2.3 3.0 5.0 Fxt max.(MHz) 4 8 20 2. Crystal Oscillator/Ceramic Resonators (XTAL) EM78P458/459 can be driven by an external clock signal through the OSCI pin as shown in Fig. 18 below. Ext. Clock OSCI EM78P458 EM78P459 OSCO Fig.
EM78P458/459 OTP ROM Table 13 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Type Frequency Mode Ceramic Resonators HXT Frequency 455 kHz 2.0 MHz 4.0 MHz 32.768kHz 100KHz 200KHz 455KHz 1.0MHz 2.0MHz 4.0MHz LXT Crystal Oscillator HXT C1(pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 330 C2(pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15 330 OSCI 7404 7404 C EM78P458 EM78P459 7404 XTAL Fig. 20 Circuit for Crystal/Resonator-Series Mode 4.
EM78P458/459 OTP ROM 3. External RC Oscillator Mode For some applications that do not require precise timing calculation, the RC oscillator (Fig. 22) could offer users with an effective cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor(Cext), and even by the operation temperature.
EM78P458/459 OTP ROM 100 pF 3.3k 5.1k 10k 100k 1.43 MHz 980 KHz 520 KHz 57 KHz 1.35 MHz 877 KHz 465 KHz 54 KHz 300 pF 3.3k 5.1k 10k 100k 510 KHz 340 KHz 175 KHz 19 KHz 470 KHz 320 KHz 170 KHz 19 KHz 1. Measured on DIP packages. 2. Design reference only 4. RC Oscillator Mode with Internal Capacitor If both precision and cost are taken into consideration, EM78P257A/B also offers a special oscillation mode. It is equipped with an internal capacitor and an external resistor (connected to Vcc).
EM78P458/459 OTP ROM 4.13 Power-on Considerations Any microcontroller is not warranted to start proper operation before the power supply stabilizes in steady state. EM78P458/459 POR voltage range is 1.2V~1.8V. Under customer application, when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power can be switched ON again. This way, the EM78P458/459 will reset and work normally. The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less).
EM78P458/459 OTP ROM VDD VDD EM78P458 EM78P459 33K Q1 10K /RESET 100K Fig. 25 1N4684 Circuit 1 for the Residue Voltage Protection VDD VDD EM78P458 EM78P459 R1 Q1 /RESET R2 R3 Fig. 26 Circuit 2 for the Residue Voltage Protection 4.14 CODE OPTION EM78P458/459 has one CODE option word and one Customer ID word that are not a part of the normal program memory. Word 0 Bit12~Bit0 Code option12~0 Word 1 Bit12~Bit0 Code option12~0 1.
EM78P458/459 OTP ROM 1: XTAL type • Bit 11 (/ENWTD): Watchdog timer enable bit. 0: Enable 1: Disable • Bit 10 (CLKS): Clocks of each instruction cycle. 0: Two clocks 1: Four clocks Refer to the section of Instruction Set. • Bit 9 (/PTB): Protect bit. 0: Enable 1: Disable • Bit 8 (HLF): XTAL frequency selection. 0: Low frequency 1: High frequency • Bit 7 (RCT): Resistor Capacitor 0: Inter C, External R 1: External RC • Bit 6 (HLP): Power consumption selection. 0: Low power. 1: High power.
EM78P458/459 OTP ROM 4.15 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅).
EM78P458/459 OTP ROM INSTRUCTION BINARY 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr HEX 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr MNEMONIC ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr 06rr RLC R 0 0111 00rr rrrr 07rr SWAPA R 0 0 0
EM78P458/459 OTP ROM 4.16 Timing Diagrams AC Test Input/O utput W aveform 2.4 2.0 0.8 TEST POIN TS 2.0 0.8 0.4 AC T esting : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Tim ing m easurem ents are m ade at 2.0V for logic "1",and 0.8V for logic "0". RESET Tim ing (CLK="0") NO P Instruction 1 Executed CLK /RESET T drh TCC Input Tim ing (CLKS="0") T ins CLK T CC T tcc This specification is subject to change without prior notice. 55 07.01.2003 (V1.
EM78P458/459 OTP ROM 5. ABSOLUTE MAXIMUM RATINGS Items Temperature under bias Storage temperature Input voltage Output voltage Rating to to to to 0°C -65°C -0.3V -0.3V This specification is subject to change without prior notice. 56 70°C 150°C +6.0V +6.0V 07.01.2003 (V1.
EM78P458/459 OTP ROM 6. ELECTRICAL CHARACTERISTICS 6.1 DC Electrical Characteristic(Ta=0°C ~ 70 °C, VDD=5.0V±5%, VSS=0V) Symbol Fxt IIL VIH1 VIL1 VIHT1 VILT1 VIHX1 VILX1 VIH2 VIL2 VIHT2 VILT2 VIHX2 VILX2 VOH1 VOL1 VOL2 IPH IPD ISB ISB ICC1 ICC2 ICC3 ICC4 Parameter Condition Min XTAL: VDD to 3V DC Two cycle with two clocks XTAL: VDD to 5V DC RC: VDD to 5V R: 5.1KΩ, C: 100pF F±30% Input Leakage Current for input pins VIN = VDD, VSS Input High Voltage,VDD=5V Ports 5, 6 2.
EM78P458/459 OTP ROM 6.
EM78P458/459 OTP ROM IVR Input voltage range OVS Output voltage swing Iop Supply current of OP Power-supply Rejection Ration for OP Offset voltage Operating range PSRR Vos Vs Vdd =5.0V, VSS =0.0V Vd =5.0V, VSS =0.0V,RL=10KΩ Vdd= 5.0V, VSS =0.0V 0 0 4.7 250 0.2 4.8 350 5 0.3 5 500 uA 50 60 70 dB ±10 ±20 5.5 mV V Vdd= 5.0V, VSS =0.0V 2.5 V V Note: 1.These parameters are characterized but not tested. 2.These parameters are for design guidance only and are not tested. 3.
EM78P458/459 OTP ROM APPENDIX Package Types: OTP MCU EM78P458AP EM78P458AM EM78P459AK EM78P459AM Package Type DIP SOP Skinny DIP SOP This specification is subject to change without prior notice. Pin Count 20 pin 20 pin 24 pin 24 pin 60 Package Size 300mil 300mil 300mil 300mil 07.01.2003 (V1.