Specifications

ManualsBrandsElan ManualsAmplifierA12

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product

without notice.

Publication# 20668 Rev: B Amendment/0

Issue Date: October 1997

Élan

™

SC310

Single-Chip, 32-Bit, PC/AT Microcontroller

DISTINCTIVE CHARACTERISTICS

n Highly integrated, single-chip CPU and system

logic

– Optimized for embedded PC applications

– Combines 32 bit, x86 compatible, low-voltage

CPU with memory controller, PC/AT peripheral

controllers, real-time clock, and PLL clock

generators

– 0.7 micron, low-voltage, CMOS process, fully

static

n Enhanced Am386

SXLV CPU core

– 25 MHz or 33 MHz operating frequencies

– 3.3 V core, 3.3 V or 5 V memory and I/O

– Low-power, fully static design for long battery life

– System Management Mode (SMM) for power

management control

n Integrated power management functions

– Internal clock generators (using multiple Phase-

Locked Loops and one external 32-KHz crystal)

– Supports CPU System Management Mode

(SMM)

– Multiple operating modes: High Speed PLL, Low

Speed PLL, Doze, Sleep, Suspend, and Off. Fully

static design allows stopped clock.

– Comprehensive control of system and peripheral

clocks

– Five external power management control pins

– Suspend refresh of DRAM array

– Clock switching during ISA cycles

– Low power consumption: 0.12 mW typical

Suspend mode power

– Simultaneous multiple-voltage I/O pads operate

at either 3.3 V or 5 V. Core operates at 3.3 V for

minimum power consumption.

n Integrated memory controller

– Controls symmetrically addressable DRAM or

asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit

DRAM or SRAM as main memory

– Zero wait-state access with 70 ns, Page mode

DRAMs

– Supports up to 16 Mbyte system memory

– Supports up to 16 Mbyte of application ROM/

Flash, and 320 Kbyte direct ROM BIOS access.

Also supports shadow RAM

– Fully PC/AT compatible

n Integrated PC/AT-lompatible leripheral logic

– One programmable interval timer (fully 8254

compatible)

– Two programmable interrupt controllers (8259A

compatible)

– Two DMA controllers (8237A compatible)

– Built-in real-time clock (146818A compatible),

with an additional 114 bytes of RAM

– Internal Phase-Locked Loops (PLL) generate all

clocks from single 32.768 kHz crystal input

n Bus configurations

– 16-bit data path

– Optional bus configurations:

— 386 Local Bus mode with subset ISA

— Maximum ISA Bus mode

– Four programmable chip selects

– Built-in 8042 chip select

n Serial port controller (16450 UART compatible)

n Bidirectional parallel port (EPP compliant)

Summary of content (119 pages)

PAGE 1
PRELIMINARY Élan™SC310 Single-Chip, 32-Bit, PC/AT Microcontroller DISTINCTIVE CHARACTERISTICS n Highly integrated, single-chip CPU and system logic – Optimized for embedded PC applications – Combines 32 bit, x86 compatible, low-voltage CPU with memory controller, PC/AT peripheral controllers, real-time clock, and PLL clock generators – 0.7 micron, low-voltage, CMOS process, fully static n Enhanced Am386®SXLV CPU core – 25 MHz or 33 MHz operating frequencies – 3.3 V core, 3.
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P R E L I M I N A R Y GENERAL DESCRIPTION The ÉlanSC310 microcontroller is a highly integrated, low-voltage, single-chip implementation of the Am386SXLV microprocessor plus most of the additional logic needed for an AT-compatible personal computer. It is ideal for embedded PC applications, such as point-of-sale equipment, web appliances, industrial controls, and communication equipment.
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P R E L I M I N A R Y BLOCK DIAGRAM SA11–SA0 IOR, IOW, MEMR, MEMW, BALE D15–D0 A20GATE, RC MCS16, IOCS16, IOCHRDY, 0WS 8042CS, SYSCLK DACKx, TC, AEN DREQx DMA Controller (2x8237A-5) Bus Controller Local Bus Controller A23–A12, ADS, D/C,M/IO, W/R, BHE, BLE, CPUCLK, CPURST, CPURDY LRDY, LDEV Memory Controller RAS, CAS, MWE PD15–PD0 Am386SXLV PA23–PA0 M U X CONTROL Mapping Registers LFX MA11/SA12– MA0/SA23 PGP3–PGP0 X32IN Clock Generators Power Management Control Unit PMCx ACIN, BLx, EX
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P R E L I M I N A R Y ORDERING INFORMATION AMD standard products are available in several packages and operating ranges. The order numbers (Valid Combinations) are formed by a combination of the elements below.
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P R E L I M I N A R Y TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 2 Customer Service ........................................................................................................................ 2 Block Diagram ......................................
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P R E L I M I N A R Y PPDWE [PPDCS].................................................................................................................. 33 PPOEN.................................................................................................................................. 33 SLCT ..................................................................................................................................... 33 SLCTIN ......................................................................
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P R E L I M I N A R Y Reset and Power ....................................................................................................................... 37 AGND.................................................................................................................................... 37 AVCC .................................................................................................................................... 37 GND .................................................................
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P R E L I M I N A R Y LIST OF FIGURES Figure 1. PLL Block Diagram .................................................................................................. 42 Figure 2. Clock Steering Block Diagram ................................................................................. 43 Figure 3. Typical System Design with Secondary Power Supply to Maintain RTC When Primary Power Supply is Off (DRAM Refresh is Optional.)...................................... 47 Figure 4.
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P R E L I M I N A R Y LIST OF TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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A D V A N C E Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. 10 I N F O R M A T I O N Local Bus Interface .................................................................................................. 98 BIOS ROM Read/Write 8-Bit Cycle........................................................................ 100 DOS ROM Read/Write 8-Bit Cycle.........................................................................
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P R E L I M I N A R Y 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 AGND LF4 Video PLL LF3 Low Speed PLL LF2 Internal PLL LF1 High Speed PLL AVCC X32OUT X32IN X1OUT [BAUD OUT] JTAGEN IRQ14 MCS16 IOCS16 IRQ1 PIRQ0 (IRQ3) PIRQ1 (IRQ6) IOCHRDY GND LPH PGP0 PGP1 PGP2 PGP3 PMC3 PMC4 PULLUP IRQ15 IRQ12 VCC PULLUP(IRQ10) PULLDN(IRQ5) IOCHCHK VCC1 DRQ5 D
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P R E L I M I N A R Y ÉLANSC310 MICROCONTROLLER PIN DESIGNATIONS This section, beginning with the Connection Diagram on the preceding page, identifies the pins of the ÉlanSC310 microcontroller and lists the signals associated with each pin. Tables 2–10, beginning on page 22, group these signals according to function.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NUMBER) Pin No. Signal Name (Alternate Functions) Pin No. Signal Name (Alternate Functions) Pin No.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NUMBER) (CONTINUED) Pin No. 14 Signal Name (Alternate Functions) Pin No. Signal Name (Alternate Functions) Signal Name (Alternate Functions) Pin No.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NAME) Signal Name Pin No. Function Pin State Table No. Description Page No.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. Function Pin State Table No. Description Page No.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. Function Pin State Table No. Description Page No.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. Function Pin State Table No. Description Page No.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. Function Pin State Table No. Description Page No.
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P R E L I M I N A R Y PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED) Signal Name Pin No. Function Pin State Table No. Description Page No.
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P R E L I M I N A R Y PIN STATE TABLES The Pin State tables beginning on page 22 are grouped by function based on their primary function when the ÉlanSC310 microcontroller is configured at reset for the internal LCD Controller mode (NAME1). The Pin State tables also show the I/O type and reset state for those pins that have been configured at reset for either Local Bus mode or Maximum ISA Bus mode.
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P R E L I M I N A R Y Table 2. Memory Bus Interface Pin No. I/O Type Drive Type Clock Off RAS01,3 2 O E,D,C RAS11,3 3 O CAS1L [SRCS2]1,2 4 CAS1H [SRCS3]1,2 Signal Name Term Reset State (volts) VCCIO VCC Clamp Spec. Load (pF) Local Bus Max ISA Active 3.3/0 3.3/0 VMEM VMEM 50 E,D,C Active 3.3/0 3.3/0 VMEM VMEM 50 O D Active 3.3/0 3.3/0 VMEM VMEM 30 5 O D Active 3.3/0 3.3/0 VMEM VMEM 30 CAS0L [SRCS0]1,2 6 O D Active 3.3/0 3.
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P R E L I M I N A R Y Table 3. System Interface Pin No. I/O Type MA11/SA12 60 O E SA11 61 O SA10 62 SA9 Signal Name Term Drive Type Clock Off Reset State (volts) VCCIO VCC Clamp Spec. Load (pF) Local Bus Max ISA 0 5.0 5.0 VSYS VCC5 70 D 0 5.0 5.0 VSYS VCC5 70 O D 0 5.0 5.0 VSYS VCC5 70 63 O D 0 5.0 5.0 VSYS VCC5 70 SA8 64 O D 0 5.0 5.0 VSYS VCC5 70 SA7 66 O D 0 5.0 5.0 VSYS VCC5 70 SA6 67 O D 0 5.0 5.
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P R E L I M I N A R Y Table 3. Pin No. I/O Type TC [TMS] 49 ENDIRL ENDIRH System Interface (Continued) Term Drive Type Clock Off O(I) — B 50 O — 51 O — DBUFOE 59 O IOR 54 IOW MEMR Signal Name Reset State (volts) VCCIO VCC Clamp Spec. Load (pF) Local Bus Max ISA 0 0.0 0.0 VSYS VCC5 30 B 1 5.0 5.0 VSYS VCC5 30 B 1 5.0 5.0 VSYS VCC5 30 — B 1 5.0 5.0 VSYS VCC5 30 O — C 1 5.0 5.0 VSYS VCC5 50 55 O — C 1 5.0 5.
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P R E L I M I N A R Y Table 5. Parallel Port Interface Pin No. I/O Type Term Drive Type Clock Off AFDT [X14OUT]1 80 O — D INIT1 89 O — STRB1 83 O SLCTIN1 84 ACK BUSY2 Signal Name Reset State (volts) VCCIO VCC Clamp Spec. Load (pF) Local Bus Max ISA Last state 5.0 5.0 VCC5 VCC5 100 D Last state 0.0 0.0 VCC5 VCC5 100 — D Last state 5.0 5.0 VCC5 VCC5 100 O — D Last state 5.0 5.0 VCC5 VCC5 100 88 I — — — 5.0 5.0 VCC5 VCC5 — 85 I — — — 5.
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P R E L I M I N A R Y Table 7. Power Management Interface Pin No. I/O Type Term Drive Type Clock Off ACIN 101 STI PD — EXTSMI 102 STI PD SUS/RES 103 STI PMC41 184 PMC31 Signal Name Reset State (volts) VCCIO VCC Clamp Spec. Load (pF) Local Bus Max ISA — 0.0 0.0 VCC5 VCC5 — — — 0.0 0.0 VCC5 VCC5 — — — — 5.0 5.0 VCC5 VCC5 — O — B Active 0.0 0.0 VCC1 VCC5 50 185 O — B Active 3.3 3.3 VCC1 VCC5 50 PMC21 77 O — B Active 0.0 0.
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P R E L I M I N A R Y Table 8. Local Bus Interface (Continued) Pin No. I/O Type Term Drive Type Clock Off A20 (LA20) 152 O — C A19 (LA19) 153 O — A18 (LA18) 154 O A17 (LA17) 155 A16 (DACK0) 158 A15 (DACK3) Signal Name Reset State (volts) VCCIO VCC Clamp Spec. Load (pF) Local Bus Max ISA 0 3.3 5.0 VSYS2 VCC5 50 C 0 3.3 5.0 VSYS2 VCC5 50 — C 0 3.3 5.0 VSYS2 VCC5 50 O — C 0 3.3 5.0 VSYS2 VCC5 50 O — C (0/1) 3.3 5.
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P R E L I M I N A R Y Table 9. Miscellaneous Interface Pin No. I/O Type Term Drive Type Clock Off IORESET1 140 I — — X32IN2 201 I — X32OUT3 202 O LF1 204 LF2 Signal Name Reset State (volts) VCCIO VCC Clamp Spec. Load (pF) Local Bus Max ISA — 0.0 0.0 VCC5 VCC5 — — — 920/0 920/0 AVCC AVCC — — osc. Active 1.68/0 1.68/0 AVCC AVCC — A — — — 1.52 1.52 AVCC AVCC — 205 A — — — 1.48 1.48 AVCC AVCC — LF3 206 A — — — 1.52 1.
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P R E L I M I N A R Y All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO. Table 10. Power Pins Signal Name Pin No. I/O Type Term Drive Clock Type Off Reset State (volts) Local Bus Max ISA VCCIO VCC Clamp Spec. Load (pF) AVCC1 203 — — — — 3.3 3.3 — — — VCC1 23, 81, 135,180 — — — — 3.3 3.3 — — — VCC51 95, 128 — — — — 5.0 5.0 — — — VSYS21 142 — — — — 3.3 5.0 — — — VSYS1 48, 65 — — — — 5.0 5.
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P R E L I M I N A R Y PIN DESCRIPTIONS Descriptions of the ÉlanSC310 microcontroller pins are organized into the following functional groupings: n Power management interface n Memory bus interface n Local bus interface n System interface n Maximum ISA bus interface n Keyboard interface n JTAG-boundary scan interface n Parallel port interface n Reset and power n Miscellaneous interface n Serial port interface MEMORY BUS INTERFACE CAS1H [SRCS3], CAS1L [SRCS2], CAS0H [SRCS1], CAS0L [SRCS0] as sho
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P R E L I M I N A R Y SYSTEM INTERFACE ENDIRH AEN [TDI] High Byte Data Buffer Direction Control (Output; Active High) DMA Address Enable (Output; Active High) AEN is used to indicate that the current address active on the SA23–SA0 address bus is a memory address and that the current cycle is a DMA cycle. All I/O devices should use this signal in decoding their I/O addresses and should not respond when this signal is asserted.
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P R E L I M I N A R Y IRQ1, IRQ14 RSTDRV Interrupt Request Channels 1 and 14 (Input; Rising Edge/Active High, with Internal Pullup) System Reset (Output; Active High) This input is connected to the internal 8259A-compatible Interrupt Controller Channels 1 and 14. In PC-compatible systems, IRQ1 may be connected to the 8042 keyboard controller. MCS16 This signal is the ISA-compatible reset signal. When this signal is asserted, all connected devices reinitialize to their reset state.
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P R E L I M I N A R Y compatibility. In PC-compatible systems, this signal can be driven by an 8042 keyboard controller, port 2, bit 1. For detailed information about the A20GATE signal, see the ÉlanTMSC300 and ÉlanSC310 Microcontrollers GATEA20 Function Clarification Application Note, order #21811. PE Paper End (Input; Active High) The printer asserts this signal when it is out of paper. PPDWE [PPDCS] Parallel Port Write Enable (Output; Active Low) This signal resets the internal CPU.
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P R E L I M I N A R Y DTR/CFG1 Data Terminal Ready (Output; Active Low) condition. These inputs can be used to force the system into one of the power saving modes when activated, as follows: This signal indicates to the external serial device that the internal serial port controller is ready to communicate. n BL1 can be programmed to force the system to go to Low Speed PLL mode or to generate an SMI. The state of this signal is used to determine the pin configuration at power-up.
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P R E L I M I N A R Y are asserted Low immediately after reset, and the PMC3 signal is asserted High immediately after reset. Each of the PMC pins can then be programmed to be High or Low for each of the ÉlanSC310 microcontroller power management modes.
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P R E L I M I N A R Y LRDY Local Bus Device Ready (Input; Active Low) Note: The DACK1, DACK2, and DACK5 signals are also available in Local Bus mode. This signal is used by the local bus devices to terminate the current bus cycle. DRQ7, DRQ6, DRQ5, DRQ3, DRQ2, DRQ1, DRQ0 M/IO DMA Request signals are asynchronous DMA channel request inputs used by peripheral devices to gain access to a DMA service.
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P R E L I M I N A R Y JTAG BOUNDARY SCAN INTERFACE RESET AND POWER The ÉlanSC310 microcontroller provides an IEEE Std 1149.1-1990 (JTAG) compliant Standard Test Access Port (TAP) and Boundary-Scan Architecture. See “Voltage Partitioning” on page 84 for more information about power. The boundary-scan test logic consists of a boundary scan register and support logic that are accessed through the TAP.
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P R E L I M I N A R Y VCC VMEM 3.3 V DC Supply Pins 3.3 V or 5 V Supply Pins These supply pins provide power to the ÉlanSC310 microcontroller core. Refer to AC Characteristics for VCC power up timing restrictions. These supply pins provide power to the Memory Interface and Data Bus pins (D15–D0). These pins must be connected to the same DC supply as the system DRAMs. The VCC pins are required for battery backup.
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P R E L I M I N A R Y one page is spread across both DRAM banks. Both DRAM modes use standard Fast Page mode DRAMs. the upper system address lines SA12–SA23 to reduce pin count. This signal sharing is shown in Table 13. The memory controller operation is synchronous with respect to the CPU. This ensures maximum performance for all transfers to local memory. The clock stretching implemented by the clock generation circuitry works to reduce synchronous logic power consumption.
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P R E L I M I N A R Y Table 15.
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P R E L I M I N A R Y SRAM Table 17. SRAM Access Pins When using SRAM instead of DRAM for main memory, up to 16 Mbyte can be accessed, the SRAM being organized as one or two banks. Each bank is 16 bits wide and is provided with a low and high byte select. An SRAM memory interface is selected by setting bit 0 of the Miscellaneous 6 Register, Index 70h. If this is done, CAS1H, CAS1L, CAS0H, and CAS0L will have their alternate function as SRAM chip select pins 3–0 (SRCS3–SRCS0).
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P R E L I M I N A R Y management control (PMC) pins that are controlled by the operating modes. Clock Generation The ÉlanSC310 microcontroller requires only one 32.768-kHz clock input that is used to generate all other clock frequencies required by the system. This 32.768-kHz clock input is provided through the X32IN and X32OUT pins and the crystal oscillator circuit. This input frequency is then used to internally drive multiple Phase-Locked Loops that create all necessary frequencies.
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P R E L I M I N A R Y (ISA Cycle) + (DMA Cycle) + (Low Speed) 2 x CPU Clock 0 2 x CPU/Local Bus Clock 1 High Speed PLL (I4) ÷2 18.432 9.216 18.432 MHz Divide Chain 4.608 2.304 1.152 I4 S2 ÷4 I3 I2 I1 ÷2 I0 Internal SYSCLK DMA Clock External SYSCLK S[1:0] Programmable Low Speed (I0–I3) (Low-Speed PLL mode only) Figure 2.
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P R E L I M I N A R Y In the PLL Block Diagram, the INT_PLL is the Intermediate PLL, and is used to multiply the 32.768-kHz input frequency by 45 to produce a 1.4746-MHz input for use by the LS_PLL and the VID_PLL. The LS_PLL, or LowSpeed PLL, is used to again multiply the 1.4746-MHz input by 25 to produce a 36.864-MHz output. This output of the LS_PLL is then divided down to provide the frequencies shown in Table 20. The LS_PLL also generates a 2.
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P R E L I M I N A R Y Table 21. PMU Modes Mode Description Power On After Power-on reset, system enters High-Speed PLL mode. High-Speed PLL The system will be in this mode as long as activities are detected by activity monitor (described in the Programmable Activity Mask Registers, Indexes 08h, 75h, and 76h). Low-Speed PLL The system will enter this mode from High-Speed PLL mode after a programmable 1/512 s to 1/2 s, or 1/16 s to 16 s of inactivity.
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P R E L I M I N A R Y asserted Low and PMC3 is asserted High. Prior to this edge, these signals are undefined. The ÉlanSC310 microcontroller can be programmed to reset a timer when an I/O access to a preset address range is detected. If no I/O activity in that range occurs before the timer expires, the ÉlanSC310 microcontroller can assert a PMC signal to turn off the device.
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P R E L I M I N A R Y Power Supply Swapping Circuit AVCC Analog ISA/LOCAL ISA On/Off Secondary Power Supply + - R RESIN C L O C A L RTC M E M O R Y PMU VCC (Core) 3.3 V IORESET ÉlanSC310 Microcontroller 5V ISA and Misc. Parallel/Serial Power Management Primary Power Supply Main Battery ACIN Figure 3. Typical System Design with Secondary Power Supply to Maintain RTC When Primary Power Supply is Off (DRAM Refresh is Optional.) The RESIN pin acts as the master reset.
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P R E L I M I N A R Y The ÉlanSC300 microcontroller samples the two reset inputs (RESIN and IORESET) to logically determine what state the power pins are in; and, in turn, controls the internal pull-down resistors. Note that in Micro Core Logic Power Off mode, the IORESET input should be terminated with a pull-down resistor if not driven Low by an external device (see Table 23 on page 50 for more information about internal I/O pull-down states).
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P R E L I M I N A R Y The Micro Power Refresh bit will always be cleared whenever the RESIN input is sampled Low. Therefore, when the core is initially powered up, the Micro Power DRAM refresh feature will be disabled. This bit is unaffected by the IORESET input. This bit will provide the system BIOS with a mechanism to determine whether or not the system DRAM data has been retained after a reset (IORESET) has occurred.
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P R E L I M I N A R Y Table 23. Internal I/O Pulldown States IORESET RESIN Force Term Comments 0 0 Active This condition occurs when any power source is initially turned on. The ÉlanSC310 microcontroller’s core and analog VCC is transitioning to on and RESIN is active (the initial power-up state). See “Micro Power Off Mode” on page 46 for more details.
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P R E L I M I N A R Y served for the coprocessor in a PC/AT system and is unavailable on the ÉlanSC310 microcontroller. The other interrupts are available to external peripherals as in the PC/AT architecture via the IRQ15, IRQ14, IRQ12–IRQ9, IRQ7–IRQ3, and IRQ1 inputs. Other sources of interrupts are SMI/NMI and the PIRQ1– PIRQ0 inputs. It can be programmed to count in binary or in Binary Coded Decimal (BCD).
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P R E L I M I N A R Y data onto the parallel port data bus, as shown in Figure 5. Table 24. Parallel Port EPP Mode Pin Definition Normal Mode EPP Mode STRB WRITE EPP write signal. This signal is driven active during writes to the EPP data or address register. AFDT DSTRB EPP data strobe. This signal is driven active during reads or writes to the EPP data register. SLCTIN ASTRB EPP address strobe. This signal is driven active during reads or writes to the EPP address register.
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P R E L I M I N A R Y 373 Octal D Transparent Latch D SD7–SD0 Q Parallel Port Data Bus EN OE PPOEN PPDCS 244 type buffer IOW Y A ENB IOR Figure 6. The ÉlanSC310 Microcontroller Bidirectional Parallel Port and EPP Implementation Parallel Port Anomalies General The ÉlanSC310 microcontroller parallel port can be physically mapped to three different I/O locations or can be completely disabled. These I/O locations are 3B(x)h, 37(x)h, and 27(x)h.
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P R E L I M I N A R Y ister at I/O address 070h. The default value for the NMI enable bit is 1, which inhibits NMI generation. The NMI enable bit (7) is a write-only bit, and is active Low. The remaining bits of the register located at 070h (6–0) control the RTC function. Because the RTC portion of this register is only 7 bits wide and is also write only, there is no conflict between the two functions.
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P R E L I M I N A R Y 1 Mbyte System Memory 3.3 V or 5 V CRT MA10–MA0 512K x 8 D15–D8 ISA VGA MA10–MA0 512K x 8 D7–D0 RAS CAS WE Serial Port MA10–MA0 D15–D0 MAX241 SA23–SA13 B SD15–SD0 U F Élan SC310 Microcontroller SA12–SA0 ROM/FLASH BIOS ROM/FLASH DOS Control Keyboard Controller (8042) L A T C H Miscellaneous I/O Control Parallel Port Figure 7.
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P R E L I M I N A R Y Local Bus or Maximum ISA Bus Controller D e p e n d i n g o n t h e c o n fi g u r a t i o n c h o s e n , th e ÉlanSC310 microcontroller’s pin functionality will differ. The two different options are Local Bus and Maximum ISA Bus modes. The pin options are selected upon power-up reset. (See “Alternate Pin Functions” on page 59.) Only Local Bus or Maximum ISA Bus mode is available in a particular design. Local bus mode does, however, provide a subset of the ISA bus.
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P R E L I M I N A R Y Table 25. External Resistor Requirements (Continued) Local Bus Signal Name Pin No.
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P R E L I M I N A R Y Table 25. External Resistor Requirements (Continued) Local Bus Signal Name Pin No. Pull Up Pull Down Maximum ISA Pull Up Pull Down Notes ERROR 86 4.7K 4.7K ACK 88 4.7K 4.7K BUSY 85 4.7K 4.7K PE 82 4.7K 4.7K SLCT 87 4.7K PGP0 189 100K 100K 4 PGP1 188 100K 100K 4 ACIN 101 10K 10K 3 BL1 106 100K 100K 3 BL2 107 100K 100K 3 BL3 108 100K 100K 3 BL4 109 100K 100K 3 SOUT 94 10K 4.
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P R E L I M I N A R Y ALTERNATE PIN FUNCTIONS To provide the system designer with the most flexibility, the ÉlanSC310 microcontroller provides a means for reconfiguring some of the pin functions, depending on the system requirements. Reconfiguration of the ÉlanSC310 microcontroller pin functions is accomplished in one of two ways, depending on the pin functions that are to be reconfigured.
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P R E L I M I N A R Y Maximum ISA Interface versus Local Bus Interface The maximum ISA interface alternate functions are configured via the DTR and RTS pin states when the ÉlanSC310 microcontroller is reset. Table 27. Pins Shared Between Maximum ISA Bus and Local Bus Interface Functions ISA Interface Pin Name Pin Type ISA Interface Pin Description/Notes Local Bus Mode Function Pin Name Pin No.
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P R E L I M I N A R Y ALTERNATE PIN FUNCTIONS SELECTED VIA FIRMWARE The following tables contain brief descriptions of the alternate pin functions/names and the pin names of the default function that the alternate function replaces. These alternate functions are selected via system firmware only. SRAM Interface This alternate function is configured by setting bit 0 of the Miscellaneous 6 Register, Index 70h. Table 28.
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P R E L I M I N A R Y PC/XT Keyboard The PC/XT keyboard functionality is enabled via bit 3 of PMU Control 3 Register, Index ADh. Table 31. PC/XT Keyboard Pin Name XT Keyboard Pin Description PC/XT Keyboard Pin Description/Notes Pin Type Default Pin Name/Function Pin No. [XTDAT] I/O Keyboard data 8042CS 75 [XTCLK] I/O Keyboard clock SYSCLK 45 14-MHz Clock Source Setting bit 3 of Miscellaneous 3 Register, Index BAh, enables the 14.336 MHz clock signal on the parallel port pin AFDT. Table 32.
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P R E L I M I N A R Y ISA BUS DESCRIPTIONS The two bus configuration options (local bus or maximum ISA bus) each support a somewhat different subset of the ISA bus standard. These subsets are defined in Tables 33 and 34. Table 33.
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P R E L I M I N A R Y System Test and Debug The ÉlanSC310 microcontroller provides test and debug features compatible with the standard Test Access Port (TAP) and Boundary-Scan Architecture (JTAG). The test and debug logic contains the following elements: n Five extra pins—TDI, TMS, TCK, TDO, and TRST (JTAGEN). JTAGEN is dedicated; the other four are multiplexed. n Test Access Port (TAP) controller, which decodes the inputs on the Test Mode Select (TMS) line to control test operations.
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P R E L I M I N A R Y Table 35. Boundary Scan (JTAG) Cells—Order and Type Cell Position Cell Type PMC2 1 output Pin No.
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P R E L I M I N A R Y Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Pin No.
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P R E L I M I N A R Y Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Pin No.
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P R E L I M I N A R Y Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Pin No.
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P R E L I M I N A R Y Table 35. Boundary Scan (JTAG) Cells—Order and Type (Continued) Pin No. Name Cell Position Cell Type 72 SA2 170 output 73 SA1 171 output 74 SA0 172 output 75 8042CS 173 bidir 76 DRQ2 * Notes This pin becomes TDO when JTAGEN is High. JTAG Instruction Opcodes Table 36 lists the ÉlanSC310 microcontroller’s public JTAG instruction opcodes. Note that the JTAG Instruction Register is 4 bits wide. Table 36.
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P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Storage Temperature ....................... –65°C to +150°C Supply Voltage VCC with Respect to VSS ................................–0.5 V to +7 V Ambient Temperature Under Bias ... –65°C to +125°C Voltage on Other Pins...............–0.5 V to (VCC +0.5 V) Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied.
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P R E L I M I N A R Y Table 38. DC Characteristics over Commercial and Industrial Operating Ranges (Plastic Shrink Quad Flat Pack (QFP), 33 MHz, 5 V) VCCIO = 4.5 V – 5.5 V; TAMBIENT = 0°C to +70°C (commercial); TCASE = -40° to +85°C (industrial) Preliminary Symbol fosc PCC(2) PCCSB(2) Parameter Description Min Frequency of Operation (internal CPU clock) 0 Supply Power—CPU clock = 33 MHz (VCCMEM=5 V) 660 Suspend Power—CPU idle, all internal clocks stopped except 32.768 kHz 0.
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P R E L I M I N A R Y THERMAL CHARACTERISTICS The ÉlanSC310 microcontroller is specified for operation with a case temperature range from 0°C to 85°C for a commercial device. Table 40 shows the thermal resistance for 208-pin QFP and TQFP packages. Table 40. Thermal Resistance (°C/Watt) ψJT and θJA for 208-pin QFP and TQFP packages θJA vs. Airflow-Linear ft/min. (m/s) Package ψJT 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) QFP 4.7 33 26 25 23 22 TQFP 7 37.4 31.0 28.5 26.9 26.
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P R E L I M I N A R Y DERATING CURVES This section describes how to use the derating curves on the following pages in order to determine potential specified timing variations based on system capacitive loading. The pin characteristics tables in this document (see page 21) have a column called “Spec. Load.
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P R E L I M I N A R Y 12 10 Time (ns) 8 6 4 2 0 10 20 30 40 50 60 Load (pF) 70 80 90 100 90 100 Figure 9. 3.3-V I/O Drive Type E Rise Time 12 10 Time (ns) 8 6 4 2 0 10 20 30 40 50 60 70 80 Load (pF) Figure 10. 74 3.
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P R E L I M I N A R Y 8 7 6 Time (ns) 5 4 3 2 1 0 10 20 30 40 50 60 70 80 90 100 90 100 Load (pF) Figure 11. 5-V I/O Drive Type E Rise Time 9 8 7 Time (ns) 6 5 4 3 2 1 0 10 20 30 40 50 60 70 80 Load (pF) Figure 12.
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P R E L I M I N A R Y 20 18 16 Time (ns) 14 12 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 100 120 130 140 120 130 140 Load (pF) Figure 13. 3.3-V I/O Drive Type D Rise Time 25 Time (ns) 20 15 10 5 0 10 20 30 40 50 60 70 80 90 100 Load (pF) Figure 14. 3.
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P R E L I M I N A R Y 16 14 12 Time (ns) 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 100 120 130 140 150 130 140 150 Load (pF) Figure 15. 5-V I/O Drive Type D Rise Time 18 16 14 Time (ns) 12 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 100 120 Load (pF) Figure 16.
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P R E L I M I N A R Y 14 12 Time (ns) 10 8 6 4 2 0 10 20 30 40 50 60 70 80 70 80 Load (pF) Figure 17. 3.3-V I/O Drive Type C Rise Time 12 10 Time (ns) 8 6 4 2 0 10 20 30 40 50 60 Load (pF) Figure 18. 3.
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P R E L I M I N A R Y 10 9 8 Time (ns) 7 6 5 4 3 2 1 0 10 20 30 40 50 60 70 80 70 80 Load (pF) Figure 19. 5-V I/O Drive Type C Rise Time 30 40 9 8 7 Time (ns) 6 5 4 3 2 1 0 10 20 50 60 Load (pF) Figure 20.
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P R E L I M I N A R Y 25 Time (ns) 20 15 10 5 0 10 20 30 40 50 60 70 80 70 80 Load (pF) Figure 21. 3.3-V I/O Drive Type B Rise Time 18 16 14 Time (ns) 12 10 8 6 4 2 0 10 20 30 40 50 60 Load (pF) Figure 22. 3.
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P R E L I M I N A R Y 16 14 12 Time (ns) 10 8 6 4 2 0 10 20 30 40 50 60 70 80 70 80 Load (pF) Figure 23. 5-V I/O Drive Type B Rise Time 30 40 14 12 Time (ns) 10 8 6 4 2 0 10 20 50 60 Load (pF) Figure 24.
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P R E L I M I N A R Y 35 30 Time (ns) 25 20 15 10 5 0 10 20 30 40 50 60 70 80 70 80 Load (pF) Figure 25. 3.3-V I/O Drive Type A Rise Time 35 30 Time (ns) 25 20 15 10 5 0 10 20 30 40 50 60 Load (pF) Figure 26. 3.
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P R E L I M I N A R Y 25 Time (ns) 20 15 10 5 0 10 20 30 40 50 60 Figure 27. 5-V I/O Drive Type A Rise Time 30 40 70 80 70 80 Load (pF) 30 25 Time (ns) 20 15 10 5 0 10 20 50 60 Load (pF) Figure 28.
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P R E L I M I N A R Y VOLTAGE PARTITIONING The ÉlanSC310 microcontroller supports both 3.3-V system designs and mixed 3.3-V and 5-V system designs. For 3.3-V-only operation, all supply pins (VCC, VCC1, VCC5, VMEM, VSYS, VSYS2, and AVCC) should be connected to the 3.3-V DC supply. To operate an interface at 5 V, the VCCIO pins associated with that I/O interface should be connected to 5 V. All supply pins of the same name should be connected to the same voltage plane.
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P R E L I M I N A R Y frequency. It is therefore required that the load capacitance in the oscillator circuit is duplicated as closely as possible to the manufacturer’s load capacitance specification. The crystal load capacitance in the circuit consists of the capacitor network CO, CSTRAY, CD, and CG. This network reduces to (CO + CSTRAY) in parallel with the series combination of CD and CG.
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P R E L I M I N A R Y LOOP FILTERS Each of the Phase-Locked Loops (PLLs) in the ÉlanSC310 microcontroller requires an external Loop Filter. Figure 30 describes each of the Loop Filters and the recommended component values. The recommended values for the components are shown in Table 44. LFx The system designer shall include the pads on the printed circuit board to accommodate the future installation/change of C2 and R1.
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P R E L I M I N A R Y AC SWITCHING CHARACTERISTICS AND WAVEFORMS The AC specifications provided in the AC characteristics tables that follow consist of output delays, input setup requirements, and input hold requirements. Figure 31 provides a key to the switching waveforms. AC specifications measurement is defined by the figures that follow each timing table. WAVEFORMS Output delays are specified with minimum and maximum limits, measured as shown.
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P R E L I M I N A R Y AC Switching Characteristics over Commercial Operating Ranges Table 45.
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P R E L I M I N A R Y VCC/AVCC VMEM t1 RESIN VCC5 VSYS2 t4 VCC1 VSYS t2 IORESET RSTDRV Note 1 Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. Figure 32.
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P R E L I M I N A R Y VCC/AVCC VMEM RESIN VCC5 Note 1 t4 VSYS2 VCC1 VSYS t5 IORESET RSTDRV Note 2 Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. 2. The pulse width of RSTDRV is adjustable based on PLL start-up timing. See the Loop Filters section on page 86 for more information. Figure 33.
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P R E L I M I N A R Y t3 RSTDRV Note 1 IORESET t7 VCC5 t6 VSYS2 VCC1 VSYS Note 2 VCC/AVCC VMEM RESIN Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. 2. A secondary power source could be applied at this time Figure 34. Entering Micro Power Off Mode (DRAM Refresh Disabled) t3 RSTDRV IORESET Note 1 2 DRAM Refresh Cycles t7 VCC5 VSYS2 VCC1 VSYS Note 2 VCC/AVCC VMEM RESIN Notes 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. 2.
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P R E L I M I N A R Y Table 46.
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P R E L I M I N A R Y t30 MA10–MA0 t31 RAS t38 t32 t39 t45 t41 t37 t46 t47 CAS t43 t42 MWE t49 t48 D15–D0 Figure 36. DRAM Timings, Page Hit t53 RAS0 t50 t51 CAS0 MWE Figure 37.
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P R E L I M I N A R Y Table 47.
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P R E L I M I N A R Y Table 48. DRAM Bank/Page Miss Read Cycles (See Figure 38) (Continued) Symbol Parameter Description t44b CAS hold from RAS Low t47 D15–D0 hold from CAS High (read) Wait State Min Max Unit 3 75 ns 4 105 ns 5 120 ns N/A 0 ns For more information about DRAM bank miss read wait states, see the DRAM Bank Miss Wait State Select Logic table in Chapter 4 of the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665.
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P R E L I M I N A R Y Table 49.
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P R E L I M I N A R Y t38 MA10–MA0 t31 t30 t34 t40 t36 RAS t44d t32 t39 t44c t39 t41d t29b t41c CAS t33 t43 t27c t27d MWE t49 t49 t5c t5c D15–D0 First Cycle Figure 39.
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P R E L I M I N A R Y Table 51.
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P R E L I M I N A R Y t1 CPUCLK t2 t11 t3 t4 ADS t5 A23–A12 LDEV LRDY t6a t6b t7 t8 t9 CPURDY D15–D0 (in) t6a t8 t9 t10 t12 t13 t13 D15–D0 (out) Figure 40.
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P R E L I M I N A R Y Table 52.
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P R E L I M I N A R Y t2a t2b SA23–SA0 t3a t3b t1a t15 ROMCS t1b t14 t8 t4a t4b MEMR/W t5a t5b t6 t7 RDDATA t9 WRDATA t11a t11b t10 DBUFOE t12 ENDIRH, ENDIRL t13 0 = Read Figure 41.
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P R E L I M I N A R Y Table 53.
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P R E L I M I N A R Y t2a t2b SA19–SA0 t3a t3b t15 t1a DOSCS t1b t14 t8 t6 t4a t4b t5a t5b MEMR/W t7 RDDATA t9 WRDATA t10 t11a t11b DBUFOE t12 ENDIRH, ENDIRL t13 0 = Read Figure 42.
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P R E L I M I N A R Y Table 54.
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P R E L I M I N A R Y t2a t2b SA23–SA0 t3a t3b t15 t1a DOSCS t1b t16a,b t14 t8 t4a t4b t6 t5a t5b MEMR/W t7 RDDATA t9 WRDATA t10 DBUFOE t11a t11b t13 t12 ENDIRH, ENDIRL 0 = Read Figure 43.
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P R E L I M I N A R Y Table 55.
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P R E L I M I N A R Y t1 t3 BALE t19 t4 t18 LA23–LA17 t5a t5b SA23–SA0 t7a t7b t12 t6 t10 t2 MEMR/W t8a t8b t9a t9b IOCHRDY t11 RDDATA t13 WRDATA t15a t15b t14 DBUFOE ENDIRH, ENDIRL t17 t16 0 = Read Figure 44.
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P R E L I M I N A R Y Table 56.
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P R E L I M I N A R Y t1 t3 BALE t21 t4 LA23–LA17 t5a t5b t20 SA23–SA0 t8a t8b t19 t13 t6 t11 t2 MEMR/W t7b t7a MCS16 t9a t9b t10a t10b IOCHRDY t12 RDDATA t14 WRDATA t16a t16b t15 DBUFOE t17 ENDIRH, ENDIRL t18 0 = Read Figure 45.
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P R E L I M I N A R Y Table 57.
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P R E L I M I N A R Y t1 t3 BALE t4 LA23–LA17 t5a t5b SA23–SA0 t8 t6 t14 t2 t12 MEMR/W t11 t7 MCS16 t9 t10 0WS t13 RDDATA t15 WRDATA Figure 46.
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P R E L I M I N A R Y Table 58.
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P R E L I M I N A R Y t2a t2b SA15–SA0 BALE t3a t3b t14 t8 t6 t1a t1b t5a t5b IOR/W t4a t4b IOCHRDY t7 RDDATA t9 WRDATA t10 t11a t11b DBUFOE t13 t12 ENDIRH, ENDIRL 0 = Read Figure 47.
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P R E L I M I N A R Y Table 59.
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P R E L I M I N A R Y t6a t6b SA15–SA0 BALE t15 t5a t5b t1a t1b t9 t13 t7 IOR/W t4a t4b t2 IOCS16 t3a t3b IOCHRDY t8 RDDATA t10 WRDATA t11 DBUFOE t12a t12b t14 ENDIRH, ENDIRL 0 = Read Figure 48.
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P R E L I M I N A R Y Table 60. EPP Data Register Write Cycle (See Figure 49) Symbol Parameter Description Max Min Units t0 AFDT delay from IOW active 8.4 4.9 ns t1 AFDT delay from PPDCS active 1.8 1.1 ns t2 AFDT delay from PPOEN active 1.0 0.8 ns t3 AFDT active pulse width (no wait states added) 450 448 ns t4 AFDT High to Low recovery 1000 ns t5 AFDT Low to STRB Low –0.2 ns t6 STRB delay from PPDCS active 1.6 0.9 ns t7 STRB delay from PPOEN active 0.8 0.
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P R E L I M I N A R Y Table 61. EPP Data Register Read Cycle (See Figure 50) Parameter Description Symbol Max Min Unit t1 AFDT delay from PPDCS active 1.8 1.1 ns t2 AFDT active pulse width (no wait states) 450 448 ns t3 AFDT High to Low recovery 1000 ns t4 Read data valid delay 25.3 ns t5 Read data hold time t6 PPDCS delay from IOR active 6.8 t7 PPDCS delay from AFDT inactive 3.7 t8 PPDCS delay from IOR inactive t9 BUSY (inactive) hold from AFDT High 2.3 ns ns 1.
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P R E L I M I N A R Y PHYSICAL DIMENSIONS PQR 208, Trimmed and Formed Plastic Shrink Quad Flat Pack (QFP) Pin 208 25.50 REF 27.90 28.10 30.40 30.80 Pin 156 Pin 1 I.D. 25.50 REF 27.90 28.10 30.40 30.80 Pin 52 Pin 104 3.20 3.60 0.50 BASIC 3.95 MAX 0.25 MIN SEATING PLANE Notes: 1. All dimensions are in millimeters 16-038-PQR-1_AH PQR208 EC95 8-13-97 lv 2. Not to scale. For reference only.
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P R E L I M I N A R Y PHYSICAL DIMENSIONS (CONTINUED) PQL 208, Trimmed and Formed Thin Quad Flat Pack (TQFP) 208 1 29.80 27.80 30.20 28.20 52 27.80 28.20 29.80 30.20 11° – 13° 1.35 1.45 1.60 MAX 0.50 BSC 11° – 13° 16-038-PQT-1_AL PQL208 9.4.97 lv 1.00 REF. Notes: 1. All dimensions are in millimeters. 2. Not to scale. For reference only. Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.