Specifications

104 Élan™SC310 Microcontroller Data Sheet
PRELIMINARY
Notes:
1. This is the timing when DOSCS
is qualified with MEMR or MEMW, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 0).
2. This is the timing when DOSCS
is configured as an address decode, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 1).
These timings are based on Index 51h, bit 1 set for 16-bit DOSCS
cycles and required initial programming. The standard DOS
ROM timings are based on the default wait state setting in bits 2 and 3 of the MMM Memory Wait States Register, Index 62h, for
4 wait states.
The Fast DOS ROM timings are based on Index B8h, bit 7 set for DOSCS
to run at high speed with the default settings in bits 5
and 6 for 4 wait states. These timings may be modified via the Command Delay Register, Index 60h. (See the
Élan
TM
SC310
Microcontroller Programmer’s Reference Manual
, order #20665.)
For more information about fast DOS ROM cycles, see the
Élan
TM
SC300 and Élan
TM
SC310 Devices’ ISA Bus Anomalies Appli-
cation Note
, order #20747.
Table 54. DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles (See Figure 43)
Symbol Parameter Description Notes
Standard
DOS
Preliminary
Fast DOS
33 MHz
Preliminary
Fast DOS
25 MHz
Preliminary
Units
Min Max Min Max Min Max
t1a SA stable to DOSCS
active 1 65 25 25 ns
t1b SA stable to DOSCS
active 2 5 5 8 ns
t2a SA hold from DOSCS
inactive (write) 1 50 15 20 ns
t2b SA hold from DOSCS
inactive (read) 1 0 0 0 ns
t3a DOSCS
pulse width (read) 1 550 130 250 ns
t3b DOSCS
pulse width (write) 1 500 100 175 ns
t4a MEMW
active to DOSCS active 1 3 3 3 ns
t4b MEMR
active to DOSCS active 1 4 4 4 ns
t5a DOSCS
hold from MEMW inactive 1 0 0 0 ns
t5b DOSCS
hold from MEMR inactive 1 0 0 0 ns
t6 RDDATA setup to command inactive 25 25 33 ns
t7 RDDATA hold from command inactive 0 0 0 ns
t8 WRDATA setup to command inactive 400 120 160 ns
t9 WRDATA hold from command inactive 45 15 20 ns
t10 DBUFOE
active from command 5 5 0 ns
t11a DBUFOE
hold from MEMW 50 15 20 ns
t11b DBUFOE
hold from MEMR –2 –2 0 ns
t12 ENDIRH, ENDIRL setup to MEMR
50 15 20 ns
t13 ENDIRH, ENDIRL hold from MEMR
–4 –4 –4 ns
t14 DOSCS
active to command active 2 65 15 20 ns
t15 DOSCS hold from SA 25 5 5 ns
t16a MEMR
pulse width 550 130 250 ns
t16b MEMW
pulse width 500 100 175 ns