Specifications

108 Élan™SC310 Microcontroller Data Sheet
PRELIMINARY
Notes:
These timings are based on default settings and required initial programming. These timings may be modified via the MMS
Memory Wait State 1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the Élan
TM
SC310 Microcontroller
Programmer’s Reference Manual
, order #20665.)
Table 56. ISA Memory Read/Write 16-Bit Cycle (See Figure 45)
Symbol Parameter Description Notes
Preliminary
Units
Min Max
t1 LA stable to BALE inactive 60 ns
t2 SA stable to command active 70 ns
t3 BALE pulse width 35 ns
t4 LA hold from BALE inactive 40 ns
t5a SA hold from command inactive Write 50 ns
t5b SA hold from command inactive Read 0 ns
t6 BALE inactive to command active 30 ns
t7a LA stable to MCS16
valid 35 ns
t7b MCS16 hold from LA change 0 ns
t8a MEMW
command pulse width 500 ns
t8b MEMR
command pulse width 550 ns
t9a MEMW active to IOCHRDY inactive 340 ns
t9b MEMR
active to IOCHRDY inactive 340 ns
t10a MEMW
hold from IOCHRDY active 110 ns
t10b MEMR hold from IOCHRDY active 160 ns
t11 RDDATA setup to command inactive 25 ns
t12 RDDATA hold from command inactive 0 ns
t13 WRDATA setup to command inactive 330 ns
t14 WRDATA hold from command inactive 50 ns
t15 DBUFOE
active from command 5 ns
t16a DBUFOE hold from command Write 50 ns
t16b DBUFOE
hold from command Read –2 ns
t17 ENDIRH, ENDIRL setup to MEMR
50 ns
t18 ENDIRH, ENDIRL hold from MEMR –4 ns
t19 SA (23:13) stable to MCS16
valid 25 ns
t20 LA stable to SA stable 15 ns
t21 SA stable to BALE inactive 45 ns