Specifications

Élan™SC310 Microcontroller Data Sheet 43
PRELIMINARY
(ISA Cycle) + (DMA Cycle) + (Low Speed)
2 x CPU Clock
High Speed PLL (I
4
)
18.432 MHz
Programmable Low Speed (I
0
–I
3
)
Divide
Chain
18.432
9.216
4.608
2.304
1.152
I
4
I
3
I
2
I
1
I
0
S
2
Internal
SYSCLK
DMA
Clock
External
SYSCLK
0
1
÷ 2
÷ 4
÷ 2
2 x CPU/Local
Bus Clock
S
[1:0]
Figure 2. Clock Steering Block Diagram
(Low-Speed PLL mode only)