Specifications

Élan™SC310 Microcontroller Data Sheet 63
PRELIMINARY
ISA BUS DESCRIPTIONS
The two bus configuration options (local bus or maxi-
mum ISA bus) each support a somewhat different sub-
set of the ISA bus standard. These subsets are defined
in Tables 33 and 34.
Table 34. ISA Bus Functionality Lost when
Configured for Local Bus Mode
Table 33. ISA Bus Functionality
Pin Name I/O Function
SA23–SA0
O
System Address Bus
D15–D0
B
System Data Bus
IOCHRDY
I
I/O Channel Ready
RSTDRV
O
System Reset
MEMW
O
Memory Write
MEMR
O
Memory Read
IOW
O
I/O Write
IOR
O
I/O Read
AEN
O
DMA Address Enable
TC
O
Terminal Count
SYSCLK
O
System Clock (ISA bus timing is not
derived from this clock)
IRQ1
I
Interrupt IRQ1
PIRQ0
I
Programmable IRQx
PIRQ1
I
Programmable IRQx
DACK2
O
DMA Channel 2 Acknowledge
DRQ2
I
DMA Channel 2 Request
IOCS16
I
I/O Device is 16 bits
MCS16
I
Memory Device is 16 bits
IRQ14
I
Interrupt Request Input
SBHE
O
Byte High Enable
X1OUT
[BAUDOUT]
O
Video Oscillator (14.336 MHz)/
Serial Port Output
IOCHCHK
I
ISA I/O Channel Check
DRQ1
I
DMA Channel 1 Request
DACK1
O
DMA Channel 1 Acknowledge
DRQ5
I
DMA Channel 5 Request
DACK5
O
DMA Channel 5 Acknowledge
IRQ4
I
Interrupt Request Input
IRQ12
I
Interrupt Request Input
IRQ15
I
Interrupt Request Input
Pin Name I/O Function
BALE
O
ISA Bus Address Latch Enable
DRQ0
I
DMA Channel 0 Request
DRQ3
I
DMA Channel 3 Request
DRQ6
I
DMA Channel 6 Request
DRQ7
I
DMA Channel 7 Request
DACK0
O
DMA Channel 0 Acknowledge
DACK3
O
DMA Channel 3 Acknowledge
DACK6
O
DMA Channel 6 Acknowledge
DACK7
O
DMA Channel 7 Acknowledge
IRQ5
I
Interrupt Request Input
IRQ7
I
Interrupt Request Input
IRQ9
I
Interrupt Request Input
IRQ10
I
Interrupt Request Input
IRQ11
I
Interrupt Request Input
LA23–LA17
O
ISA Non-Latched Address
LMEG
O
ISA Memory Cycle Below 100000h
0WS
I
Zero Wait State Request