Specifications

92 Élan™SC310 Microcontroller Data Sheet
PRELIMINARY
Notes:
These timings are based on 33-MHz operation (70 ns or faster DRAM recommended).
Table 46. DRAM Memory Interface, Page Hit and Refresh Cycle (See Figures 36 and 37)
Symbol Parameter Description Notes
Preliminary
Unit
Min Max
t30 MA valid setup to RAS
Low 0 ns
t31 MA hold from RAS
Low 10 ns
t32 MA setup to CAS
Low 0 ns
t37 CAS
precharge (Page mode) 10 ns
t38 MA hold from CAS
active 15 ns
t39 RAS
to CAS delay 20 ns
t41 CAS
pulse width (page hit) 20 10,000 ns
t42 MWE
setup to CAS Low (page hit) 0 ns
t43 MWE
hold from CAS Low 15 ns
t45 CAS
cycle time (Page mode) 45 ns
t46 CAS
Low to D15–D0 valid (read access time) 20 ns
t47 D15–D0 hold from CAS
High (read) 0 ns
t48 D15–D0 setup to CAS
Low (write) 0 ns
t49 D15–D0 hold from CAS
Low (write) 15 ns
t50 CAS
Low to RAS Low (refresh) 10 ns
t51 CAS
hold from RAS Low (refresh) 70 ns
t53 RAS
pulse width (suspend refresh) 80 ns