Specifications

Élan™SC310 Microcontroller Data Sheet 95

PRELIMINARY

For more information about DRAM bank miss read wait states, see the DRAM Bank Miss Wait State Select Logic table in Chapter

4 of the

Élan

SC310 Microcontroller Programmer’s Reference Manual

, order #20665.

t44b

CAS

hold from RAS Low

375 ns

4 105 ns

5 120 ns

t47 D15–D0 hold from CAS

High (read) N/A 0 ns

Table 48. DRAM Bank/Page Miss Read Cycles (See Figure 38) (Continued)

Symbol Parameter Description Wait State Min Max Unit

t41a

RAS

t36

t40

t38

t30

t31

t34

t44a

t39

t5b

t47

MA10–MA0

CAS

MWE

D15–D0

Figure 38. DRAM First Cycle and Bank/Page Miss (Read Cycles)

t32

First Cycle

Bank/Page Miss

t33

t5a

t28a

t28b

t41b

t39

t29a

t44b