Specifications

98 Élan™SC310 Microcontroller Data Sheet
PRELIMINARY
Table 51. Local Bus Interface (See Figure 40)
Symbol Parameter Description Notes
Preliminary
Unit
Min Max
t1 CPUCLK period 14 ns
t2 CPUCLK pulse width Low 7 ns
t3 CPUCLK pulse width High 7 ns
t4 ADS
delay from CPUCLK 3 15 ns
t5 A[23–1] BLE
, BHE, W/R,D/C, M/IO delay from CPUCLK 5 23 ns
t6a LDEV
valid from address or control (non-zero wait state) 2 20 ns
t6b LDEV
valid from address or control (zero wait state) 2 18 ns
t7 LRDY
valid from CPUCLK 2 12 ns
t8 LRDY
high impedance from CPUCLK 0 5 ns
t9 CPURDY
delay from CPUCLK 5 26 ns
t10 CPURDY
high impedance from CPUCLK 0 5 ns
t11 D15–D0 setup to CPUCLK (Read) 7 ns
t12 D15–D0 hold from CPUCLK (Read) 0 0 ns
t13 D15–D0 valid from CPUCLK (Write) 5 20 ns