Data Sheet

ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
18 of 39
6 Digital Interface
6.1 I
2
C Serial Interface
The internal registers and memory of the ITG-3200 can be accessed using I
2
C at up to 400kHz.
Serial Interface
Pin Number
Pin Name
Pin Description
8
VLOGIC
Digital IO supply voltage. VLOGIC must be ≤ VDD at all times.
9
AD0
I
2
C Slave Address LSB
23
SCL
I
2
C serial clock
24
SDA
I
2
C serial data
6.1.1 I
2
C Interface
I
2
C is a two wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I
2
C interface implementation, attached devices can be a master or a
slave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ITG-3200 always operates as a slave device when communicating to the system processor, which thus acts as the
master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400kHz.
The slave address of the ITG-3200 devices is b110100X which is 7 bits long. The LSB bit of the 7 bit address is
determined by the logic level on pin 9. This allows two ITG-3200 devices to be connected to the same I
2
C bus. When
used in this configuration, the address of the one of the devices should be b1101000 (pin 9 is logic low) and the address
of the other should be b1101001 (pin 9 is logic high). The I
2
C address is stored in register 0 (WHO_AM_I register).
I
2
C Communications Protocol
START (S) and STOP (P) Conditions
Communication on the I
2
C bus starts when the master puts the START condition (S) on the bus, which is defined as a
HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy
until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line
while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
START condition STOP condition
P
START and STOP Conditions