Data Sheet

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ITG-3200 Product Specification

Document Number: PS-ITG-3200A-00-01.4

Revision: 1.4

Release Date: 03/30/2010

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8.4 Register 23 – Interrupt Configuration

Type: Read/Write

(Hex)

(Decimal)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Default

Value

ACTL

OPEN

LATCH_

INT_EN

INT_

ANYRD_

2CLEAR

ITG_RDY_

RAW_

RDY_ EN

00h

Description:

This register configures the interrupt operation of the device. The interrupt output pin (INT) configuration can

be set, the interrupt latching/clearing method can be set, and the triggers for the interrupt can be set.

Note that if the application requires reading every sample of data from the ITG-3200 part, it is best to enable

the raw data ready interrupt (RAW_RDY_EN). This allows the application to know when new sample data is

available.

Parameters:

ACTL Logic level for INT output pin – 1=active low, 0=active high

OPEN Drive type for INT output pin – 1=open drain, 0=push-pull

LATCH_INT_EN Latch mode – 1=latch until interrupt is cleared, 0=50us pulse

INT_ANYRD_2CLEAR Latch clear method – 1=any register read, 0=status register read only

ITG_RDY_EN Enable interrupt when device is ready (PLL ready after changing clock source)

RAW_RDY_EN Enable interrupt when data is available

0 Load zeros into Bits 1 and 3 of the Interrupt Configuration register.

8.5 Register 26 – Interrupt Status

Type: Read only

(Hex)

(Decimal)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Default

Value

ITG_RDY

RAW_

DATA_

RDY

00h

Description:

This register is used to determine the status of the ITG-3200 interrupts. Whenever one of the interrupt sources

is triggered, the corresponding bit will be set. The polarity of the interrupt pin (active high/low) and the latch

type (pulse or latch) has no affect on these status bits.

Use the Interrupt Configuration register (23) to enable the interrupt triggers. If the interrupt is not enabled, the

associated status bit will not get set.

In normal use, the RAW_DATA_RDY interrupt is used to determine when new sensor data is available in either

the sensor registers (27 to 32).

Interrupt Status bits get cleared as determined by INT_ANYRD_2CLEAR in the interrupt configuration

Parameters:

ITG_RDY PLL ready

RAW_DATA_RDY Raw data is ready