Maintenance Guide Part 1

NeTIS MAINTENANCE GUIDE – Version 1.1 34/139
3.5.3 C LOCK FAULT
A high number of defects can have their origin in a clock fault; they should therefore be
checked systematically before any research on the other signals.
*Check on one BS in the network depending on your measuring bench:
With a digital TETRA bench measure the frequency error at the UCM or PA output; it
should be less than +-100Hz. If this is not the case, check the clocks.
With an analogue bench, check the frequency error at the UCM or PA output; it
should be less than +-100Hz. To do this keep the 2.25 KHz test button on the face of
the UCM pressed down in order to observe a pure offset carrier compared to the TX
BS frequency of 2.25 KHz.
If this is not the case, check the clocks:
-If the SWITCH is synchronised on the GPS signal, then check the rhythm of the GPS
indicator on the CPUBDT board of the SWITCH
-If the SWITCH is synchronised on its own LO (local oscillator), then adjust the CPUBDT
LO using the potentiometer on the face (small hole)
The general check of the clock signals is carried out from the front face of the CPU_BDT
module using the selector located on the top.