Datasheet

M2F1G64CBH4B5P/ M2F1G64CBH4B9P
M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN
M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SDRAM DIMM
REV 1.0 5
05/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram
[1GB – 1 Rank, 128Mx16 DDR3 SDRAMs]
Notes :
1. DQ wiring may differ from that shown however, DQ, DM,
DQS, and relationships are maintained as shown.
SPD
SCL
WP
SCL
SDA
SA0
SA1
A0
A1
A2
Vtt
V
REFDQ
V
REFCA
V
DD
V
DDSPD
Vtt
SPD / TS
D0-D7
D0-D7
V
SS
D0-D7
D0-D7, SPD, Temp sensor
CK0

CK1



D0-D3
D0-D3
Temp Sensor
D0-D7
D4-D7
D4-D7
DQS0

DM0
DQ[8:15]
DQS1
DM1

DQ[0:7]
LDQS
L
UDM

UDQS
DQ[0:7]
LDM
DQ[8:15]
D0




CK0

CKE0
ODT0
A[0:13]/BA[0:2]
ZQ
240ohm
+/-1%




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS2

DM2
DQ[24:31]
DQS3
DM3

DQ[16:23]
LDQS
L
UDM

UDQS
DQ[0:7]
LDM
DQ[8:15]
D1
ZQ
240ohm
+/-1%




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS4

DM4
DQ[40:47]
DQS5
DM5

DQ[32:39]
LDQS
L
UDM

UDQS
DQ[0:7]
LDM
DQ[8:15]
D2
ZQ
240ohm
+/-1%




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS6

DM6
DQ[56:63]
DQS7
DM7

DQ[48:55]
LDQS
L
UDM

UDQS
DQ[0:7]
LDM
DQ[8:15]
D3
ZQ
240ohm
+/-1%




CK

CKE
ODT
A[0:13]/BA[0:2]
Vtt
VDD
Vtt