P L 3 1 2 0 ®/ P L 3 1 5 0 ®/ P L 3 1 7 0 Power Line Smart Transceiver Data Book 005-0193-01C ®
Echelon, LON, LONWORKS, i.LON, LonBuilder, NodeBuilder, LNS, LonTalk, Neuron, 3120, 3150, LonMaker, ShortStack, and the Echelon logo are trademarks of Echelon Corporation registered in the United States and other countries. Other brand and product names are trademarks or registered trademarks of their respective holders.
Table of Contents Chapter 1 -Introduction ..............................................................................................................................................1 Overview ................................................................................................................................................................2 Product Overview...........................................................................................................................................
SERVICE Pin................................................................................................................................................32 Integrity Mechanisms ...........................................................................................................................................34 Memory Integrity Using Checksums.............................................................................................................34 Reboot and Integrity Options Word .............
Edgedivide Output.........................................................................................................................................93 Frequency Output..........................................................................................................................................95 Infrared Pattern Output..................................................................................................................................96 Oneshot Output ...........................
Energy Storage Capacitor-Input Power Supplies ........................................................................................158 Energy Storage Linear Supplies ..................................................................................................................161 Traditional Linear Power Supplies .....................................................................................................................162 Pre-Verified Switching Power Supplies ................................
Standard Transceiver Types ...............................................................................................................................210 Development Tools Support...............................................................................................................................211 Mini EVK Evaluation Kit............................................................................................................................211 NodeBuilder Development Tool ..................
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 1
Chapter 1 - Introduction Overview This data book provides detailed technical specifications on the electrical interfaces, mechanical interfaces, and operating environment characteristics for the PL 3120®, PL 3150® and PL 3170 Power Line Smart Transceivers. This data book also provides guidelines for migrating applications to the PL Smart Transceiver using the NodeBuilder® Development Tool, the Mini EVK Evaluation Kit, or the ShortStack® Developer’s Kit.
The PL Smart Transceivers integrate a Neuron processor core with an ANSI/EIA-709.2 compliant power line transceiver within a single IC, eliminating the need for an external transceiver. Three variants of PL Smart Transceivers are available: • • • The PL 3120 chip includes self-contained application program memory, RTOS, and application library preprogrammed in ROM. The PL 3150 chip includes both internal memory and an external memory bus.
Chapter 1 - Introduction Dual-Carrier Frequency Operation The PL Smart Transceivers utilize a dual-carrier frequency signaling technology to provide superior communication reliability in the face of interfering noise sources. In the case of acknowledged messaging, packets are initially transmitted on the primary frequency and if an acknowledgement is not received the packet is retransmitted on the secondary frequency.
Forward Error Correction Many noise sources interfere with power line signaling by corrupting data packets. The PL Smart Transceivers use a highly efficient, low-overhead forward error correction (FEC) algorithm in addition to a cyclical redundancy check (CRC) to overcome packet errors.
Chapter 1 - Introduction Figure 1.1 shows the CENELEC frequency restrictions that are mandatory in EU countries and are observed in many non-EU countries as well. FCC, Industry Canada and the Japan MPT regulations are less strict than the CENELEC requirements. The frequency allocations for these countries are summarized in Figure 1.3. "A" "C" Restrictions Under Consideration 100kHz 200kHz 300kHz 400kHz Restricted 500kHz 600kHz 700kHz Figure 1.
Electric Utility vs. Home/Commercial/Industrial Applications The PL 3120 and PL 3150 Smart Transceivers are designed to operate in one of two frequency ranges depending on the end application. However, the PL 3170 Smart Transceiver is designed to operate in one frequency range for the home control and automation market. When configured for use in electric utility applications, the Smart Transceivers communicate in the A-band frequency range.
Chapter 1 - Introduction PLCA-22 Power Line Communication Analyzer User’s Guide (078-0147-01) LONWORKS PCLTA-20 PCI Interface User’s Guide (078-0179-01) LONWORKS USB Network Interface User’s Guide (078-0296-01) Neuron Chip Quadrature Input Function Interface Engineering Bulletin (005-0003-01) 8 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 9
Chapter 2 – Hardware Resources Overview The PL 3120 Smart Transceiver is a complete SoC (system-on-a-chip) for designs that require up to 4KB of memory. The PL 3170 Smart Transceiver includes self-contained application program memory, Interoperable Self-Installation (ISI) library and engine, RTOS, and an application library pre-programmed in ROM. The PL 3150 Smart Transceiver supports external memory for more complex applications.
Processor 2 is the network processor that implements layers 3 through 6 of the LonTalk protocol stack. It handles network variable processing, addressing, transaction processing, authentication, background diagnostics, software timers, network management, and routing functions. Processor 2 uses network buffers in shared memory to communicate with Processor 1, and application buffers to communicate with Processor 3. These buffers are also located in shared RAM memory.
Chapter 2 – Hardware Resources Each of the three identical processors has its own register set (Table 2.2), but all three processors share data, ALUs (arithmetic logic units) and memory access circuitry (Figure 2.3). On the PL 3150 Smart Transceiver, the internal address, data, and R/W~ signals are reflected on the corresponding external lines when utilized by any of the internal processors.
The architecture is stack-oriented; one 8-bit wide stack is used for data references, and the ALU operates on the TOS (Top of Stack) register and the next entry in the data stack which is in RAM. A second stack stores the return addresses for CALL instructions, and can also be used for temporary data storage. This stack architecture leads to very compact code. Tables 2.3, 2.4, and 2.5 outline the instruction set. Figure 2.4 shows the layout of a base page, which can be up to 256 bytes long.
Chapter 2 – Hardware Resources A processor instruction cycle is three system clock cycles, or six input clock (XIN) cycles. Most instructions take between one and seven processor instruction cycles. At an input clock rate of 10MHz, instruction times vary between 0.6 μs and 4.2 μs. Execution time scales inversely with the input clock rate. The formula for instruction time is: (Instruction Time) = (# Cycles) x 6 / (Input Clock) Tables 2.3, 2.4, and 2.
PUSH/POP !D 4 1 Byte register [8 to 23] PUSH !TOS 4 1 EA = BP + TOS, push byte to NEXT POP !TOS 4 1 EA = BP + TOS, pop byte from NEXT PUSH [RSP] 4 1 Push from return stack to data stack, RSP unchanged DROP [RSP] 2 1 Increment RSP PUSHS #literal 4 1 Push short literal value [0 to 7] PUSH #literal 4 2 Push 8-bit literal value [0 to 255] PUSHPOP 5 1 Pop from return stack, push to data stack POPPUSH 5 1 Pop from data stack, push to return stack LDBP address 5 3 Load base p
Chapter 2 – Hardware Resources Memory Memory Allocation Overview PL 3150 Smart Transceiver Memory Allocation See Figure 2.5 for a memory map of the PL 3150 Smart Transceiver. • 512 bytes of in-circuit programmable EEPROM that store the following: • — Network configuration and addressing information. — Unique 48-bit Neuron ID — written at the factory. — User-written application code and read-mostly data. See Table 2.6 for available EEPROM space.
FFFF FFFF 1KB Reserved Space For Memory Mapped I/O FC00 FBFF FC00 FBFF 1KB Reserved Space For Memory Mapped I/O 2.5KB Reserved Space F200 F1FF Internal 0.5KB EEPROM 3KB EEPROM F000 EFFF F000 EFFF Internal 2KB RAM 2KB RAM E800 E800 E7FF Unavailable 83FF 42KB of Memory Space Available to the User 1KB EEPROM 8000 External 4000 3FFF 16KB Neuron Firmware and Reserved Space 0000 Unavailable 5FFF 0000 Figure 2.5 PL 3150 Smart Transceiver Memory Map 24KB Neuron Firmware (ROM) Figure 2.
Chapter 2 – Hardware Resources When the PL Smart Transceiver is not within the specified power supply voltage range, a pending or on-going EEPROM write is not guaranteed. The PL Smart Transceiver contains a built-in low-voltage interruption (LVI) circuit that holds the chip in reset when VDD5 is below a certain voltage. See the PL 3120/ PL 3150 or PL 3170 Smart Transceiver Datasheets for LVI trip points. This reduces the risk of EEPROM data corruption.
Static RAM The PL Smart Transceivers contain 2048 bytes of static RAM. The RAM is used to store the following: • • Stack segment, application, and system data Network buffers and application buffers The RAM state is retained as long as power is applied to the device. After reset, releasing the PL Smart Transceiver initialization sequence will clear the RAM (see the section Reset Processes and Timing for more information).
Chapter 2 – Hardware Resources Table 2.7 External Memory Interface Pins Direction Function Pin Designation A0 - A15 Output Address Pins D0 - D7 Input/Output Data Pins E Output Enable Clock R/W output Read/Write Select Low The PL Smart Transceiver can be interfaced to another MPU through the 12 I/O pins using a serial or parallel connection, or through a dual-ported RAM device such as the Cypress CY7C144, CY7C138, or CY7C1342.
System Clock Divide Chain IO6 IO5 MUX IO7 System Clock Divide Chain Control Logic Timer/Counter 1 Control Logic Timer/Counter 2 IO4 IO3 IO2 IO1 IO0 Figure 2.7 Timer/Counter Circuits Clock Input The PL Smart Transceiver requires a 10.0000MHz clock signal for C-band operation and a 6.5536MHz signal for Aband operation. This clock can be provided by connecting an appropriate parallel resonant crystal to the XIN and XOUT pins of the PL Smart Transceiver as shown in Figure 2.8.
Chapter 2 – Hardware Resources Coptional XIN PL Smart Transceiver XOUT Coptional Figure 2.8 PL 3120, PL 3150, PL 3170 Smart Transceiver crystal clock connections The PL Smart Transceiver requires a clock frequency accuracy of ±200ppm over the full range of component tolerances and operating conditions. Variation within the PL Smart Transceiver IC uses a portion of the overall ±200ppm budget.
Band-In-Use (BIU) and Packet Detect (PKD) LED Connections The PL Smart Transceiver supplies two output signals, PKD and BIU, that are intended to drive low-current lightemitting diodes (LEDs). Both signals are active-high and must be connected to separate LEDs, with series currentlimiting resistors added between the LEDs and ground. The PKD and BIU pins are rated to source up to 12mA.
Chapter 2 – Hardware Resources Additional Functions Reset Function The reset function is a critical operation in any embedded microcontroller. In the case of the PL Smart Transceiver, the reset function plays a key role in the following conditions: • • • • • Initial VDD5 power up (reset ensures proper initialization of the PL Smart Transceiver during power up). VDD5 power down (reset ensures proper shut down of the PL Smart Transceiver).
RESET~ Pin The RESET~ pin is both an input and an output. The RESET~ pin includes an internal current source that acts as a pullup resistor.
Chapter 2 – Hardware Resources PL Smart Transceiver VDD5 To Other Devices IN LVI RESET~ RESET~ CE Switch GND If using external flash, an external pulse-stretching LVI must be used (Dallas DS1813-5). (100 pF Min 1000 pF Max) Figure 2.9 Example Reset Circuit For PL 3150 Smart Transceiver-based Devices Power Up Sequence During power up sequences, the RESET~ pin will be held low by the internal LVI until the power supply is stable.
Reset Processes and Timing During the reset period, the I/O pins are in a high-impedance state. The PL 3150 Smart Transceiver address lines A15 – A0 are forced to 0xFFFF, R/W~ is forced to 0, and E is forced to 1. The data lines are driven low, so they will not float and draw excess current. The SERVICE~ pin is high impedance during reset and the internal pull-up is disabled.
Specified by Application Specified by Application Chapter 2 – Hardware Resources Scheduler Init One-Second Timer Init Checksum Init Comm Port Init System RAM Setup Stable R/W~ Reflecting Firmware Execution Stable Data Reflecting Firmware Execution Stable Address Reflecting Firmware Execution Oscillates at Divide by 2 of CLK1 Oscillates Pull-Ups Disabled Random Number Seed Calc Off-Chip RAM State Init SERVICE~ Pin Init Stack Init and BIST Oscillator Start-Up* WARNING: NOT TO SCALE R/W~ DATA [
After the oscillator has started up, the PL Smart Transceiver counts additional transitions on XIN to allow the oscillator’s frequency to stabilize. From the time RESET~ is asserted until the end of the oscillator stabilization period, the I/O pins are in a high-impedance state. The E~ signal goes inactive (high) immediately after reset goes low, and the address bus becomes high (0xFFFF) to deselect external devices.
Chapter 2 – Hardware Resources • • • • • I/O pin initialization step — Initialize I/O pins based on application definition. Prior to this point, I/O pins are high impedance. State wait II — Wait for the device to leave the unconfigured or hard-offline state. If waiting was required, a flag is set to indicate that the device should come up offline. Parallel I/O synchronization — Devices using parallel I/O attempt to execute the master/slave synchronization protocol at this point.
Stack Initialization and BIST 38.6000 ms SERVICE~ Pin Initialization 0.1000 ms State Initialization 0.0250 ms Off-Chip RAM Initialization 0 ms Random Number Seed Calculation 0 ms System RAM Setup 2.7000 ms Communication Port Initialization 0.0000 ms Checksum Initialization 10.8000 ms One-Second Timer Initialization 0.6100 ms Scheduler Initialization 0.7400 ms Total 53.5757 ms Table 2.
Chapter 2 – Hardware Resources Stack Initialization and BIST 42.50 ms SERVICE~ Pin Initialization 0.10 ms State Initialization 0.13 ms Off-Chip RAM Initialization 353.00 ms Random Number Seed Calculation 5.00 ms System RAM Setup 4.20 ms Communication Port Initialization Checksum Initialization 0 ms 12.50 ms One-Second Timer Initialization 0.61 ms Scheduler Initialization 0.74 ms Total 418.
PL 3120/3150 Smart Transceiver VDD Config Pull-Up LED Broadcast ID SERVICE~ VSS 20 mA Sink Drive Out For driving a 50% duty cycle output. Waveform is sampled for external ground condition. ThreeState ThreeState SERVICE~ Pin Signal Out Low Low ThreeState Low Firmware Samples Figure 2.11 PL Smart Transceiver SERVICE~ Circuit Table 2.
Chapter 2 – Hardware Resources Integrity Mechanisms Memory Integrity Using Checksums To ensure the integrity of the memory of the PL Smart Transceiver, the Neuron firmware maintains a number of checksums. Each checksum is a single byte and is the two’s complement of the sum of all bytes it covers. These checksums are verified during reset processing and also on a continual basis via a background diagnostic process.
Upon detecting a checksum error, the reset process will force the appropriate state and log an error in the error log. For the PL 3150 Smart Transceiver, a checksum must fail twice during reset processing in order for it to be deemed bad. Reboot and Integrity Options Word A PL 3150 Smart Transceiver has a number of options for actions taken following a checksum error or other memory related fatal errors.
Chapter 2 – Hardware Resources Reset Processing During reset processing, the configuration checksum is checked first. If bad, and no configuration recovery options are set, then a configuration checksum error is logged, the checksum repaired, and the device state is changed to unconfigured. If the configuration recovery option is set, the configuration is recovered. Next, the application checksum is checked.
PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 37
Chapter 3 – Input/Output Interfaces Introduction The PL 3120, PL 3150, and PL 3170 Power Line Smart Transceivers connect to application-specific external hardware via 12 pins, named IO0-IO11. These pins can be configured in numerous ways to provide flexible input and output functions with minimal external circuitry. The programming model (Neuron C language) allows the programmer to declare one or more pins as I/O objects.
Hardware Considerations Tables 3.1 through 3.5 list the available I/O objects. Various I/O objects of different types can be used simultaneously. Figure 3.3 summarizes the pin configuration for each of the I/O objects. For the electrical characteristics of these pins, refer to the PL 3120/PL 3150 or PL 3170 Smart Transceiver Datasheets. The following sections contain detailed descriptions of all the I/O objects. The application program can optionally specify the initial values of digital outputs.
Chapter 3 – Input/Output Interfaces Table 3.
Table 3.5 Summary of Timer/Counter Output Objects I/O Object Applicable I/O Pins Output Signal Page 93 Edgedivide Output IO0, IO1 + (one of IO4 – IO7) Output frequency is the input frequency divided by a user-specified number Infrared Pattern Output IO0, IO1 Series of timed repeating square wave output signals 96 Frequency Output IO0, IO1 Square wave of 0.3 Hz to 2.5MHz 95 Oneshot Output IO0, IO1 Pulse of duration 0.2 µs to 1.
Chapter 3 – Input/Output Interfaces tsetup 20ns thold 0ns IO0-IO11 Inputs (220ns pulse) Internal System Clock (XIN Input Clock 10MHz divided by 2) IO0-IO11 Inputs D Q D Q Synchronized IO0-IO11 Inputs Internal System Clock I/O Input Synchronizer Structure Figure 3.
I/O Pin DIRECT I/O OBJECTS 0 1 2 3 4 5 6 7 8 9 10 11 Bit Input, Bit Output All Pins 0 – 7 Byte Input, Byte Output Leveldetect Input Any Four Adjacent Pins Nibble Input, Nibble Output PARALLEL I/O OBJECTS Parallel I/O Muxbus I/O Data Pins 0 – 7 Master/Slave A Data Pins 0 – 7 CS R/W HS Slave B Data Pins 0 – 7 CS R/W A0 Bitshift Input, Bitshift Output I 2 C I/O Magcard Input SERIAL I/O OBJECTS C D C D C D C D ALS WS RS C D C D C C D Optional Timeout C D Magcard Bits
Chapter 3 – Input/Output Interfaces I/O Timing Issues The PL Smart Transceiver I/O timing is influenced by four separate, yet overlapping areas of the overall chip architecture: • • • • The scheduler The I/O object’s firmware The PL Smart Transceiver hardware Interrupts The contribution of the scheduler to the overall timing characteristic is approximately uniform across all I/O function blocks because its contribution to the overall I/O timing is at a relatively high functional level.
IO_out call IO_out call IO_out call t ww t sol t ww IO_0 TIME 1st when end-of-loop clause processing begins 2nd when clause 1st when clause (Not to scale) Symbol Description Typ @ 10MHz tww when-clause to when-clause latency 940 µs tsol Scheduler overhead latency (see text) 54 µs Figure 3.
Chapter 3 – Input/Output Interfaces Overall accuracy is always related to the accuracy of the XIN input of the PL Smart Transceiver. Timing diagrams are provided for all non-trivial cases to clarify the parameters given. For more information on the operation of each of the I/O objects, refer to the Neuron C Reference Guide.
t fin t ret INPUT TIME START OF io_in() INPUT PIN SAMPLED END OF io_in() Symbol Description Typ @ 10MHz tfin Function call to sample IO0 – IO10 IO11 41 µs 8.4µs tret Return from function IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 19 µs 23.4 µs 27.9 µs 32.3 µs 36.7 µs 41.2 µs 45.6 µs 50 µs 19 µs 23.4 µs 27.9 µs 7.8 µs Figure 3.
Chapter 3 – Input/Output Interfaces Byte Input/Output Pins IO0 – IO7 can be configured as a byte-wide input or output port, which can be read or written using integers in the range 0 to 255. This is useful for driving devices that require ASCII data, or other data, eight bits at a time. For example, an alphanumeric display panel can use byte function for data, and use pins IO8 – IO11 in bit function for control and addressing. See Figures 3.8, 3.9, and 3.10. IO0 represents the LSB of data.
Leveldetect Input Pins IO0 – IO7 can be individually configured as leveldetect input pins, which latch a negative-going transition of the input level with a minimal low pulse width of 200ns, with a PL Smart Transceiver clocked at 10MHz. The application can therefore detect short pulses on the input which might be missed by software polling. This is useful for reading devices, such as proximity sensors. This is the only direct I/O object which is latched before it is sampled.
Chapter 3 – Input/Output Interfaces Nibble Input/Output Groups of four consecutive pins between IO0 – IO7 can be configured as nibble-wide input or output ports, which can be read or written to using integers in the range 0 to 15. This is useful for driving devices that require BCD data, or other data four bits at a time.
t fout t ret OUTPUT TIME START OF OUTPUT PIN END OF io_out() io_out() UPDATED Symbol Description Typ @ 10MHz tfout Function to update IO0 IO1 IO2 IO3 IO4 78 µs 89.8 µs 101.5 µs 113.3 µs 125 µs tret Return from function IO0 – IO4 5 µs Figure 3.14 Nibble Output Latency Values Parallel I/O Objects Muxbus Input/Output This I/O object provides a means of performing parallel I/O data transfers between the PL Smart Transceiver and an attached peripheral device or processor (see Figure 3.15).
Chapter 3 – Input/Output Interfaces ADDR/ DATA IO0 DATA ADDR t as IO1 t rset t as C_ALS (IO8) IO2 IO3 IO4 DATA ADDR t ahw AD0 – AD7 IO5 tahr twas t adrs C_RS~ (IO10) IO6 t wrs t dws IO7 t rhold t whold IO8 C_ALS IO9 C_WS~ IO10 C_RS~ IO11 C_WS~ (IO9) t wws t fout t wret START OF io_out() END OF io_out() t rret t fin TIME START OF io_in() END OF io_in() NOTE: Data is latched 4.8 µs after the falling edge of C_RS~.
Parallel Input/Output Pins IO0 – IO10 can be configured as a bidirectional 8-bit data and 3-bit control port for connecting to an external processor. The other processor can be a computer, microcontroller, or another PL Smart Transceiver (for gateway applications). The parallel interface can be configured in master, slave A, or slave B mode.
Chapter 3 – Input/Output Interfaces IO0 IO0 IO1 IO1 IO2 IO2 IO3 IO3 IO4 D0 – D7 D0 – D7 IO5 IO5 IO6 IO6 IO7 VDD5 IO7 IO8 CS~ IO9 R/ W~ IO10 IO11 IO4 10Kohm CS~ IO8 R/W~ IO9 HS HS PARALLEL MASTER IO10 IO11 PARALLEL SLAVE A Figure 3.
CS~ t mhscs tmcspw t mhsv t mcspw t mhsv t mhsh t mhsh HS tmrwh t mrws tmrws tmhsdv R/W~ tmwdh tmrdz t mwdd mwds t DATA OUT t mrds t mrdh DATA IN READ CYCLE Symbol WRITE CYCLE Min Typ Max tmrws R/W~ setup before falling edge of CS~ (Note 6) Description 150 ns 3 XIN — tmrwh R/W~ hold after rising edge of CS~ 100 ns — — tmcspw CS~ pulse width (Note 6) 150 ns 2 XIN — tmhsh HS hold after falling edge of CS~ 0 ns — — tmhsv HS checked by firmware after rising edge of CS~ (No
Chapter 3 – Input/Output Interfaces CS~ tsahsv t sacspw tsahsv t sacspw t sahsh t sahsh HS t sarwh t sarws t sarws R/W~ t t sards sawd t sardh DATA IN t sawdh t sawds t sardz DATA OUT WRITE CYCLE (MASTER READ) Symbol READ CYCLE (MASTER WRITE) Description Min Typ Max tsarws R/W~ setup before falling edge of CS~ 25 ns — — tsarwh R/W~ hold after rising edge of CS~ 0 ns — — tsacspw CS~ pulse width 45 ns — — tsahsh HS hold after rising edge of CS~ 0 ns — — tsahsv HS vali
Slave B Mode The slave B mode is recommended for interfacing a PL Smart Transceiver acting as the slave to another microprocessor acting as the master. When configured in slave B mode, the PL Smart Transceiver accepts IO8 as a chip select and IO9 to specify whether the master will read or write, and accepts IO10 as a register select input. When CS~ is asserted and either IO10 is low or IO10 is high and R/W~ is low, pins IO0 – IO7 form the bidirectional data bus.
Chapter 3 – Input/Output Interfaces MASTER CS~ tsbcspw tsbcspw tspah MASTER A0 tsbas tsbrwh tsbrws MASTER R/W~ tsbrws MASTER DATA OUT t sbwdv WRITE CYCLE SLAVE (MASTER READ) DATA OUT Symbol Description tsbrdh tsbrds LATCH t sbwdz t sbwdh READ CYCLE (MASTER WRITE) Min Typ Max tsbrws R/W~ setup before falling edge of CS~ PL 3120, PL 3150, and PL 3170 Smart Transceivers 0 ns — — tsbrwh R/W~ hold after rising edge of CS~ 0 ns — — tsbcspw CS~ pulse width Note 1 — — tsbas A0 setup
Serial I/O Objects The timing numbers shown in this section are valid for both an explicit I/O call or an implicit I/O call through a when clause, and are assumed to be for a PL Smart Transceiver running at 10MHz. Bitshift Input/Output Pairs of adjacent pins can be configured as serial input or output lines. The first pin of the pair can be IO0-IO6, IO8, or IO9, and is used for the clock (driven by the PL Smart Transceiver).
Chapter 3 – Input/Output Interfaces INPUT SAMPLED t hold t fin t aet t tae OUTPUT CLOCK t ret DATA IN START OF io_in() END OF io_in() Active clock edge assumed to be positive in the above diagram. Symbol Description Typ @ 10MHz tfin Function call to first edge 156.6 µs tret Return from function 5.4 µs thold Active clock edge to sampling of input data 15 kbps bit rate 10 kbps bit rate 1 kbps bit rate 9 µs 40.8 µs 938.
tsetup tfin taet ttae OUTPUT CLOCK tret DATA OUT START OF io_in() END OF io_in() Active clock edge assumed to be positive in the above diagram. Symbol Description Typ @ 10MHz tfin Function call to first data out stable 16-bit shift count 1-bit shift count 185.3 µs 337.6 µs tret Return from function 10.8 µs tsetup Data out stable to active clock edge 15 kbps bit rate 10 kbps bit rate 1 kbps bit rate 10.8 µs 10.8 µs 10.
Chapter 3 – Input/Output Interfaces At the start of all transfers, a right-justified 7-bit I2C address argument is sent out on the bus immediately after the I2C “start condition.” For more information on this protocol, refer to Philips Semiconductor’s I2C documentation.
Magcard Input This I/O object is used to transfer synchronous serial data from an ISO 7811 Track 2 magnetic stripe card reader in real time. The data is presented as a data signal input on pin IO9, and a clock, or a data strobe, signal input on pin IO8. The data on pin IO9 is clocked on or just following the falling (negative) edge of the clock signal on IO8, with the LSB first.
Chapter 3 – Input/Output Interfaces IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Timeout Clock Serial Data DATA (IO9) thold t setup thigh CLOCK (IO8) tclk t low t wto TIMEOUT tret ttret tfin TIME START OF io_in() END OF io_in() Symbol Description Min Typ Max tfin Function call to first clock input — 45.
Magtrack1 Input This input object type is used to read synchronous serial data from an ISO3554 magnetic stripe card reader. The data input is on pin IO9, and the clock, or data strobe, is presented as input on pin IO8. The data on pin IO9 is clocked in just following the falling edge of the clock signal on IO7, with the LSB first.
Chapter 3 – Input/Output Interfaces Data are recognized in the IATA format as a series of 6-bit characters plus an even parity bit per character. The process begins when the start sentinel (hex 05) is recognized, and continues until the end sentinel (0x0F) is recognized. No more than 79 characters, including the 2 sentinels and the LRC character, will be read.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Select Timeout Clock Data Out Data In Clock Data Out Data In Neurowire MASTER IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Neurowire SLAVE Figure 3.28 Neurowire Input/Output Neurowire Master Mode The Neurowire master mode I/O object is still provided for legacy support. Echelon recommends using the hardware SPI instead of the legacy software I/O object (See the SPI Input/Output section later in this manual).
Chapter 3 – Input/Output Interfaces t hold t setup t high t low CLOCK DATA OUT DATA IN INPUT SAMPLED t fin tcs_clock tclock_cs CLOCK t ret SELECT START OF io_in() OR io_out() END OF io_in() OR io_out() Parameter Description Typ tfin Function call to CS~ active 69.9 µs tret Return from function 7.2 µs thold Active clock edge to sampling of input data 20 kbps bit rate 10 kbps bit rate 1 kbps bit rate 11.4 µs 53.4 µs 960.
In Neurowire slave mode, pin IO8 is the clock (driven by the external master), IO9 is the serial data output, and IO10 is the serial data input. Serial data is clocked out on pin IO9 at the same time as data is clocked in from pin IO10. Data is clocked by the rising edge of the clock signal (default), which can be up to 18kbps at 10MHz. This data rate scales with PL Smart Transceiver input clock rate. The invert keyword changes the active clock edge to negative.
Chapter 3 – Input/Output Interfaces 4. 5. 6. Test the input clock for a low input level. This is the test for the falling edge of the input clock. If the input clock is still high, sample the timeout event pin and abort if high. When the input clock is low, return to step 1 if there are more bits to be processed. Else return the number of bits processed. When either clock input test fails (that is, the clock is sampled before the next transition), there is an additional timeout check time of 19.
Serial Input DATA 1 2 3 4 5 6 7 8 START Serial Output STOP START IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 SERIAL INPUT ONE FRAME tfin tret TIME START OF io_in() START BIT APPEARS END OF FRAME Symbol Description Typ @ 10MHz tfin Function call to input sample Min (first sample) Max (timeout) 67 µs 20 byte frame tret Return from function 10 µs END OF io_in() Figure 3.
1 2 3 4 5 6 7 8 START DATA STOP START Chapter 3 – Input/Output Interfaces SERIAL OUTPUT ONE FRAME t fout tret TIME START OF io_out() START BIT APPEARS END OF FRAME Symbol Description Typ @ 10MHz tfout Function call to start bit 79 µs tret Return from function 10 µs END OF io_in() Figure 3.32 Serial Output The duration of this function call is a function of the number of data bits transferred and the transmission bit rate.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 LINE TYPE LEGEND PL Smart Transceiver 1-Wire Memory PULL-UP RESISTOR WRITE 1 tf tlow DATA LINE t ibd High Current Sink Drivers RESET AND PRESENCE t pd trsto t wh t rstl t wrd WRITE 0 DATA LINE t pdl t rdi t rret READ DATA LINE DATA LINE t ret TIME TIME START OF touch_reset() INPUT SAMPLED END OF touch_reset() START OF io_in() OR io_out() INPUT END OF SAMPLED io_in() OR io_out() Symbol Description Min Typ Max trsto Reset call to data lin
Chapter 3 – Input/Output Interfaces The leveldetect input object can be used for detection of asynchronous attachments of 1-Wire Memory devices to the PL Smart Transceiver. In such a case, the leveldetect input object is overlaid on top of the Touch I/O object. Refer to the Neuron C Programmer’s Guide for information on I/O object overlays.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Optional Pull-Up Resistors t dw DATA A t ibd DATA B t fin t tow TIMEOUT t tret t ret TIME START OF io_in() END OF io_in() Symbol Description Min Typ Max tfin Function call to start of second data edge — 75.6 µs — tdw Input data width (at 10MHz) 200 ns 100 µs 880 ms tibd Inter-bit delay 150 µs — 900 µs ttow Timeout pulse width — 39 µs — ttret Timeout to function return — 18.0 µs — tret Last data bit to function return — 74.
Chapter 3 – Input/Output Interfaces are also supported for full-duplex transfers. No errors are introduced (other than inter-byte spacing of transmitted data) under these conditions. For 6.5536MHz operation, the bit rates are limited to a maximum of 19200 bits per second for both half and full-duplex transfers. The frame format is one start bit, eight data bits and one or two stop bits. Up to 255 output bytes and 255 input bytes can be transferred at a time.
coexist with other slave mode devices on a 3 wire bus. A logic one level on the select line disables the output drivers of the output pins and puts them in a high impedance state. If the PL Smart Transceiver is the only slave device on the SPI bus and the master device does not drive the Slave Select (SS~) signal, then either Pin IO7 should be declared as an input pin and externally grounded.
Chapter 3 – Input/Output Interfaces polarity (CPOL) to determine the behavior of the clock signal during SPI transmissions. These terms relate directly to the clockedge and invert keywords used in this data book as follows: CPHA 1 = clockedge(+) 0 = clockedge(-) CPOL 1 = [default] 0 = invert The active edge of the clock is determined by the clockedge and invert keywords. If the clock signal is idle at logic 1 (default), then clockedge(-) indicates that the falling edge of the clock signal is active.
Up to 255 bytes can be bi-directionally transferred at a time. This I/O model depends on interrupts to process data at high speed and does not use the io_in() and io_out() function calls. Once transfer is initiated, control will be returned to the application immediately and the application will need to poll the I/O model for completion. Transfers can be suspended and resumed by disabling and enabling interrupts.
Chapter 3 – Input/Output Interfaces IO0 IO0 IO1 IO1 IO2 IO2 IO3 IO3 IO4 IO4 IO5 IO5 IO6 IO6 IO7 IO7 IO8 Clock IO8 Clock IO9 MISO IO9 Data Out IO10 MOSI IO10 IO11 Data In IO11 SPI Master (Neurowire pin mode) SPI Master . Select Tsc Tck Clock (invert for clockedge+ or invert=true) Tdoc Tcdo Data Out Data In Tdis Tdih Param Description Tck Clock cycle (user specified) Tsc Select low to Clock transition 4.8 μs Tdoc Data out to Clock (1st bit of invert mode) 0.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 Select IO8 Clock IO9 Data Out IO10 Data In IO11 SPI Slave Select Tsc Tck Clock (invert for clockedge- or invert=true) Tdoc Tcdo Data Out Data In Tdis Tdih Param Description Min Typ Max Units Tck Clock cycle (user specified) Tsc Select low to Clock transition 220 μs Tdoc Data out to Clock (1st bit of invert mode) 440 ns Tcdo Clock to data out Tdis Data in setup 10 ns Tdih Data in hold 10 ns Tsdz Select high to data in high impedance
Chapter 3 – Input/Output Interfaces Timer/Counter Input Objects The PL Smart Transceivers have two 16-bit timer/counters. For the first timer/counter, IO0 is used as the output, and a multiplexer selects one of pins IO4 – IO7 as the input. The second timer/counter uses IO1 as the output and IO4 as the input (see Figure 2.7). Multiple timer/counter input objects can be declared on different pins within a single application.
Dualslope Input This input object uses a timer/counter to control and measure the integration periods of a dualslope integrating analog to digital converter (see Figure 3.41). The timer/counter provides the control output signal and senses a comparator output signal. The control output signal controls an external analog multiplexer which switches between the unknown input voltage and a voltage reference.
Chapter 3 – Input/Output Interfaces Edgelog Input The edgelog input object can record a stream of input pulses measuring the consecutive low and high periods at the input and storing them in user-defined storage (see Figure 3.42). The values stored represent the units of clock period between rising and falling input signal edges. The measurement series starts on the first rising (positive) edge, unless the invert keyword is used in the I/O object declaration.
IO0 Timer/Counter 1 IO1 IO2 Timer/Counter 2 IO3 IO4 Input Bit Stream IO5 IO6 IO7 IO8 IO9 IO10 IO11 t win t wtcp INPUT (IO4) t setup t ret t oret t hold TIME START OF io_in() OVERFLOW END OF io_in() Symbol Description Min Typ Max tsetup Input data setup 0 — — twin Input pulse width 1 T/C clk — 65,534 T/C clks thold io_in() call to data input edge for inclusion of that pulse 26.4 µs — — twtcp Two consecutive pulse widths 104 µs — — toret Return on overflow — 42.
Chapter 3 – Input/Output Interfaces Infrared Input The infrared input object is used to capture a stream of data generated by a class of infrared remote control devices (see Figure 3.43). The input to the object is the demodulated series of bits from infrared receiver circuitry. The period of the on/off cycle determines the data bit value, a shorter cycle indicating a one, and a longer cycle indicating a zero. The actual threshold for the on/off determination is set at the time of the call of the function.
Ontime Input A timer/counter can be configured to measure the time for which its input is asserted. Table 3.8 shows the resolution and maximum times for different I/O clock selections. Assertion can be defined as either logic high or logic low. This object can be used as a simple analog-to-digital converter with a voltage-to-time circuit, or for measuring velocity by timing motion past a position sensor (see Figures 3.40 and 3.44).
Chapter 3 – Input/Output Interfaces IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Event Register Timer/Counter 2 mux Timer/Counter 1 Event Register System Clock Divide Chain Optional Pull-Up Resistors INPUT TIME START TIMER COUNTER STOP TIMER COUNTER t fin t ret START OF io_in() READ END OF TIMER/ io_in() COUNTER FLAG AND EVENT REGISTER CLEAR FLAG Reference Figure 3.
Because the period function measures the delay between two consecutive active edges, the invert option has no effect on the returned value of the function for a repeating input waveform. Pulsecount Input A timer/counter can be configured to count the number of input edges (up to 65,535) in a fixed time (0.8388608 second) at all allowed input clock rates. Edges can be defined as rising or falling. This object is useful for average frequency measurements, or tachometer applications (see Figure 3.46).
Chapter 3 – Input/Output Interfaces The internal counter increments with every occurrence of an active input edge. Every 0.839 second, the content of the counter is saved and the counter is then reset to 0. This sequence is repeated indefinitely. The actual active edge of the input depends on whether or not the invert option was used in the declaration of the function block. The default is the negative edge.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Event Register Timer/Counter 2 Timer/Counter 1 Event Register Optional Pull-Up Resistors INPUT 1 INPUT 2 read, reset read, reset Count + 6 counts t fin t ret read, reset read, reset Count – 6 counts 2 x XIN Period, Ex: 200 ns @ 10MHz (minimum time allowed between consecutive transitions) A START OF END OF READ io_in() TIMER/COUNTER io_in() FLAG AND EVENT REGISTER CLEAR FLAG B Reference Figure 3.
Chapter 3 – Input/Output Interfaces Totalcount Input A timer/counter can be configured to count either rising or falling input edges, but not both. Reading the value of a totalcount object gives the number of transitions because the last time it was read (0 to 65,535). Maximum frequency of the input is one-quarter of the input clock rate, for example 2.5MHz at a maximum of 10MHz PL Smart Transceiver input clock.
Timer/Counter Output Objects Edgedivide Output This output object acts as a frequency divider by providing an output frequency on either pin IO0 or IO1. The output frequency is a divided-down version of the input frequency applied on pins IO4 – IO7. The object is useful for any divide-by-n operation, where n is passed to the timer/counter object through the application program and can be from 1 to 65,535. The value of 0 forces the output to the off level and halts the timer/counter.
Chapter 3 – Input/Output Interfaces IO0 Timer/Counter 1 IO1 IO2 Timer/Counter 2 Output IO3 IO4 IO5 IO6 mux Sync Input IO7 IO8 IO9 IO10 IO11 High Current Sink Drivers Optional Pull-Up Resistors tsod OUTPUT SYNC INPUT t fout t ret twin tfod TIME START OF OUTPUT INACTIVE io_out() START OF INTERNAL END OF COUNT io_out() io_out() BEGINS Symbol Description Min Typ Max tfout Function call to start of timer — 96 µs — tfod Function to output disable — 82.
Frequency Output A timer/counter can be configured to generate a continuous square wave of 50% duty cycle. Writing a new frequency value to the device takes effect at the end of the current cycle. This object is useful for frequency synthesis to drive an audio transducer, or to drive a frequency to voltage converter to generate an analog output (see Figure 3.50). .
Chapter 3 – Input/Output Interfaces Infrared Pattern Output An infrared_pattern I/O object produces a series of timed repeating square wave output signals. The frequency of the square wave output is controlled by the application. Normally, this frequency is the modulation frequency used for infrared transmission. The pattern of this modulation frequency is controlled by an array of unsigned long timing values.
Oneshot Output A timer/counter can be configured to generate a single pulse of programmable duration. The asserted state can be either logic high or logic low. Retriggering the oneshot before the end of the pulse causes it to continue for the new duration. Table 3.8 in the Notes section at the end of this chapter gives the resolution and maximum time of the pulse for various clock selections. This object is useful for generating a time delay without intervention of the application processor (see Figure 3.
Chapter 3 – Input/Output Interfaces Pulsecount Output A timer/counter can be configured to generate a series of pulses. The number of pulses output is in the range 0 to 65,535, and the output waveform is a square wave of 50% duty cycle. This function suspends application processing until the pulse train is complete. The frequency of the waveform can be one of eight values given by Table 3.9 in the Notes section at the end of this chapter with clock select values of 0 through 7.
Pulsewidth Output A timer/counter can be configured to generate a pulsewidth modulated repeating waveform. In pulsewidth short function, the duty cycle ranges from 0% to 100% (0/256 to 255/256) of a cycle in steps of about 0.4% (1/256). The frequency of the waveform can be one of eight values given by Table 3.9. In pulsewidth long function, the duty cycle ranges from 0% to almost 100% (0/65,536 to 65,535/65,536) of a cycle in steps of 15.25 ppm (1/65,536).
Chapter 3 – Input/Output Interfaces A disabled output is a logic 0 by default unless the invert keyword is used in the I/O object declaration. Triac Output On the PL Smart Transceiver, a timer/counter can be configured to control the delay of an output signal with respect to a synchronization input. This synchronization can occur on the rising edge, the falling edge, or both the rising and falling edges of the input signal.
The hardware update does not happen until the occurrence of an external active sync clock edge. The internal timer is then enabled and a triac gate pulse is generated after the user-defined period has elapsed. This sequence is repeated indefinitely until another update is made to the triac gate pulse delay value. tfout (min) refers to the delay from the initiation of the function call to the first sampling of the sync input.
Chapter 3 – Input/Output Interfaces Triggered Count Output A timer/counter can be configured to generate an output pulse that is asserted under program control, and de-asserted when a programmable number of input edges (up to 65,535) has been counted on an input pin (IO4 – IO7). Assertion can be either logic high or logic low. This object is useful for controlling stepper motors or positioning actuators which provide position feedback in the form of a pulse train.
Notes Various combinations of I/O pins can be configured as basic inputs or outputs. The application program can optionally specify the initial values of basic outputs. Pins configured as outputs can also be read as inputs, returning the value last written. The gradient behavior of the timing numbers for different PL Smart Transceiver pins for some of the I/O objects is due to the shift-and-mask operation performed by the Neuron firmware.
Chapter 3 – Input/Output Interfaces Table 3.9 Timer/Counter Square Wave Output Clock Select (System Clock ÷) Repetition Rate (Hz) Repetition Period (µs) Resolution of Pulse (µs) 0 (÷1) (5MHz) 19,531 51.2 0.2 1 (÷ 2) (2.5MHz) 9,766 102.4 0.4 2 (÷ 4) (1.25MHz) 4,883 204.8 0.8 3 (÷ 8) (625 kHz) 2,441 409.6 1.6 4 (÷ 16) (312.5 kHz) 1,221 819.2 3.2 5 (÷ 32) (156.25 kHz) 610 1,638.4 6.4 6 (÷ 64) (78.125 kHz) 305 3,276.8 12.8 7 (÷ 128) (39.06 kHz) 153 6,553.6 25.
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 105
Chapter 4 – Coupling Circuits Introduction This chapter includes example coupling circuits that address most application requirements. For those who wish to understand the background behind coupling circuit design, a tutorial covering the design principles follows the detailed example circuits. Recommended Coupling Circuits This section provides schematics and component information for coupling the PL Smart Transceiver to the power mains.
Table 4.1 Coupling Circuit Selection Guide Example Connection Type Line Voltage Isolated/ Non-Isolated Freq.
Chapter 4 – Coupling Circuits Example 1. Line-to-Neutral, Non-Isolated Coupling Circuit Figure 4.1 presents a schematic for a line-to-neutral (L-N), non-isolated mains coupling circuit. Table 4.2 lists component values and example suppliers/part numbers for coupling to the AC mains with a nominal line voltage of ≤240VAC. This schematic can also be used for coupling to wiring other than AC mains with AC or DC voltages of 250VRMS or less. Figure 4.
Table 4.2 ≤240VAC Line-to-Neutral, Non-Isolated Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C101 0.15µF 0.10µF ±10%, ≥250VAC, X2 type (1) IllinoisCap/154MKP275KB AID Electronics/ MEX154K275AC IllinoisCap/104MKP275K AID Electronics/ MEX104K275AC C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 2. Line-to-Neutral, Transformer-Isolated Coupling Circuit Figure 4.2 presents a schematic for a line-to-neutral (L-N), transformer-isolated coupling circuit. Table 4.3 lists component values and example suppliers/part numbers for coupling to AC mains with a nominal line voltage of ≤240VAC. This schematic can also be used for coupling to wiring other than AC mains with AC or DC voltages of 250VRMS or less or for coupling to an un-powered wire pair. Figure 4.
Table 4.3 Line-to Neutral, Transformer-Isolated Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C101 0.15µF 0.10µF ±10%, ≥250VAC, X2 type (1) IllinoisCap/154MKP275KB AID Electronics/ MEX154K275AC IllinoisCap/104MKP275K AID Electronics/ MEX104K275AC C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 3. Line-to-Earth, Non-Isolated Coupling Circuit Figure 4.3 presents a schematic for a line-to-earth, non-isolated mains coupling circuit. Table 4.4 lists component values and example suppliers/part numbers for coupling to the AC mains with a nominal line voltage in the range 100-277VAC. Figure 4.3 Line-to-Earth, Non-Isolated Coupling Circuit Schematic Example Vendor Websites Abracon Corporation www.abracon.com Littlefuse www.littlefuse.com AID Electronics www.aid.
Table 4.4 Line-to-Earth Non-Isolated Coupling Circuit Component Values Value Comp C-band 100120VAC Required Specifications C-band 200277VAC Example Vendors / Part numbers C-band 100-120VAC C-band 200-277VAC C101 0.068µF ≥120VAC ≥300VAC 0.033µF ±10%, X2 type (1) IllinoisCap/683MKP275KB Evox-Rifa/ PHE840EA5330KA02 C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 4. Line-to-Earth, Transformer-Isolated Coupling Circuit Figure 4.4 presents a schematic for a line-to-earth, transformer-isolated coupling circuit. Table 4.5 lists component values and example suppliers/part numbers for coupling to AC mains with a nominal line voltage in the range 100277VAC. Figure 4.4 Line-to-Earth, Transformer-Isolated Coupling Circuit Schematic Example Vendor Websites Abracon Corporation www.abracon.com Illinois Capacitor www.illinoiscapacitor.
Table 4.5 Line-to-Earth, Transformer-Isolated Coupling Circuit Component Values Value Comp C-band 100120VAC Required Specifications C-band 200277VAC Example Vendors / Part numbers C-band 100-120VAC C-band 200-277VAC C101 0.068µF ≥120VAC ≥300VAC 0.033µF ±10%, X2 type (1) IllinoisCap/683MKP275KB Evox-Rifa/ PHE840EA5330KA02 C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 5. 3-Phase, Non-Isolated Coupling Circuit Figure 4.5 presents a schematic for a non-isolated 3-phase coupling circuit. Table 4.6 lists component values and example suppliers/part numbers for coupling to AC mains with a nominal line voltage in the range 100-277VAC. Figure 4.5 3-Phase, Non-Isolated Coupling Circuit Schematic Example Vendor Websites Abracon Corporation www.abracon.com Joyin www.joyin.com.tw ACT www.act1.com Nichicon www.nichicon-us.
Table 4.6 100-277 VAC, 3-Phase, Non-Isolated Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C101A-C 0.15µF 0.10µF ±10%, ≥250VAC, X2 type (1) IllinoisCap/154MKP275KB AID Electronics/ MEX154K275AC IllinoisCap/104MKP275K AID Electronics/ MEX104K275AC C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 6. 3-Phase, Transformer-Isolated Coupling Circuit Figure 4.6 presents a schematic for a transformer-isolated 3-phase coupling circuit. Table 4.7 lists component values and example suppliers/part numbers for coupling to AC mains with a nominal line voltage in the range 100-277VAC. Figure 4.6 3-Phase, Transformer-Isolated Coupling Circuit Schematic Example Vendor Websites Abracon Corporation www.abracon.com Joyin www.joyin.com.tw ACT www.act1.com MCC www.mccsemi.
Table 4.7 3-Phase, Transformer-Isolated Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C101A-C 0.15µF 0.10µF ±10%, ≥250VAC, X2 type (1) IllinoisCap/154MKP275KB AID Electronics/ MEX154K275AC IllinoisCap/104MKP275K AID Electronics/ MEX104K275AC C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 7. Line-to-Neutral, Non-Isolated Floating Coupling Circuit Figure 4.7 presents a schematic for a line-to-neutral (L-N), non-isolated mains coupling circuit that can be used in con conjunction with full-wave rectified non-isolated power supply based devices. Refer to the section later in this chapter titled Non-isolated Floating Coupling Circuits for more detailed application information. Table 4.
Table 4.8 Line-to-Neutral, Non-Isolated Floating Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C101A,B 0.22µF 0.15µF ±10%, ≥250VAC, X2 type (1) IllinoisCap/224MKP275KB AID Electronics/ MEX224K275AC IllinoisCap/154MKP275K AID Electronics/ MEX154K275AC C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 8. Line-to-Neutral, Power Line Power Supply Plus Coupler Figure 4.8 presents a schematic for using a communication coupler combined with a power supply. Both 5W and 10W versions of this combined power supply/coupler are available from Echelon Corporation. These Power Supply/Couplers incorporate line-to-neutral coupling. Table 4.9 lists component values and recommended suppliers/part numbers for this design. Figure 4.
Table 4.9 Line-to-Neutral, Power Line Power Supply Plus Coupler Component Values Value Comp C-band Example Vendors / Part# Required Specifications C-band C102 1.0µF ±10%, ≥63VDC, metallized film Arcotronics/ R82DC4100AA60J Surge /SRMA100V105K C103 ≥820µF ±20%, ≥25VDC, aluminum electrolytic, ≤0.35Ω ESR @100kHz/20C, ≥290mARMS ripple current @105C Nichicon/UHE1E821MPD Fenghua/8821LDM1020LY D101 1A Reverse breakdown ≥50VDC, forward voltage ≤1.
Chapter 4 – Coupling Circuits Example 9. Low-Voltage AC, Non-Isolated Coupling Circuit Figure 4.9 presents a schematic for a low-voltage AC, non-isolated coupling circuit. Table 4.10 lists component values and example suppliers/part numbers for coupling to AC circuits with voltages of ≤48Vpk. Figure 4.9 Low-Voltage AC, Non-Isolated Coupling Circuit Schematic Example Vendor Websites Abracon Corporation www.abracon.com ON Semiconductor www.onsemi.com ACT www.act1.com Panasonic www.panasonic.
Table 4.10 Low-Voltage AC, Non-Isolated Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C101 0.47µF 0.47µF ±10%, ≥63VDC, metallized film Arcotronics/ R82DC3470AA60J Surge /SRMA100V474K Arcotronics/ R82DC3470AA60J Surge /SRMA100V474K C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 10. Low-Voltage AC, Transformer-Isolated Coupling Circuit Figure 4.10 presents a schematic for a low-voltage AC, transformer-isolated coupling circuit. Table 4.11 lists component values and example suppliers/part numbers for coupling to AC circuits with voltages of ≤48Vpk. Figure 4.10 Low-Voltage AC, Transformer-Isolated Coupling Circuit Schematic Example Vendor Websites Abracon Corporation www.abracon.com ON Semiconductor www.onsemi.com ACT www.act1.
Table 4.11 Low-Voltage AC, Transformer -Isolated Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C101 0.47µF 0.47µF ±10%, ≥63VAC, metallized film Arcotronics/ R82DC3470AA60J Surge /SRMA100V474K Arcotronics/ R82DC3470AA60J Surge /SRMA100V474K C102 1.0µF 1.
Chapter 4 – Coupling Circuits Example 11. Low-Voltage DC, Non-Isolated Coupling Circuit Figure 4.11 presents a schematic for a low-voltage DC, non-isolated coupling circuit. Table 4.12 lists component values and example suppliers/part numbers for coupling to DC circuits with voltages of ≤48Vpk. Figure 4.11 Low-Voltage DC, Non-Isolated Coupling Circuit Schematic Example Vendor Websites Abracon Corporation www.abracon.com Nichicon www.nichicon-us.com ACT www.act1.com ON Semiconductor www.onsemi.
Table 4.12 Low-Voltage DC, Non-Isolated Coupling Circuit Component Values Value Comp A-band Required Specifications Example Vendors / Part numbers A-band C-band C-band C102 1.0µF 1.0µF ±10%, ≥63VDC, metallized film Arcotronics/ R82DC4100AA60J Surge /SRMA100V105K C103 ≥120µF ≥120µF ±20%, ≥16VDC, aluminum electrolytic, ≤0.
Chapter 4 – Coupling Circuits Coupling Circuit Tutorial Power Line Communications Background The PL Smart Transceivers employ sophisticated digital signal processing techniques, a transmit power amplifier with a very low output impedance, and a very wide (>80dB) dynamic range receiver to overcome the signal attenuation and noise inherent in power mains communication.
Figure 4.12 Power Distribution Model Attenuation is most easily understood in terms of a voltage-divider circuit formed by the output impedance of the transmitter, the impedance of the various mains circuit branches, and any loads present on the mains branch circuits.
Chapter 4 – Coupling Circuits Power Line Coupling Basics Injecting a communication signal into a power mains circuit is normally accomplished by capacitively coupling the output of a transceiver to the power mains. In addition to the coupling capacitor, an inductor or transformer is generally present. The coupling capacitor and the inductor or transformer together act as a high-pass filter when receiving the communications signal.
systems where a separate earth conductor is present and accessible (i.e., safety ground, which is not the same as a neutral wire with an earth bond), and wiring systems where there is no earth conductor. When an earth conductor is always present, a coupling method known as line-to-earth coupling provides the best communications performance. With line-to-earth coupling, the communications signal is coupled to the line wire relative to earth, and earth is used as the return path for the communications signal.
Chapter 4 – Coupling Circuits to transceivers using non-earth-return coupling. For this reason, when a safety ground connection is known to be available throughout the wiring system, a line-to-earth coupling scheme is preferred. In applications where a safety ground connection is not always available, or where line-to-earth coupling is precluded by local regulations, the coupling circuit must be connected between the line and neutral wires.
. Figure 4.17 Simplified Coupling Circuit with DC Blocking Capacitor Given the attenuation model presented earlier in Figure 4.13, one critical design constraint is that the impedance of the series combination of C101 and C102 must be very low at the communication frequencies of the PL Smart Transceiver. The impedance of these capacitors, along with the PL Smart Transceiver transmit amplifier’s output impedance, corresponds to “Z0 Transmitter” in Figure 4.13.
Chapter 4 – Coupling Circuits Figure 4.18 Simplified Coupling Circuit with Resonant Inductor An important design constraint on L102 is that its DC resistance must be a small fraction of an ohm because it is in the transmit signal path and effectively part of the transmitter's output impedance. Fortunately low-cost inductors with DC resistance of 0.3 ohms or less are widely available.
Figure 4.19 shows additions to the coupling circuit which are required to make it fully functional. The first is an inductor, L103, connected to the PL Smart Transceiver receive filtering circuitry. The DC resistance of L103 can be up to 55 ohms. The second consists of diodes, D101 and D102, connected from the transmitter to the amplifier supply rails to protect the inputs of the PL Smart Transceiver from large (>18V) transients.
Chapter 4 – Coupling Circuits Figure 4.
In instances where large ambient magnetic fields might be present (such as from switched mode power supply open frame magnetic elements), it is possible that one or more of the PL Smart Transceiver coupling circuit inductors might pick up these stray fields and conduct them onto the power mains. Depending on the frequency and amplitude of these fields they could result in failure to meet conducted emission regulations.
Chapter 4 – Coupling Circuits Some products cannot rely on their enclosure as a safety isolation barrier and an alternate method of safety isolation must then be provided. For example, a circuit board that used a non-isolated line-to-neutral coupling circuit in conjunction with a PL Smart Transceiver whose I/O pins are user-accessible would present a potential electrical shock hazard.
The receive-mode impedance of the transformer isolated coupling circuit dips near 10kHz due to the series resonant effect between C101 and T101. This dip in out-of-band impedance does not have any adverse effect on communication performance. If local regulations require a receive impedance at this resonant frequency of greater than 5 ohms, then an optional series RLC circuit can be added as shown in Figure 4.21. Figure 4.
Chapter 4 – Coupling Circuits Capacitor Charge Storage The coupling capacitors depicted in the earlier figures can retain substantial charge even after a PL Smart Transceiverbased device has been disconnected from the power mains. This can be of significant concern in applications where a line cord could be touched by a user after being disconnected from the power mains.
Detailed schematics and component values for both non-isolated and isolated 3-phase coupling circuits are given in example coupling circuit numbers 5 and 6, respectively. Figure 4.22 Transformer Isolated 3-Phase Coupling Circuit Non-isolated Floating Coupling Circuits The non-isolated coupling circuits discussed so far are suitable for use with devices incorporating power supplies where the output common terminal can be connected directly to the mains wiring.
Chapter 4 – Coupling Circuits Figure 4.23 Half-Wave Rectified Power Supply and Non-Isolated Coupling Figure 4.24 Full-Wave Rectified Power Supply and Non-Isolated Coupling Circuit Figure 4.
Power Line Power Supply Plus Coupler One very convenient coupling circuit implementation combines an isolated universal-input power supply and a line-toneutral coupling circuit. Figure 4.26 illustrates how such a device is connected to a PL Smart Transceiver-based product.
Chapter 4 – Coupling Circuits Low-Voltage Coupling Circuits While the same coupling circuits that are used to couple to the AC mains can also be used to couple to lower voltage AC or DC lines, simplified and lower cost options are possible for these lower voltage applications. This section discusses the simplifications that are possible when coupling to AC and DC lines with peak voltages below 48V.
Low-Voltage DC Coupling Circuits For applications where power line communication on ≤48V low-voltage DC power lines is required (for example, 12V automotive systems) the coupling circuit can be simplified by removing the high-pass filter components L101 and C101 as shown in Figure 4.27. Component values and part numbers for this circuit are shown in Example 11 in this chapter. Figure 4.
Chapter 4 – Coupling Circuits Line Surge Protection Coupling circuits that connect the PL Smart Transceiver to the power mains require the addition of one or more components to provide protection for the PL Smart Transceiver from the high-voltage surges that occur on power distribution systems. Primarily lightning induced, these surges can present voltages of up to 6kV at very high current levels, for brief periods, to the coupling circuits inside buildings and homes.
Surge Immunity of Example Circuits The recommendations for the surge protection components that are included in the example circuits documented in this chapter are based on testing performed on particular PCB layouts. The efficacy of the surge protection implemented in each product containing the PL Smart Transceiver must always be verified empirically using the final product design because factors such as PCB layout and packaging can influence the results as much as the choice of protection components.
Chapter 4 – Coupling Circuits Table 4.13 Surge Levels of the Example Coupling Circuits Example Coupling Type Location Type Ring Wave (0.5µs-100kHz) Level Tested with 30 Surge Events 1 2 3 4 5 6 8 150 1-phase, L-N, non-isolated 1-phase, L-N, isolated 1-phase, L-E, non-isolated 1-phase, L-E, isolated 3-phase, non-isolated 3-phase, isolated Power Supply Plus Coupler Combination Wave (1.
It is important to be aware that the PL Smart Transceiver used in conjunction with some of the coupling circuits listed in this chapter might experience a reset event when subjected to higher surge levels. The system designer must determine if their application can tolerate a reset event under high surge conditions. The level of immunity to reset events under surge conditions varies from one coupling circuit to another – as well as with specific layout.
Chapter 4 – Coupling Circuits Figure 4.
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 153
Chapter 5 – Power Supplies for PL Smart Transceivers Introduction In order to preserve the full communications capability of the PL Smart Transceiver, it is important to ensure that the power supply does not impair communication performance. If not properly designed, a power supply could attenuate the communication signal and couple noise into the transceiver - since the input of the supply is connected directly to the communication channel.
Note 1: When using the 1Ap-p transmit amplifier, VA must be ≥10.8V under typical line voltage and current draw conditions (including typical VA transmit current of 120mA). The minimum transmit VA voltage can be relaxed to 8.5V when worst case line voltage, component tolerance and transmit power supply loading are present (including a maximum VA transmit current of 250mA). Note 2: When using a supply voltage above 12.6V the following formula must be satisfied.
Chapter 5 – Power Supplies for PL Smart Transceivers Energy Storage Power Supplies PL Smart Transceivers incorporate a power management feature that supports the design of low cost power supplies in cost sensitive consumer applications such as networked light dimmers, switches, and household appliances. This class of application typically requires only occasional low-duty cycle transmission from the device.
Once enabled, the power management system detects any instance where the VA supply drops below the Smart Transceiver’s lower power management threshold (nominally 7.9V). The PL Smart Transceiver then delays transmission until the energy storage capacitor has been recharged, to allow transmission of a complete packet. The PL Smart Transceiver then transmits any waiting packets once the capacitor has fully charged.
Chapter 5 – Power Supplies for PL Smart Transceivers Energy Storage Capacitor-Input Power Supplies A particularly cost-effective example of an energy storage power supply is the capacitor-input power supply. The most attractive feature of this supply is that both the VA and VDD5 supplies can be built with just a few components for approximately US$1.00. Figure 5.2 illustrates the operation of a capacitor-input power supply.
4 Line Frequency (Hz) 60 60 50 120 120 230 S1 SERVICE SVC- D1 LED Y EL R1 1K 5% 1 + VDD5 VI U201 LM78L05 VA C202 3300uF 20% 16V <0.3 OHM @100kHZ 3 Figure 5.3 C-band Capacitor-Input Power Supply Schematic 159 5 25 5 Application & I/O Current (mA) SVC- RXCOMP RXIN TXOUT VO 1 1.8/400 3.3/250 2.7/250 C201 (uF/VDC) PL 3120/ PL 3170 Reference Design (See Appendix A) 2 GND 2 3 1 VDD5 D202 1N5350B 13V 5W PSA VDD5 2 1 2 Line Voltage (VAC) 2 VA D203 >=0.
2 4 VDD5 1 2 S1 SERVICE SVC- D1 LED Y EL R1 1K 5% D202 1N5350B 13V 5W 1 + VDD5 VI VA C202 3900uF 20% 16V <0.3 OHM @100kHZ 3 SVC- PL 3120/ PL 3170 Reference Design (See Appendix A) 2 3 1 2 PSA VDD5 GND U201 LM78L05 VA D203 >=0.8A 1 GND RXCOMP RXIN TXOUT VO 1 4 - VDD5 L201 0.75cm min. L201 0.75cm min. L102 L201 VA 1 2 L201 1mH 10% >200mA C102 1uF D102 D101 1 2 1 AC1 2 1 L101 1mH 1 L202 220uH 10% >200mA 2 C101B 0.22uF 2 C101A 0.22uF 2 C201 1.
Energy Storage Linear Supplies For products requiring minimal application current and safety isolation, an energy storage linear supply is a small cost effective option. Consider a device based on a PL 3120 or PL 3170 Smart Transceiver consuming 10mA of application and I/O current. Using a linear VA power supply and a linear regulator for the VDD5 supply, the worst case current requirements are presented in the table below. Table 5.
Chapter 5 – Power Supplies for PL Smart Transceivers In summary, an energy storage linear supply differs from a traditional linear supply in the following ways: • • • • Allows the use of a smaller transformer Requires more output capacitance for energy storage Requires that the device be programmed to enable power management, as described in Chapter 8. Under typical conditions, exhibits transmit duty cycles which are not limited.
Figure 5.6 Pre-verified Energy Storage Switching Supply Schematic The circuit in Figure 5.6 supports the power requirements of the PL 3120 and PL 3170 Smart Transceiver in conjunction with 10mA of application current. The design has been verified to meet the energy storage power supply requirements described earlier in this chapter. Specifically, it provides ≥10.8V after a transient load of 120mA for 140.
Chapter 5 – Power Supplies for PL Smart Transceivers A Pre-Verified Isolated Switching Supply When significant application current is required and small size, universal input, safety isolation and/or good efficiency are also desired, the power supply described in this section is an excellent choice. This design is based on the STMicroelectronics VIPer®20A off-line switch-mode power supply IC. This pre-verified power supply provides a total output current of 363mA at 12V.
NEUTRAL 3 4 Optional (See Text) Common Mode Choke 2 1 L203 L202 1mH R202 510 C201 0.01uF X2 L201 1mH 4 + 1 2 R201 510 1/2W R203 51 RTN 3 C202 0.47uF X2 D201 BRIDGE LINED 10uF 400V + C203 LINEF SW VDD COMP D202 UF4005 Z202 1SMB120 Z201 1SMB120 U201 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book R205 5.11K C204 0.001uF C205 1uF CCOMP RTN CCR VIPer20A-DIP 1 COSC CSUPL 3 1 2 C206 2200pF 2% C207 22uF 16V R204 18.2K 0.
Chapter 5 – Power Supplies for PL Smart Transceivers Table 5.7 Pre-Verified Isolated Switching Supply Bill of Materials (BOM) Component Value Required Specifications Example Vendor / Part # R201, R202 510Ω ±5%, ≥1/4W, overload voltage ≥500V Generic R203 51Ω ±5%, ≥1/2W, carbon composition or wire-wound KOA/RC1/2TT52A510J R204 18.2kΩ ±0.5%, ≥1/16W, ≤25ppm/C, 0603 Susumu/RR0816P-1822-D R205 5.11kΩ ±1%, ≥1/16W, 0603 Generic C201 0.
The performance of this power supply is somewhat sensitive to layout. Minimizing the length of the net from the Drain of the VIPer20A IC is of particular importance in controlling conducted emissions. In order to reduce the time required to successfully implement this supply, a recommended layout is provided below. Figure 5.
Chapter 5 – Power Supplies for PL Smart Transceivers 5W and 10W Echelon Power Supply Plus Couplers One very convenient power supply implementation combines an isolated universal-input power supply and a C-band line-to-neutral coupling circuit into a single package. The power supply inside the combined unit provides power for a PL Smart Transceiver-based product while a communication transformer couples the communication signal to the product over a common pair of low-voltage wires.
Off-the-Shelf Switching Supplies Most commercially available switching power supplies have been designed with some level of input noise filtering. Frequently this level of filtering is adequate if the supply’s fundamental switching frequency falls within the recommended ranges of Table 5.8 under all conditions.
Chapter 5 – Power Supplies for PL Smart Transceivers Power Supply Impedance and Noise Requirements Power Supply-Induced Attenuation The input stage of a switching power supply typically contains an EMC filter that includes one or more capacitors connected directly from line to neutral and, in many cases, additional capacitors from line and neutral to ground.
An example of a system that would benefit from an even greater input impedance would be one in which 100 or more PL Smart Transceiver-based devices were connected to a long twisted pair cable. In this case the input impedance of the power supply could limit either the maximum transmission distance and/or the maximum number of devices that could be connected to the cable.
Chapter 5 – Power Supplies for PL Smart Transceivers Figure 5.
Noise at the Power Supply Input In order to achieve maximum communication performance and to comply with the conducted emissions regulations such as CENELEC EN 50065-1 and FCC Part 15, a switching power supply input must not conduct excessive noise onto the power mains. A switching power supply contains an oscillator that operates at a frequency between 10kHz and several MHz.
Chapter 5 – Power Supplies for PL Smart Transceivers 90 Noise Level (dBuV) 80 Quasi-peak detector Average detector 70 60 50 40 30 20 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency (Hz) Figure 5.12 Switching Power Supply Input Noise Limits for C-band CENELEC Compliance 90 Noise Level (dBuV) 80 70 60 50 40 30 20 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency (Hz) Figure 5.
90 Quasi-peak detector Average detector Noise Level (dBuV) 80 70 60 50 40 30 20 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency (Hz) Figure 5.14 Switching Power Supply Input Noise Limits for A-band CENELEC Compliance 90 Noise Level (dBuV) 80 70 60 50 40 30 20 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Fr e que ncy (Hz ) Figure 5.
Chapter 5 – Power Supplies for PL Smart Transceivers Table 5.10 lists the endpoints of the straight lines shown in Figure 5.12, and Table 5.11 lists those shown in Figure 5.13. Table 5.12 lists the end points of the straight lines shown in Figure 5.14. Table 5.13 lists the levels shown in Figure 5.15. Table 5.
Table 5.12 Switching Power Supply Input Noise Limits for A-band CENELEC Compliance Noise Level (dBμV): Quasi-Peak Detector Noise Level (dBμV): Average Detector 9 89 N/A 70 72 N/A 70+ 30 N/A 90 30 N/A 90+ 70 N/A 150 66 56 500 56 46 5000 56 46 5000+ 60 50 30000 60 50 Frequency (kHz) Table 5.
Chapter 5 – Power Supplies for PL Smart Transceivers Figure 5.16 Optional Switching Power Supply Filter The C-band version of this filter has the attenuation characteristics shown in Figure 5.17, when connected to a 50Ω mains network. The characteristics of the A-band version of the filter into a 50Ω network are shown in Figure 5.18. If the power supply noise drops by less than the values indicated in the graph when the filter is added, it is likely due to parasitic coupling between the two inductors.
PL PS filter C-band.CIR 15 10 Attenuation (dB) 0 -10 Communication Frequencies (110kHz - 138kHz) -20 -30 110.055K,-39.802 -40 138.429K,-47.423 -50 -60 1K 10K 100K 1M Frequency (Hz) Figure 5.17 C-band Filter Frequency Response PL PS filter A-band.CIR 15 10 Attenuation (dB) 0 -10 Communication Frequencies (70kHz - 90kHz) -20 70.044K,-28.709 -30 89.948K,-34.689 -40 -50 -60 1K 10K 100K 1M Frequency (Hz) Figure 5.
Chapter 5 – Power Supplies for PL Smart Transceivers In some instances it is possible that noise radiated from either the power supply or the supply filter can couple into the inductors of the coupling circuit of the PL Smart Transceiver. The coupling circuit can then couple this noise onto the power mains. This problem can be diagnosed by disconnecting the transceiver's coupling circuit and then analyzing the conducted line noise.
Figure 5.19 10X Power Supply Noise Probe If the noise masks for either the VA or VDD5 power supplies are not met, then additional filtering must be added to the offending supply in order to bring it into compliance. In the event that extra filtering is needed an inductor of about 10µH can be added in series with the supply line.
110 -10 100 -20 90 -30 80 -40 70 Noise Level (dBV) Noise Level (dBuV) Chapter 5 – Power Supplies for PL Smart Transceivers -50 VA 60 -60 VDD5 (3kHz) ≤ VDD5 (?300Hz filter) 50 40 1.0E+04 -70 -80 1.0E+06 1.0E+05 Frequency (Hz) 110 -10 100 -20 90 -30 80 -40 70 VA -50 VDD5 (3KHz filter) ≤ VDD5 (?300Hz filter) 60 50 40 1.0E+04 -60 Noise Level (dBV) Noise Level (dBuV) Figure 5.20 VA and VDD5 Power Supply Output Noise Limits for C-band -70 1.0E+05 -80 1.
Tables 5.14 and 5.15 list the levels shown in Figures 5.20 and 5.21 respectively. Table 5.14 VA and VDD5 Power Supply Output Noise Limits for C-band Frequency (kHz) VA Noise Level w/3kHz filter (dBV) VDD5 Noise Level w/3kHz filter (dBV) 10-40 -20 -40 40-55 -20 -50 55-110 -30 -50 110-115 -40 -50 115-135 -40 -70 135-1000 -40 -50 Frequency (kHz) VDD5 Noise Level w/300Hz filter (dBμV) 110-138 -60 Table 5.
Chapter 5 – Power Supplies for PL Smart Transceivers 184 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 185
Chapter 6 – Design and Test for Electromagnetic Compatibility Introduction Products that communicate using public ac mains wiring generally need to demonstrate compliance with electromagnetic compatibility (EMC) standards from various regulatory agencies. This chapter provides information regarding the most effective ways to satisfy electromagnetic interference (EMI) and electrostatic discharge (ESD) requirements with Smart Transceiver-based products.
Conducted Emissions Testing Each PL Smart Transceiver reference design has been demonstrated to comply with both FCC Section 15.107 “Limits for carrier current systems” [1] and CENELEC EN 50065-1 “Signaling on low-voltage electrical installations in the frequency range 3kHz to 148.5kHz” Part 1 “General requirements, frequency bands and electromagnetic disturbances” [2].
Chapter 6 – Design and Test for Electromagnetic Compatibility EMI Remedies If a device does not pass conducted emission regulatory limits it is helpful to know whether the failing frequencies are from a switching power supply (fundamental or harmonics), communication harmonics, or other frequencies from other digital circuitry. If a failing frequency is related to the power supply, refer to the sections of Chapter 5 that cover power supply noise and mitigation techniques.
Table 6.1 EMC Suppression Capacitor Value vs.
Chapter 6 – Design and Test for Electromagnetic Compatibility Figure 6.
Design for Electrostatic Discharge (ESD) Compliance Reliable system design must consider the effects of ESD and steps must be taken to protect sensitive components. Static discharges occur frequently in low-humidity environments when operators touch electronic equipment. Keyboards, connectors, and enclosures themselves can provide paths for static discharges to reach ESD sensitive components such as the PL Smart Transceiver.
Chapter 6 – Design and Test for Electromagnetic Compatibility Figure 6.
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 193
Chapter 7 –Communication Performance Verification Introduction This chapter describes a simple “black box” testing methodology for determining whether or not the basic communication performance of a PL Smart Transceiver-based product has been significantly compromised. This procedure works equally well for products employing L-N or L-E coupling.
Power Line Test Isolator The circuit shown in Figure 7.1 is used to create a power mains environment that is isolated from the noise and loading present on typical power mains. When properly constructed, the circuit provides 60 to 80dB of isolation between the power mains and the product under test at the communication frequencies of the PL Smart Transceiver. The effectiveness of the circuit should be verified by using a pair of PLCA-22 analyzers communicating between the power mains input and the output.
Chapter 7 –Communication Performance Verification • • A four (or more) outlet power strip which does not include surge protection, neon lights, or noise filtering circuitry. One personal computer configured with a PL-20 network interface (such as PCLTA-20/SMX network interface with PLM-22 SMX transceiver, or U20 USB network interface). Test Equipment to be Constructed The following additional equipment will need to be constructed for testing: “5Ω Load” Circuit This circuit, as shown in Figure 7.
Impedance Circuit This circuit, as shown in Figure 7.4, should be built in a suitable enclosure with bulkhead BNC jacks (AMP 227755-x or equivalent). This impedance circuit, placed in series with the output path of a PLCA-22 analyzer, effectively increases its output impedance. This will allow for a more sensitive measurement of the receive mode impedance of the product under test. 88.7Ω ±1%, 1/4W Figure 7.
Chapter 7 –Communication Performance Verification Good Citizen Verification The following steps are used to verify that the Unit Under Test (UUT) does not inject unwanted noise onto the power mains or excessively load the power mains. Unintentional Output Noise Verification The following procedure determines if the UUT is generating unwanted noise which might hinder its communication performance or that of other devices on the power mains. 1.
If either of the -72dB LEDs is on solid or if either of the -66dB LEDs flash or if the PKD LED flashes more than once per minute, then excessive noise or interference is present. This could be caused by one or more of the following sources: • • • The UUT is generating unwanted noise internally. This is most often associated with on-board switching power supplies. If the UUT includes a switching power supply, verify that the power supply noise masks of Chapter 5 have been met.
Chapter 7 –Communication Performance Verification PLCA-22 See text before powering unit. Unit Under Test Recv (UUT) service pin packet detect LED To power mains Isolated Power Line ISOLATOR PLCA-22 coax Send TxVpp:10V Impedance Circuit (see fig. 7.4) coax PL-20 L-N 240V Coupler Figure 7.
Transmit Performance Verification Use the following procedure to verify that the transmit output impedance of the UUT is low enough to adequately drive low impedance loads. 1. With a single PLCA-22 analyzer in idle mode (no packets being transmitted) and set for the same band of operation as the UUT, Internal and Line-to-Neutral coupling, connect the analyzer, the UUT, the “5Ω load”, and the Isolator as shown in Figure 7.
Chapter 7 –Communication Performance Verification Receive Performance Verification The receive performance verification procedure requires a software tool to measure the number of uncorrupted packets received by the UUT. Packet error rate is then calculated based on the number of packets sent and the number correctly received. Packet Error Measurement with NodeUtil A utility called NodeUtil (nodeutil.exe) is used to measure packets correctly received by the UUT.
Receive Performance Verification Procedure The following procedure is used to verify that the receive sensitivity of the UUT is correct. Determination of receive sensitivity is made by monitoring the physical layer error rate while increasing the level of signal attenuation between a reference transmitter and the UUT. 1. Insure that the UUT application program is not sending messages (depending on the application it may be necessary to set the device status to “applicationless” to accomplish this). 2.
Chapter 7 –Communication Performance Verification PLCA-22 Unit Under Test (UUT) Recv PC containing a PCLTA-20 service pin packet detect LED To power mains Isolated Power Line ISOLATOR coax PL-20 L-N 240V Coupler PLCA-22 coax Send TxVpp:3.5 Attenuation Circuit (see fig. 7.5) coax PL-20 L-N 240V Coupler Figure 7.9 Receive Performance Verification 8. After moving the cursor to the Attn field, press the CHANGE and ENTER keys on the Send PLCA-22 analyzer to increment the Attn level by 6dB.
The overall signal attenuation between the Send PLCA-22 analyzer and Recv PLCA-22 analyzer shown in Table 7.1 is the sum of the attenuation level of the attenuator circuit and the Attn level of the Send PLCA-22 analyzer plus 6dB resulting from the use of a 3.5Vp-p transmit level on the Send PLCA-22 analyzer. A properly performing PL Smart Transceiver-based product will show a low packet error rate (<3%) up to an overall attenuation of 78dB r.e. 7Vpp (72dB for secondary frequency).
Chapter 7 –Communication Performance Verification Table 7.
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 207
Chapter 8 – PL Smart Transceiver Programming Introduction Certain parameters of PL Smart Transceivers are programmed by the developer. This chapter provides an explanation of the various choices and how they are programmed by way of the NodeBuilder® Development Tool, Mini EVK Evaluation Kit, or ShortStack® Developer’s Kit. The factory preprogrammed settings for the PL 3120 and PL 3170 Smart Transceivers are in accordance with the PL-20N “standard transceiver type” described in this chapter.
access protocol while still maintaining the benefits of the LonTalk protocol. When the CENELEC access protocol is enabled, overall network throughput is reduced by 11%. The CENELEC access protocol must be enabled to meet regulatory requirements in countries that follow CENELEC regulations (i.e., most European countries). It is recommended that the CENELEC access protocol be disabled on products that will be used in any country that does not follow CENELEC regulations, in order to maximize throughput.
Chapter 8 – PL Smart Transceiver Programming ! When power management is enabled, PL Smart Transceivers require a VA supply voltage of 13.0V before they can be assured of transmitting a packet. A product with a fixed VA power supply less than or equal to 13.0V should never have power management enabled because it might not be allowed to transmit. Likewise a device whose power supply relies on power management to operate correctly should never have the power management feature disabled. Table 8.
Table 8.
Chapter 8 – PL Smart Transceiver Programming PL Smart Transceiver Channel Definitions The appropriate standard transceiver type (PL-20N, PL-20C, PL-20N-LOW, PL-20C-LOW, PL-20A or PL-20A-LOW) is selected on the NodeBuilder Hardware Template Properties page, as shown in the figure below: . Figure 8.1 Choosing the Standard Transceiver Type in NodeBuilder Tool PL Smart Transceiver Clock Speed Selection When operating in A-band the PL Smart Transceiver uses a 6.5536MHz crystal and thus a clock speed of 6.
ShortStack Developer’s Kit The ShortStack Developer’s can be used to develop a prototype or production device based on the PL 3120, 3150, or 3170 Smart Transceiver, with an application that runs on an attached microcontroller. Any release of the ShortStack Developer’s Kit can be used to develop applications for the PL 3120 or 3150 Smart Transceiver. ShortStack 2.1 (or newer) is required to develop applications for the PL 3170 Smart Transceiver. ShortStack 2.
Chapter 8 – PL Smart Transceiver Programming Transceiver. If a production line is capable of producing one completed device every 10 seconds, then 3 NodeLoad stations will be required to keep up with the production volume. Isolators will be required at each NodeLoad station to prevent communication from occurring between stations. See the Power Line Test Isolator section in Chapter 7 for details on how to build your own isolator.
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 215
Appendix A – PL Smart Transceiver Reference Designs Introduction This appendix describes the implementation of the external, discrete interface circuitry for the PL 3120, PL 3150 and PL 3170 Smart Transceivers. The interface circuitry includes the front-end filter for the receiver and the power amplifier for the transmitter. The interface is comprised of roughly fifty components, primarily resistors and capacitors.
Development Support Kit Contents The PL Smart Transceiver DSK includes the following reference designs: Reference Design Number PL Smart Transceiver Model Description Zip File Name 1200F PL3120-E4T10 or PL3170-E4T10 2 layer 23x63mm PCB layout Reference Designs\1200 with 1-sided component mounting and 1Ap-p transmit amplifier 1201F PL3120-E4T10 or PL3170-E4T10 4 layer 20x38mm PCB layout Reference Designs\1201 with 2-sided component mounting and 1Ap-p transmit amplifier 1204E PL3120-E4T10 or PL3170
Appendix A – PL Smart Transceiver Reference Designs Reference Design Files For each reference design the following files are provided. File Name Description Circuit Description.pdf Document describing the operation of the reference circuitry Using the Reference Layouts.pdf Explains how to use the reference layout files Using the Viewer.pdf Description of how to obtain and use a free P-CAD® viewer 012-xxxx-51_R_Schematic.dsn Schematic design file in OrCAD® format 012-xxxx-51_R_Schematic.
Reference Design Specifications Recommended Operating Conditions for Reference Designs with 1Ap-p Transmit Amplifier Symbol Parameter Min Typ Max Unit VARX VA Supply Voltage - Receive Mode 8.5 12.0 18.0 V VATX VA Supply Voltage - Transmit Mode (1) 10.8 12.0 18.
Appendix A – PL Smart Transceiver Reference Designs Recommended Operating Conditions for Reference Designs with 2Ap-p Transmit Amplifier Symbol Parameter Min Typ Max Unit VARX VA Supply Voltage - Receive Mode 12.0 15.0 18.0 V VATX VA Supply Voltage - Transmit Mode (1) C-band A-band 14.25 12.0 15.0 15.0 18.0 18.
Each DSK reference design has been subjected to thorough electrical and thermal analysis which addresses all of the above issues.
Appendix A – PL Smart Transceiver Reference Designs 222 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 223
Appendix B –PL Smart Transceiver-Based Device Checklist Introduction This appendix includes a checklist that can be used to verify critical design elements described in this user’s guide. Verifying compliance with these items is an important step toward insuring that a Smart Transceiver-based product realizes the full communication performance of the PL Smart Transceiver. All of the items listed below should be carefully checked prior to releasing a design either for review by Echelon or for production.
Device Checklist PL Smart Transceiver Development Support Kit (DSK) Reference Design (refer to the DSK and Chapter 2) Item 1 OK? Description Reference design used:_______________________________________ Use the name of the ZIP archive file containing the reference design document (for example, PL_3120_DSK_2L1S_TX1_1_R). 2* 3 Check that the reference design portion of the circuit is an accurate copy of the reference layout without any deviations.
Appendix B –PL Smart Transceiver-Based Device Checklist 15 The proper parts are specified for Q2 and Q3 of the reference design; OnSemi BC847BPDW1T1G and OnSemi BC847BDW1T1G respectively. 16 The proper transistors are specified for Q4 and Q5 of the reference design; Zetex FCX690B or STM 2STF1360 for Q4 and Zetex FCX790A or STM 2STF2360 for Q5 for the 1Ap-p transmit amplifier (Zetex ZXT690B and ZXT790A respectively for the 2Ap-p amplifier).
30 Diode D102 – Ground clamp diode Current Rating ≥1A Reverse breakdown ≥50V Forward voltage ≤1.0V@1A/25C Surge current ≥30A for 8.3ms Reverse recovery ≤25ns Reverse current ≤100uA@100C Typical capacitance ≤40pF@4V 31 * Fuse F101 – Line fuse 6A or 6.3A rating (or higher if in accordance with varistor vendor recommendations) Proper voltage rating Time-lag (slow-blow type) 32 Inductor L101 – Shunt coupling inductor (for a non-transformer isolated coupling circuit) 1.
Appendix B –PL Smart Transceiver-Based Device Checklist 41 The signal return traces from the AC mains connection to the transmit amplifier are a copper plane or ≥1.3mm wide and ≤15cm long (before becoming a ground plane). 42 Traces from the point where D101 taps into the signal path to the point where C103 connects back to ground are ≥1.3mm wide and ≤2cm long. 43 The traces between the VA input of the transmit amplifier and the point where C103 connects back to ground are at least 1.
56 The output noise masks shown in Chapter 5 are satisfied using measurements taken over the full range of anticipated loads. Design and Test for Electromagnetic Compatibility (refer to Chapter 6) 57 Product enclosure is made from the following material(s) _____________________________ Method of ESD mitigation is _____ A) The product is sealed to prevent static discharges from reaching sensitive circuitry. B) A path is provided for ESD currents to be shunted around sensitive circuitry.
Appendix B –PL Smart Transceiver-Based Device Checklist PL Smart Transceiver Programming (refer to Chapter 8) 73 The correct standard transceiver type is defined for the transceiver by way of NodeBuilder 3.1, Mini EVK 1, or newer: 1. A-band Power management disabled: PL-20A Power management enabled: PL-20A-LOW 2.
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 231
Appendix C - Isolation Transformer Specifications 12μH-Leakage Transformer Specifications 1 3 2 4 Schematic Table C.1 12μH-Leakage Transformer Electrical Specifications Parameter Min Turns Ratio (1-2):(3-4) Typ Max Units 0.20 ohm 1.25 mH 1.0 DC Resistance 1-2, 3-4 Magnetizing Inductance 1-2 Dry, @100kHz, 1VRMS 0.75 Magnetizing Inductance 1-2, Wet, @100kHz, 1VRMS, plus 15mADC 0.75 Leakage Inductance 1-2 (3-4 shorted) @100kHz, 1VRMS 10.8 1.0 mH 12.0 13.
Low-Leakage Transformer Specifications 1 5 Schematic 4 8 Table C.3 Low-Leakage Transformer Electrical Specifications Parameter Min Turns Ratio (1-4):(5-8) Typ Max Units 0.35 ohm 1.8 mH 1.0 DC Resistance 1-4, 5-8 Magnetizing Inductance 1-4 Dry, @100kHz, 1VRMS 0.75 Magnetizing Inductance 1-4, Wet, @100kHz, 1VRMS, plus 30mADC 0.75 1.45 mH Leakage Inductance 1-4 (3-4 shorted) @100kHz, 1VRMS 1.
Appendix C - Isolation Transformer Specifications 234 PL 312/ PL 3150/PL 3170 Power Line Smart Transceiver Data Book
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 235
Appendix D – Manufacturing Test and Handling Guidelines Production Test Guidelines This appendix describes recommended production test procedures that can be used to verify the communication functionality of each PL Smart Transceiver-based device. The production test procedure described below is applicable for PL Smart Transceiver-based devices operating in either the A or C bands.
Transmitter Performance Verification Transmitter performance is verified by causing the unit under test to transmit a packet into a low impedance load (approximately 5 ohms), and then verifying that an acceptable amplitude signal is produced. Initiating a Packet Transmission A simple way of causing the PL Smart Transceiver-based device to transmit a packet is to communicate with it over the power mains connection using a standard network management command.
Appendix D – Manufacturing Test and Handling Guidelines A/D, D/A- based Test System This section describes a practical test system that can perform both transmit and receive performance verification. Hardware Description The test system should have the following components.
The interface board performs three functions: • • • The 4.7 ohm resistor in series with the 1uF X2 capacitor provides a low impedance load for the transmit level verification test. The 15k ohm resistor, in conjunction with the 4.7 ohm resistor and 1uF X2 capacitor, provide approximately 70dB of attenuation of the message generated by the D/A converter as part of the receive mode test. The 1N4148 diode, 0.
Appendix D – Manufacturing Test and Handling Guidelines 7V p-p D/A signal QueryID message send to UUT before attenuation QueryID message seen by the UUT (70dB attenuation) Response from UUT to QueryID message into 5 ohm load A/D signal Trigger signal Figure D.2 Test Cycle Waveforms Notes on Missed Messages Due to the adaptive sensitivity algorithms inside the PL Smart Transceiver, it is statistically possible for a good transceiver to miss a single packet.
The simplest method of verifying the test system background noise is to connect one PLCA-22 Power Line Communications Analyzer, Echelon Model 58022, to the UUT port of the test system. The PLCA-22 can be used to monitor the noise level via its signal strength bar graph LED. The signal strength meter displays the mains signal level after being filtered by the transceiver’s internal digital signal processing. Thus the meter displays only the noise that will affect the PL Smart Transceiver.
Appendix D – Manufacturing Test and Handling Guidelines Handling Precautions and Electrostatic Discharge All CMOS devices have an insulated gate that is subject to voltage breakdown. The gate oxide for the PL Smart Transceiver breaks down at a gate-source potential of about 10V. The high-impedance gates on the PL Smart Transceiver are protected by on-chip networks. However, these on-chip networks do not make the IC immune to ESD.
4 1 5 R = 1M Ω 3 NOTES: 1. 1/16 inch conductive sheet stock covering bench-top work area. 2. Ground strap. 3. Wrist strap in contact with skin. 2 4. Static neutralizer. (Ionized air blower directed at work.) Primarily for use in areas where direct grounding is impractical. 5. Room humidifier. Primarily for use in areas where the relative humidity is less than 45%.
Appendix D – Manufacturing Test and Handling Guidelines 244 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book
PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 245
Appendix E – References This appendix provides a list of the reference material used in the preparation of this manual. [1] 47CFR15, Subpart B (Unintentional Radiators), U.S. Code of Federal Regulations. [2] CENELEC EN 50065-1:2001 “Signaling on low-voltage electrical installations in the frequency range 3kHz to 148.5kHz” Part 1 “General requirements, frequency bands and electromagnetic disturbances”.
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