Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 97
Oneshot Output
A timer/counter can be configured to generate a single pulse of programmable duration. The asserted state can be either
logic high or logic low. Retriggering the oneshot before the end of the pulse causes it to continue for the new duration.
Table 3.8 in the Notes section at the end of this chapter gives the resolution and maximum time of the pulse for various
clock selections. This object is useful for generating a time delay without intervention of the application processor (see
Figure 3.52).
END
OF
io_out()
START
OF 2ND
io_out()
T = User-defined oneshot output period
T
ONESHOT
OUTPUT
TIME
HARDWARE
UPDATE/
RETRIGGER
HARDWARE
UPDATE
START
OF 1ST
io_out()
t
fout
t
fout
System Clock
Divide Chain
Timer/Counter 1
Timer/Counter 2
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
High Current Sink Drivers
T
IO11
t
jit
t
ret
Symbol Description Typ @ 10MHz Max
t
fout
Function call to output update 96 µs —
t
ret
Return from function 13 µs —
t
jit
Output duration jitter — 1 timer/counter
clock period*
Figure 3.52 Oneshot Output Latency Values
*Timer/counter clock period = (2000ns * 2
∧
(clock))/(input clock in MHz).
While the output is still active, a subsequent call to this function will cause the update to take effect immediately,
extending the current cycle. This is, therefore, a retriggerable oneshot function.