Datasheet

SPEC No.
LCP-1109027
MODEL No.
LS013B4DN04
PAGE
15
6-5) Input Signal Timing Chart
6-5-1 Data update mode (1 line)
Updates data of only one specified line. (M0=”H”、M2＝”L”)
SCS
SI
M0 M1 M2 DM
Y
DM
Y
DM
Y
DM
Y
DM
Y
A
G0
A
G1
A
G2
A
G3
A
G4
A
G5
A
G6
DM
Y
D1 D2 D3 D4 D93 D94 D95 D96 DUMMY DATA
(
don't care
)
SCLK
tsSI thSI
tsSCS
Data writing period
(96ck)
Data transfer period
(16ck)
Mode selection period
(3ck+5ckDMY)
twSCLKHtwSCLKL
twSCSH
Gate line address period
(7ck+1ckDMY)
thSCS
twSCSL
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
When “L”, display mode (maintain memory internal data).
M1: Frame inversion flag.
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
M2: All clear flag.
Refer to 6-5-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
※ Data write period
Data is being stored in 1
st
latch block of binary driver on panel.
※ Data transfer period
Data written in 1
st
latch is being transferred (written) to pixel internal memory circuit.
※For gate line address setting, refer to 6-6) Input Signal and Display.
※M1: Frame inversion fl is enaled when EXTMODE=”L”.
※When SCS becomes “L”, M0 and M2 are cleared.