Datasheet

SPEC No.
LCP-1109027
MODEL No.
LS013B4DN04
PAGE
16
6-5-2 Data Update Mode (Multiple Lines)
Updates arbitrary multiple lines data. (M0=”H”、M2＝”L”)
SCS
SI
DUMMY DATA(don't care)
SCLK
DUMMY DATA(don't care)
DUMMY DATA(don't care)D95 DMYAG6AG5AG4AG0 AG1D96
AG3 DMYAG6AG5AG4 D94 D95 D1D1 D2 D3 DMYAG6AG5DMY DMY D2AG1D4 AG0D93 D9 6M0 M2 DMY DMYM1 DMY
D95 D96D2 D94D1
AG0 AG1 AG2
tsSI thSI
tsSCS
GL1
Data transfer period
(96ck)
GL2
Mode selection period
(3ck+5ckDMY)
GL(n)th line
Data writing period
(96ck)
Data transfer period
(16ck)
GL(n-1)th Line
thSCS
twSCLKHtwSCLKL
twSCSLtwSCSH
twSCSH
Gate line address period
(7ck+1ckDMY)
Data transfer period
(8ck(Dymmy)+7ck(address)+1ck(Dummy)=16ck)
Data transfer period
(8ck(Dummy)+7ck(address)+1ck(Dummy)=16ck)
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
When “L”, display mode (maintain memory internal data).
M1: Frame inversion flag.
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
M2: All clear flag.
Refer to 6-5-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
※ Data write period
Data is being stored in 1
st
latch block of binary driver on panel.
※ Data transfer period
For example, during GL2nd line data transfer period, GL 2
nd
line address is latched and GL1st
line data is transferred from 1
st
latch to pixel internal memory circuit at the same time.
※ For gate line address setting, refer to 6-6) Input Signal and Display.
※ Input data continuously.
※ M1: Frame inversion flag is enabled when EXTMODE=”L”.
※ When SCS becomes “L”, M0 and M2 are cleared.