User manual

LPC3250 Developer’s Kit v2 - User’s Guide
Page 13
Copyright 2013 © Embedded Artists AB
3.1.11 Schematic Page 4: NAND Flash
A 1 Gbit (128 MByte) NAND flash is used (K9F1G08 from Samsung). The chip is powered by 3.3V and
has 8-bit databus width. The NAND flash builds on a single-level cell (SLC) technology and has a page
size of 2112 bytes (2,048 + 64 bytes). Note that the chip is not directly accessible via the memory bus.
Instead, all accesses must be done via the on-chip NAND flash controller of the LPC3250.
The NAND FLASH has an optional busy output that can be used for controlling the erase/program
operations with better precision. This signal is connected to GPO19 and is also available on the
(SODIMM) expansion connector. For compatibility with other OEM boards, the busy signal can also be
routed to a suitable (i.e., free) input pin. The OEM Base Board can connect the signal to GPIO72 by
inserting a jumper between pin 3-4 on JP2. This feature is not needed for the LPC3250 OEM board,
where the busy signal is connected tp GPO19.
Also note that the busy status of the chip is available under software control so the hardware signals is
not strictly needed.
3.1.12 Schematic Page 4: Buffers to External Interface
The LPC3250 memory interface is available on the expansion connector. The data bus width is 16-bits
on the external interface. The relevant signals are buffered. The following four static memory regions
are available for external access:
 External static bank #0 (0xE000 0000 – 0xE0FF FFFF)
16-bit databus width and 16MByte in size.
 External static bank #1 (0xE100 0000 – 0xE1FF FFFF)
16-bit databus width and 16MByte in size.
 External static bank #2 (0xE200 0000 – 0xE2FF FFFF)
16-bit databus width and 16MByte in size.
 External static bank #3 (0xE300 0000 – 0xE3FF FFFF)
16-bit databus width and 16MByte in size.
By default (R44 = 0 ohm, R43 not mounted), signal N_ABUF_EN is pulled low and the two buffers for
address and control signals (U13 and U14) are enabled and act as output (from the LPC3250 OEM
Board).
The buffered version of the LPC3250 signal OE controls the direction of the data bus buffer (U15).
During read operations the buffer acts as an input and during write operations it acts as an output. The
data bus buffer is controlled by the signals BLS0 and BLS1, each controlling lower and upper bytes of
the 16-bit databus. These signals are active when accessing the external static memory regions.
The buffers are dual voltage buffers and act as level translators between the internal 1.8V signal levels
and the external levels. Connect the external bus voltage to VDD_EXT. See the datasheet of
74AVCA164245 for exact details about voltage range. Normally 3.3V powering is used on the external
side.
3.2 Memory Layout
The external memory controller on the LPC3250 defines eight memory regions. See table below for
details about usage.
Name
Control
signal
Address range
Memories on LPC3250
OEM Board
External memory bus
comment
Static memory #0
CS0
0xE000 0000 –
0xE0FF FFFF
Available for external
use.
Static memory #1
CS1
0xE100 0000 –
0xE1FF FFFF
Available for external
use.