User manual

LPC3250 Developer’s Kit v2 - User’s Guide
Page 14
Copyright 2013 © Embedded Artists AB
Static memory #2
CS2
0xE200 0000 –
0xE2FF FFFF
Available for external
use.
OEM Base Board can
connect a parallel NOR
flash to this chip select.
Static memory #3
CS3
0xE300 0000 –
0xE3FF FFFF
Available for external
use.
OEM Base Board can
connect a 16-bit parallel
register to this chip
select.
Dynamic memory #0
DYCS0
0x8000 0000 –
0x9FFF FFFF
SDRAM (512 MBit = 64
MByte in size)
Cannot be accessed on
external memory bus.
Dynamic memory #1
DYCS1
Cannot be accessed.
As seen in the table above, it is only the static memory regions that are available on the external
memory bus from the LPC3250 OEM Board. The data bus buffers on the LPC3250 OEM Board are
controlled automatically and only enabled when a static memory region is accessed. The address and
control bus buffers are always enabled.
Note that the BLS0 and BLS1 pins must be initialized for these functionalities. Else the buffer control
will not work correctly.
3.3 LEDs
P2.10, P2.11 and P2.12 controls three LEDs on the LPC3250 OEM Board. The LED driving is isolated
via mosfet transistors so P2.10, P2.11 and P2.12 are not loaded because of this.