User manual

LPC4357 Developer’s Kit - User’s Guide
Page 10
Copyright 2013 © Embedded Artists AB
3 LPC4357 OEM Board Design
Please read the LPC4357 OEM Board datasheet and associated schematic for information about the
board. Some additional information about the LPC4357 OEM Board is presented below.
3.1 Memory Layout
The external memory controller on the LPC4357 defines eight memory regions. See table below for
details about usage.
Name
Control
signal
Address range
Memories on LPC4357
OEM Board
External memory bus
comment
Static memory #0
CS0
0x1C00 0000 –
0x1CFF FFFF
Available for external
use.
OEM Base Board can
connect a parallel NOR
flash to this chip select.
Static memory #1
CS1
0x1D00 0000 –
0x1DFF FFFF
NAND FLASH (1 GBit =
128 MByte in size)
Not available for
external use.
It is however possible
to disable NAND flash
chip by removing R25
on LPC4357 OEM
Board.
Static memory #2
CS2
0x1E00 0000 –
0x1EFF FFFF
Available for external
use.
OEM Base Board can
connect a 16-bit parallel
register to this chip
select.
Static memory #3
CS3
0x1F00 0000 –
0x1FFF FFFF
Available for external
use.
Dynamic memory #0
DYCS0
0x2800 0000 –
0x2FFF FFFF
SDRAM (256 MBit = 32
MByte in size)
Cannot be accessed on
external memory bus.
Dynamic memory #1
DYCS1
0x3000 0000 –
0x3FFFF FFFF
Cannot be accessed on
external memory bus.
As seen in the table above, it is only the static memory regions that are available on the external
memory bus from the LPC4357 OEM Board. The data bus buffers on the LPC4357 OEM Board are
controlled automatically and only enabled when a static memory region is accessed. The address and
control bus buffers are always enabled.
Note that the BLS0, BLS1, BLS2 and BLS3 pins must be initialize for these functionalities. Else the
buffer control will not work correctly.
3.1.1 NAND Flash
Note that the NAND flash is connected after the memory bus buffers, i.e., on the same side as the
LPC4357 OEM Board expansion signals. This is to allow flexibility in NAND flash usage and reduce
loading on memory bus that is directly connected to the SDRAM.