User manual

LPC4357 Developer’s Kit - User’s Guide
Page 5
Copyright 2013 © Embedded Artists AB
1 Document Revision History
Revision
Date
Description
PA1
2012-10-29
First version.
PA2
2012-12-08
Added information about ESD sensitive JTAG interface.
PA3
2013-01-21
Minor clarifications.
PA4
2013-04-08
Clarified that JP4 must be shorted (jumper installed) in order for the
LPC4357 SWD/JTAG interface to function.
PA5
2013-06-04
Added information about external SDRAM frequency and
CLK2_OUT signal relation, see section 5.6.6
PA6
2013-07-26
Updated section 5.4.1 for DFUSec ver 1.10.