User manual

LPC4357 Developer’s Kit - User’s Guide
Page 57
Copyright 2012 © Embedded Artists AB
Signal CLK2_OUT can only be used as a general clock signal if the external SDRAM is not
used/activated. If external SDRAM is not used on the LPC4357 OEM board then there are no
limitations on the core clock frequency of the LPC4357. It can run at up to 204 MHz.
On the OEM base board (on which the LPC4358 OEM board is mounted) SODIMM pad/pin 115 is
connected to signal GPIO68_I2S-MCLK, which is routed a long distance over the base board. This will
distort the CLK2_OUT signal seen by the LPC4357 and, as a result, limit the core clock operating
frequency when the external SDRAM is used. The problem limits the frequencies to 96/96MHz
(core/emc frequency) and 144/72MHz.
By following the solutions outlined in the separate note document, full operating speed can be
achieved, which means 102/102MHz and 204/102MHz operation.
5.6.7 JTAG/SWD Connection Problems
Note that JP4 shall be shorted in order to enable the JTAG/SWD interface on the LPC4357. JP4
might not be inserted by default on the OEM Base Board.