User manual

LPCXpresso Experiment Kit - User’s Guide
Page 68
Copyright 2013 © Embedded Artists AB
The suggested program structure is presented in the code block below.
//Time multiplexed loop for controlling two 7-segment digits
while (1)
{
//Calculate value to present on display, e.g. read ADC input #0
...
//Disconnect anode of digit #2 and reset segment outputs
...
//Connect anode of digit #1 to +3.3V
...
//Output value on digit #1 (control segment outputs)
...
//Wait 5ms
...
//Disconnect anode of digit #1 and reset segment outputs
...
//Connect anode of digit #2 to +3.3V
...
//Output value on digit #2 (control segment outputs)
...
//Wait 5ms
...
}
Implement the time multiplexed control above and create a program just like on the previous
experiment that presents the value of analog input #0 – not on one digit (0-9) but on two digits (0-99).
Adjust the conversion function accordingly.
7.9.5 Lab 8e: Control 7-segment Display via Shift Register
In this experiment we shall use a shift register to control the LED segments. This is the circuit that is
drawn in the schematic and designed on the pcb. The idea is to use a serial bus (called SPI) but in this
experiment we will not use this bus. That is for a later experiment. Instead you shall emulate the serial
bus with GPIO operations. Three signals shall be controlled, called SSEL, SCK and MOSI. These are
connected to GPIO_4, GPIO_3 and GPIO_1, respectively. Figure 40 illustrates the timing of the
signals. It is the signal MOSI that outputs the different segment values. The SCK signal clocks in the
value of the MOSI signal on its rising edge. Signal SSEL shall be low during the clock-in process.
When SSEL goes high, the value on the shift register is transferred to the outputs of the shift register.
Check the datasheet of the shift register, 74HC595 for details about the shift register operation. Note
the order of the bits on the MOSI signals. First the DP bit shall be output, and then segment G, etc. A
zero will turn the segment on and a one will turn it off.
Figure 40 – SPI Shift Register Communication
DP G F E D C B A
SSEL
SCK
MOSI