User manual

LPCXpresso Experiment Kit - User’s Guide
Page 80
Copyright 2013 © Embedded Artists AB
/*****************************************************************************
** Function name: SSP0Init
**
** Descriptions: SSP port #0 initialization routine
** Note that GPIO control of SSEL signal is not done, must
** be done separately.
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void SSP0Init( void )
{
uint8_t i, dummy = dummy;
LPC_SYSCON->PRESETCTRL |= (0x1<<0); /* Reset SSP0 block */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11); /* Enable SSP0 block */
LPC_SYSCON->SSP0CLKDIV = 0x02; /* Clock to SSP0 block is divided by 2 */
/* which will equal 24MHz clock rate */
/* SSP I/O config */
LPC_IOCON->PIO0_8 &= ~0x07;
LPC_IOCON->PIO0_8 |= 0x01; /* SSP0 MISO */
LPC_IOCON->PIO0_9 &= ~0x07;
LPC_IOCON->PIO0_9 |= 0x01; /* SSP0 MOSI */
LPC_IOCON->SCK_LOC = 0x01; /* Needed to conf. PIO2_11 as SCLK */
LPC_IOCON->PIO2_11 &= ~0x07;
LPC_IOCON->PIO2_11 |= 0x01; /* SSP0 SCLK */
/* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */
LPC_SSP0->CPSR = 0x2;
/* Set DSS data to 8-bit, Frame format SPI, mode #0 (CPOL = 0, CPHA = 0)
and SCR is 7, which equals 24MHz / (CPRS*(SCR+1)) = 1500 kHz SCLK frequency */
LPC_SSP0->CR0 = 0x0707;
/* clear the RxFIFO */
for ( i = 0; i < FIFOSIZE; i++ )
dummy = LPC_SSP0->DR;
/* Master mode */
LPC_SSP0->CR1 = SSPCR1_SSE;
}
/*****************************************************************************
** Function name: SSP0Send
**
** Descriptions: Send a block of data to the SSP port, the
** first parameter is the buffer pointer, the 2nd
** parameter is the block length.
**
** parameters: buffer pointer, and the block length
** Returned value: None
**
*****************************************************************************/
void SSP0Send( uint8_t *pBuf, uint32_t length )
{
uint32_t i;
uint8_t dummy = dummy;
for ( i = 0; i < length; i++ )
{
/* Move on only if NOT busy and TX FIFO not full. */
while ( (LPC_SSP0->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF )
;
LPC_SSP0->DR = *pBuf;
pBuf++;
while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE )
;
/* Whenever a byte is written, MISO FIFO counter increments, Clear FIFO
on MISO. Otherwise, when SSP0Receive() is called, previous data byte
is left in the FIFO. */