User manual

LPCXpresso Experiment Kit - User’s Guide
Page 87
Copyright 2013 © Embedded Artists AB
7.13 Work with Interrupts
In this experiment you will learn how to incorporate interrupts in your program. Interrupts are a
powerful concept in embedded programming. It is a way to interrupt the normal program execution flow
to service something else quickly. This “something else” is typically a peripheral block that needs to be
serviced or it is an external event that needs attention/a reaction.
There is a functional block in the LPC111x that is called the Nested Vectored Interrupt Controller
(NVIC). It is an integral part of the Cortex-M0 core. The NVIC can be regarded as a peripheral block,
but a special one. It is programmed/setup via registers, just like any other peripheral. It supports 32
interrupt sources and there are four programmable priority levels. Individual interrupts can be masked
(i.e., disabled) in the NVIC. It is also possible to generate an interrupt via software - writing in a special
register will trigger the specified interrupt.
An indication that the NVIC is a special function block is that all information can be found in chapter
28.6.2 – Nested Vectored Interrupt Controller in the LPC111x user’s manual. This is the chapter that
contains Cortex-M0 core information. Chapter 6 - LPC111x/LPC11Cxx Nested Vectored Interrupt
Controller (NVIC) basically only contains a table (Table 54) that lists the different interrupt sources in
the LPC111x. Almost all of the 32 sources are used.
Have a look in file LPC11xx.h. It is found in the CMSIS library, in the inc sub-directory. Amongst
other things, the typedef declaration below is found in this file. It lists the names and numbers of
the different interrupt sources.
...
/* Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***********************************/
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt */
/****** LPC11xx Specific Interrupt Numbers ***************************************/
WAKEUP0_IRQn = 0, /* All I/O pins can be used as wakeup source. */
WAKEUP1_IRQn = 1, /* There are 13 pins in total for LPC11xx */
WAKEUP2_IRQn = 2,
WAKEUP3_IRQn = 3,
WAKEUP4_IRQn = 4,
WAKEUP5_IRQn = 5,
WAKEUP6_IRQn = 6,
WAKEUP7_IRQn = 7,
WAKEUP8_IRQn = 8,
WAKEUP9_IRQn = 9,
WAKEUP10_IRQn = 10,
WAKEUP11_IRQn = 11,
WAKEUP12_IRQn = 12,
SSP1_IRQn = 14, /* SSP1 Interrupt */
I2C_IRQn = 15, /* I2C Interrupt */
TIMER_16_0_IRQn = 16, /* 16-bit Timer0 Interrupt */
TIMER_16_1_IRQn = 17, /* 16-bit Timer1 Interrupt */
TIMER_32_0_IRQn = 18, /* 32-bit Timer0 Interrupt */
TIMER_32_1_IRQn = 19, /* 32-bit Timer1 Interrupt */
SSP0_IRQn = 20, /* SSP0 Interrupt */
UART_IRQn = 21, /* UART Interrupt */
ADC_IRQn = 24, /* A/D Converter Interrupt */
WDT_IRQn = 25, /* Watchdog timer Interrupt */
BOD_IRQn = 26, /* Brown Out Detect(BOD) Interrupt */
EINT3_IRQn = 28, /* External Interrupt 3 Interrupt */
EINT2_IRQn = 29, /* External Interrupt 2 Interrupt */
EINT1_IRQn = 30, /* External Interrupt 1 Interrupt */
EINT0_IRQn = 31, /* External Interrupt 0 Interrupt */
} IRQn_Type;
...