User’s Manual from Emerson Network Power ™ Embedded Computing ATCA-9305: ATCA® Blade with Dual Cavium Processors April 2009
The information in this manual has been checked and is believed to be accurate and reliable. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others. Emerson.
Regulatory Agency Warnings & Notices The Emerson ATCA-9305 meets the requirements set forth by the Federal Communications Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information is provided as required by this agency. This device complies with part 15 of the FCC Rules.
Regulatory Agency Warnings & Notices (continued) EC Declaration of Conformity According to EN 45014:1998 Manufacturer’s Name: Emerson Network Power Embedded Computing Manufacturer’s Address: 8310 Excelsior Drive Madison, Wisconsin 53717 Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC Directive and 1999/5/EC, RTTE Directive and their amending directives, Product: ATCA Blade Model Name/Number: ATCA-9305/10009986-xx has been designed and manufactured to
Regulatory Agency Warnings & Notices 10009109-01 (continued) ATCA-9305 User’s Manual iii
Regulatory Agency Warnings & Notices iv ATCA-9305 User’s Manual 10009109-01 (continued)
Contents 1 Overview Components and Features . . . . . . . . . . . 1-1 Functional Overview . . . . . . . . . . . . . . . . 1-3 Additional Information . . . . . . . . . . . . . . 1-4 Product Certification . . . . . . . . . . . . . 1-4 RoHS Compliance. . . . . . . . . . . . . . . . 1-5 Terminology and Notation . . . . . . . . 1-6 Technical References. . . . . . . . . . . . . 1-6 2 Setup Electrostatic Discharge . . . . . . . . . . . . . . 2-1 ATCA-9305 Circuit Board . . . . . . . . . . . . 2-1 Connectors . .
Contents (continued) Reset Command 4 . . . . . . . . . . . . . . . 5-7 Reset Command 5 . . . . . . . . . . . . . . . 5-7 Reset Command Sticky #1 . . . . . . . . 5-7 Reset Command Sticky #2 . . . . . . . . 5-8 Boot Device Redirection . . . . . . . . . . 5-8 Miscellaneous Control. . . . . . . . . . . . 5-9 Low Frequency Timer 1 and 2 . . . . . 5-9 RTM GPIO State . . . . . . . . . . . . . . . .5-10 RTM GPIO Control . . . . . . . . . . . . . .5-10 RTM Status . . . . . . . . . . . . . . . . . . . .
Contents (continued) Get Message Listener List . . . . . . . .7-45 System Firmware Progress Sensor . . . 7-45 Entities and Entity Associations . . . . . . 7-46 Sensors and Sensor Data Records . . . . 7-48 FRU Inventory . . . . . . . . . . . . . . . . . . . . . 7-50 E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 Base Point-to-Point Connectivity .7-52 HPM.1 Firmware Upgrade. . . . . . . . . . . 7-52 HPM.1 Reliable Field Upgrade Procedure . . . . . . . . . . . . . . . . . . . . .
Contents (continued) iminfo . . . . . . . . . . . . . . . . . . . . . . . . .9-22 isdram . . . . . . . . . . . . . . . . . . . . . . . .9-22 loop. . . . . . . . . . . . . . . . . . . . . . . . . . .9-22 memmap . . . . . . . . . . . . . . . . . . . . . .9-22 moninit . . . . . . . . . . . . . . . . . . . . . . .9-22 pci . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23 phy . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23 ping. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Figure 2-1: ATCA-9305 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2-2: Component Map, Top (Rev. 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Figure 2-3: Component Map, Bottom (Rev. 01). . . . . . . . . . . . . . . . . . . .
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Tables Table 1-1: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Table 1-2: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2: Typical Power Requirements. . . . . . . . . . . . . . . . . . . . .
Tables (continued) Table 7-14: xii ATCA-9305 User’s Manual Set FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 Table 7-15: Get FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 Table 7-16: Vendor Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 Table 7-17: Get Status Command . . . . . . . . . . .
Tables (continued) Table 8-3: Zone 3 Connector, J30 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Table 8-4: Zone 3 Connector, J31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Table 8-5: Zone 3 Connector, J33 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Table 9-1: Debug LED Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Registers Register 3-1: Data 31:24 (0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Register 3-2: Data 23:16 (0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Register 3-3: Data 15:8 (0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Register 3-4: Data 7:0 (0x3). . . . . . . .
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Section 1 Overview The ATCA-9305 is an Advanced Telecom Computing Architecture (AdvancedTCA®, ATCA®) blade based on dual Cavium OCTEON™ CN5860 processors and the Freescale™ Semiconductor MPC8548 management processor. This blade is targeted at security and packet-processing applications in the wireless and transport market segments. These markets include data-plane packet-processor, security co-processor, video compression, and pattern matching.
Overview: Components and Features Real-time Clock: The STMicroelectronics M41T00S RTC provides counters for seconds, minutes, hours, day, date, month, years, and century. The M41T00S serial interface supports I2C bus and has a super-cap backup capable of maintaining the clock for a minimum of two hours.
Overview: Functional Overview FUNCTIONAL OVERVIEW The following block diagram provides a functional overview for the ATCA-9305: Figure 1-1: General System Block Diagram Console RJ45 RJ45 Mag Mag Socketed ROM 512KB x8 KSL CPLD Console (ENG use only) Latched Adrs BCM5461S BCM5461S NAND Flash 1GB x 16 Adrs/Data COP/JTAG MPC8548 Management Processor P1 DDR SDRAM COP/ JTAG NOR Flash 512Mb or 64MB x 16 PQ DDR2 SDRAM I2C EEPROM (ENG use only) NOR Flash 4M x 16 A/D I2C EEPROM Console PCIe x4
Overview: Additional Information ADDITIONAL INFORMATION This section lists the ATCA-9305 hardware’s regulatory certifications and briefly discusses the terminology and notation conventions used in this manual. It also lists general technical references. Mean time between failures (MTBF) has been calculated at 439,924 hours using the Telcordia SR-332, Issue 1 (Reliability Prediction for Electronic Equipment), method 2 at 30° C.
Overview: Additional Information (continued) Type: Specification: EMC FCC Part 15, Class A– Title 47, Code of Federal Regulations, Radio Frequency Devices ICES 003, Class A – Radiated and Conducted Emissions, Canada NEBS: Telecordia GR-1089 level 3 – Emissions and Immunity (circuit pack level testing only) EN55022 – Information Technology Equipment, Radio Disturbance Characteristics, Limits and Methods of Measurement EN55024 – Information Technology Equipment, Immunity Characteristics, Limits and Meth
Overview: Additional Information Terminology and Notation Active low signals: An active low signal is indicated with an asterisk * after the signal name. Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to 32 bits, double long word refers to 64 bits. PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also known as FPGA, CPLD, EPLD, etc.). Radix 2 and 16: Hexadecimal numbers end with a subscript 16.
Overview: Additional Information Device / Interface: Flash Document: 1 (continued) 32 Mbit (x8/x16) Concurrent SuperFlash Data Sheet (Silicon Storage Technology, Inc., S71270-01-000 9/05) http://www.sst.com mDOC H3 Embedded Flash Drive (EFD) featuring Embedded TrueFFS® Flash Management Software Preliminary Data Sheet (msystems 92-DS-1205-10 Rev. 0.2 June 2006) http://www.m-systems.com/mobile StrataFlash® Embedded Memory (P33) Data Sheet (Intel®, Order Number: 314749-004 November 2007) http://www.intel.
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Section 2 Setup This chapter describes the physical layout of the boards, the setup process, and how to check for proper operation once the boards have been installed. This chapter also includes troubleshooting, service, and warranty information. ELECTROSTATIC DISCHARGE Before you begin the setup process, please remember that electrostatic discharge (ESD) can easily damage the components on the ATCA-9305 hardware.
Setup: ATCA-9305 Circuit Board Figure 2-1: ATCA-9305 Front Panel MGT ETH SPD Red/Amber = Out of Service (OOS) O O S Green = In Service (2) 2 LINK ACT SPD Amber = User Defined (3) 3 SWITCH ETH Management Console Reset Blue Hot Swap LINK ACT Ethernet Speed (top LED) Off = 10 Mbps Yellow = 100 Mbps Port 1 Green = 1000Mbps Port 2 Ethernet Link/Activity (bottom LED) Off = No Link On= Link, No Activity Blink = Link/Activity MGT CSL RST H/S ATCA-9035 Note: The electromagnetic compatibility (EMC)
Setup: ATCA-9305 Circuit Board Figure 2-2: Component Map, Top (Rev.
Setup: ATCA-9305 Circuit Board R1007 R1008 C2100 C2098 R1002 R1003 C2097 R1005 C2101 R1004 C2102 J16 R1006 R1009 Figure 2-3: Component Map, Bottom (Rev.
Setup: ATCA-9305 Circuit Board CR1 CR4 CR2 CR3 Figure 2-4: LED, Fuse and Switch Locations, Top CR1 - P2_LED_GPIO12-R CR2 - P2_LED_GPIO13-R CR3 - P2_LED_GPIO14-R CR4 - P2_LED_GPIO15-R J1 F1 F1 - .75 Amp Fuse (self resetting) F2 - .
Setup: ATCA-9305 Circuit Board Figure 2-5: LED and Switch Locations, Bottom CR57 J16 Hot Swap CR57 - BLUE_LED_CONN_K SW2 - Front Panel Reset CR54 CR55 CR56 SW2 2-6 Front Panel CR54 - Red = LED1R_CONN Amber = LED1A_CONN CR55 - LED2_CONN CR56 - LED3_CONN ATCA-9305 User’s Manual 10009109-01
Setup: ATCA-9305 Circuit Board Connectors The ATCA-9305 circuit board has various connectors and headers (see the figures beginning on page 2-3), summarized as follows: J1: This 14-pin JTAG header is used for debugging CN5860 processor 2. See Table 3-7. J3-J6: These 240-pin sockets are installed for the CN5860 processor 1 DDR2 SDRAM memory. J9: This 14-pin configuration header allows selection of boot device, and MPC8548 configuration for the configuration SROM. See Fig. 2-6.
Setup: ATCA-9305 Setup Configuration Header There are a total of seven jumper pairs on J9 (pins 11-14 are spare posts). See figure Fig. 2-2 for the jumper location on the ATCA-9305. Also reference the “Jumper Settings (0x18)” register. Figure 2-6: Configuration Header, J9 13 11 9 7 5 3 1 BT FLASH PROG STAND BOOT REDIR EN IG ROM BT SKT 14 12 10 8 6 4 2 BT SKT: A shunt on pins 1-2 selects the 512 KB socketed ROM as the boot device for the MPC8548.
Setup: ATCA-9305 Setup Power Requirements The ATCA-9305 circuit board uses —48 volts from the backplane to derive 3.3 volts for the IPMC and 12 volts for payload power. Table 2-2: Typical Power Requirements Configuration: Power: 1.
Setup: ATCA-9305 Setup Figure 2-7: Air Flow Graph Hot Swap The ATCA-9305 can be Hot Swapped, as defined in the AdvancedTCA specification (see reference in Table 1-2). This section describes how to insert and extract an ATCA-9305 module in a typical AdvancedTCA system. (These procedures assume the system is using a shelf manager.) Note: The ATCA-9305 Rear Transistion Module (RTM) has its own Hot Swap LED and switch, and it can be Hot Swapped in/out independently of the front board.
Setup: Troubleshooting Insert a board: 1 Insert the ATCA-9305 into an available slot. 2 Push in the front panel handle (tab). The blue Hot Swap LED on the front panel (see Fig. 2-1) flashes a long blink to indicate that board insertion is in progress and system management software is activating the slot. Then the blue LED turns off, indicating the insertion process is complete, and payload power is present. Remove a board: 1 Pull out the handle (tab) on the ATCA-9305 front panel one click.
Setup: Troubleshooting • whether your board has been customized for options such as a higher processor speed or additional memory • license agreements (if applicable) If you do not have internet access, please call Emerson for further assistance: (800) 327-1251 or (608) 826-8006 (US) 44-131-475-7070 (UK) Figure 2-8: Serial Number and Product ID on Top Side Serial Number Product ID Product Repair If you plan to return the board to Emerson Network Power for service, visit http://www.
Setup: Troubleshooting Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA number. Comments and Suggestions We welcome and appreciate your comments on our documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to us by filling out the following online form: http://www.emersonnetworkpowerembeddedcomputing.
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Section 3 Cavium Processor Complex The ATCA-9305 provides two Cavium processor complexes. The major devices on each complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM, RLDRAM®, an I2C EEPROM, socketed ROM, Flash, and the PCI bus interface.
Cavium Processor Complex: PCI The CN5860 and switch route packets using SPI-4.2 and control information flow using PCI. The CN5860 has two SPI-4.2 interfaces with each one supporting up to 16 ports. Two highspeed SPI-4.2 Altera (Stratix™ GX) FPGAs function as the SPI-to-XAUI bridge for each processor to switch complex. The PCI interface supports up to four ports, consequently a total of 36 ports can be supported internally by each CN5860.
Cavium Processor Complex: PCI The CN5860 processor is designed such that another PCI device can initialize its memory interface, copy code over PCI into its local memory space, and then write a boot release register. CN5860 Boot Over PCI The PCI bus is configured to run at 66 MHz in 64-bit conventional PCI mode. On power-up, the CN5860 processor’s 16 internal cores are held in reset. The MPC8548 management processor performs the following steps: 1 Initialize the CN5860 RAM.
Cavium Processor Complex: PCI Cavium Reset Each CN5860 can be reset independently of the other processor without affecting its operation. This task is performed by the MPC8548 management processor.
Cavium Processor Complex: Cavium Ethernet CAVIUM ETHERNET The Ethernet address for your board is a unique identifier on a network. The address consists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique identifier that has been assigned to Emerson Network Power, Embedded Computing by IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
Cavium Processor Complex: Cavium Monitor CAVIUM MONITOR The primary function of the monitor software is to transfer control of the hardware to the user’s application. Secondary responsibilities include: • low-level initialization of the hardware • diagnostic tests • low-level monitor commands/functions to aid in debug Start-up Display At power-up or after a reset, the Cavium monitor runs diagnostics and reports the results in the start-up display, see an example in Fig. 3-3.
Cavium Processor Complex: Cavium Monitor Figure 3-4: Power-up/Reset CN5860 Boot Sequence Flowchart Power-up or Reset Cavium Hardware Wait for PCI load of U-boot U-Boot Monitor Default Board Initialization U-Boot Monitor Execute POST U-Boot Monitor Start Autoboot Sequence (Boot Operating System) Operating System Boot Boot OS image according to configuration parameters Diagnostic Tests During Power-up and Reset The Cavium monitor diagnostic tests can be executed during power-up or invoked from the mon
Cavium Processor Complex: Cavium Monitor Table 3-4: POST Diagnostic Results–Bit Assignments Bit: Diagnostic Test: 0-1 Reserved 2 DRAM Verify address and data lines are intact 3 Cavium BIST - 0 Passed the test 4 I2C Verify all local I2C devices are connected to the I2C bus 1 Failure detected 5-31 Reserved Description: Value: Cavium Environment Variables The following table lists the standard Cavium environment variables: Table 3-5: Standard Cavium Environment Variables 3-8 ATCA-9305
Cavium Processor Complex: Memory Variable: Default Value: stdin serial Sets the standard source for console input Valid options: serial, pci stdout serial Sets the standard destination for console output Valid options: serial, pci Description: (continued) MEMORY The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency DRAM (RLDRAM) memory devices. DDR2 SDRAM The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor complex.
Cavium Processor Complex: StratixGX Interconnect Table 3-6: Cavium NVRAM Memory Map Address Offset (hex): Description: Window Size (bytes) 0x1E00-0x1FFF Monitor parameters 256 0x0000-0x1D36 User defined 79F Flash, 512 KB x 8 The 512 KB of 32-pin PLCC socketed flash starts at physical address1D46,000016 and is used for Engineering code. The StrataFlash features high-performance fast asynchronous access times, low power, and flexible security options.
Cavium Processor Complex: StratixGX Interconnect Register 3-2: Data 23:16 (0x1) Bits: R/W: Function: 7 R/W Data 23 6 R/W Data 22 5 R/W Data 21 4 R/W Data 20 3 R/W Data 19 2 R/W Data 18 1 R/W Data 17 0 R/W Data 16 Register 3-3: Data 15:8 (0x2) Bits: R/W: Function: 7 R/W Data 15 6 R/W Data 14 5 R/W Data 13 4 R/W Data 12 3 R/W Data 11 2 R/W Data 10 1 R/W Data 9 0 R/W Data 8 Register 3-4: Data 7:0 (0x3) Bits: R/W: Function: 7 R/W Data 7 6 R/W Da
Cavium Processor Complex: StratixGX Interconnect Address Registers Register 3-5: Address 9:8 (0x4) Bits: R/W: Function: 7 — Reserved 6 — 5 — 4 — 3 — 2 — 1 R/W Address 9 0 R/W Address 8 Register 3-6: Address 7:0 (0x5) Bits: R/W: Function: 7 R/W Address 7 6 R/W Address 6 5 R/W Address 5 4 R/W Address 4 3 R/W Address 3 2 R/W Address 2 1 R/W Address 1 0 R/W Address 0 Control Register The write only Control register performs two functions: • Writing a value of
Cavium Processor Complex: Bits: R/W: Function: 1 W Read 0 W Write StratixGX Interconnect Version Register This read-only register tracks the PLD versions. The version is hard coded in the PLD and changes with every released code change. Version starts at 0116. Register 3-8: Version (0x7) Bits: R/W: Function: 7 R 0x01 6 R 5 R 4 R 3 R 2 R 1 R 0 R Scratch Register All registers in this range act as the same register.
Cavium Processor Complex: Headers and Connectors Perform a read. =>write64b 1d030006 02 Display the results. =>read64l 1d030000 Write Example: To write to the FPGA bridge MAC_CMD_CFG register at 0x00C, use the following commands. Set data bits 31:24. =>write64b 1d030000 a9 Set data bits 23:16. =>write64b 1d030001 b8 Set data bits 15:8. =>write64b 1d030002 c7 Set data bits 7:0. =>write64b 1d030003 d6 Set address bits 9:8. =>write64b 1d030004 00 Set address bits 7:0.
Cavium Processor Complex: Headers and Connectors Pin: J1 (processor 2): J15 (processor 1): (continued) 5 P2_ETDO P1_ETDO 6 ground ground 7 P2_TMS P1_TMS 8 ground ground 9 P2_TCK P1_TCK 10 ground ground 11 P2_EJTAG_RST P1_EJTAG_RST 12 key (pin not installed) key (pin not installed) 13 P2_EJTAG_DINT P1_EJTAG_DINT 14 P2_COP_PWR (3.3V) P1_COP_PWR (3.
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Section 4 Management Complex The ATCA-9305 management complex is comprised of the Freescale MPC8548 processor, CPLD, SDRAM, flash, I2C EEPROM, Real-time Clock, and PCI bus interface. Board power-up, booting and monitoring the Cavium processors, PCI bus arbitration, interrupt servicing, memory persistence functionality, and other board level management tasks are implemented using the MPC8548 processor.
Management Complex: MPC8548 Processor MPC8548 PROCESSOR The MPC8548 processor has the following features: Table 4-1: MPC8548 Features Feature: Description: L1 Cache 32-kilobyte data and instruction caches with parity protection, 32byte line, eight-way set associative L2 Cache 512 kilobytes, eight-way set associative CPU Core Speed 1 GHz with a 400 MHz DDR2 bus DDR2 Memory Controller 64-bit data interface, four banks of memory supported (each up to 4 GB), full ECC support Dual I2C Controllers T
Management Complex: MPC8548 Processor Figure 4-2: MPC8548 Memory Map Hex Address Address Range FFFF,FFFF FFF0,0000 FFEF,FFFF FF80,0000 FF7F,FFFF FF70,0000 FF6F,FFFF FC88,0000 FC87,FFFF FC80,0000 FC7F,FFFF FC48,0000 FC47,FFFF FC40,0000 FC3F,FFFF FC11,0000 FC10,FFFF FC10,0000 FC0F,FFFF FC00,8000 FC00,7FFF FC00,0000 FBFF,FFFF F800,0000 F7FF,FFFF F600,0000 F5FF,FFFF F400,0000 F3FF,FFFF F080,0000 F3FF,FFFF F3C0,0000 F3BF,FFFF F380,0000 F0FF,FFFF F000,0000 EFFF,FFFF E000,0000 DFFF,FFFF 8000,0000 7FFF,FFFF 0000,
Management Complex: Hex Physical Address: Access Mode: ATCA-9305 User’s Manual Register Description: (continued) See Page: 4-7 FC80,0000 R/W Socketed flash, optional (512 KB) FC48,0000 — reserved (3.
Management Complex: MPC8548 Processor Hex Physical Address: Access Mode: Register Description: (continued) See Page: F800,0000 — reserved (64 MB) F600,0000 R/W Soldered flash bank 4 (32 MB) 4-7 F400,0000 R/W Soldered flash bank 3 (32 MB) 4-7 F080,0000 — reserved (56 MB) F3C0,0000 R/W Soldered flash bank 2 (4 MB) F380,0000 R/W Soldered flash bank 1 (4 MB) 4-7 F000,0000 R/W PCI Express I/O space (16 MB) 4-8 4-7 E000,0000 R/W PCI Express (256 MB) 4-8 8000,0000 R/W PCI (1.
Management Complex: MPC8548 Processor Reset Diagram Figure 4-3: MPC8548 Reset Diagram 33MHz L_PAYLD_EN 3_3V_PWRGD 2_5V_PWRGD 1_8V_PWRGD 1_2V_PWRGD 1_0V_PWRGD PQ_CORE_PWRGD* P1_CORE_PWRGD* P2_CORE_PWRGD* 3_3V_MP PQ_HRESET* PQ_SRESET* PQ_TRST* IPMP CPLD RESET_INDICATION* Reset to IPMC I2C1 I2C2 PWRGD_OK 3_3V_MP Front Panel Reset 3_3V_MP IPMC Reset Voltage Monitor Delay PRIV_I2C_SDA IPMC_PO_RST* NOR Flash 4M x 16 NAND_RST* NAND Flash 1GB x 16 BOOT_REDIR BOOT_SEL0 BOOT_SEL1 NAND_WARM_RST* PQ
Management Complex: Memory MEMORY The memory devices in the management complex consist of: • 1 GB DDR2 SDRAM • 512 KB socketed flash • 8 MB soldered NOR flash (two redundant banks of 4 MB each) • 1 GB soldered NAND flash • 512 Mb or 64 MB soldered NOR flash SDRAM This is a specialized, socketed, 200-pin, small outline, clocked, dual in- line, memory module (SO-CDIMM). It provides Error-correcting Code (ECC) on the SDRAM memory bus operating at 200 MHz.
Management Complex: PCI in a dual-bank architecture for concurrent read/write operation with hardware and software data protection schemes. These devices start at physical addresses F000,000016 (boot bank 1) and F040,000016 (boot bank 2). 1 GB x 16 The ATCA-9305 uses 1 GB of M-Systems DiskOnChip (mDOC H3) NAND flash starting at physical address FC00,000016 for non-volatile RAM storage and True Flash File System (TFFS).
Management Complex: I2C Interface I2C INTERFACE The I2C interface consists of the MPC8548 initialization EEPROM, user (storage) NVRAM, SO-CDIMM, and the Real-time Clock (RTC). The two Atmel two-wire serial EEPROMs on the I2C interface consist of the Serial Clock (SCL) input and the Serial Data (SDA) bidirectional lines.
Management Complex: Management Processor Header and Serial Pin: Signal: Description: (continued) 3 PQ_TDI Test Data Input is the serial input pin for instructions as well as test and programming data. 4 DEBUG_TRST* Test Reset input signal resets the test access port. 5 no connect — 6 PQ_JTAG_PWR 3.3 volt power 7 PQ_TCK_R Test Clock Input is the clock input to the boundary scan test (BST) circuitry.
Section 5 Management Processor CPLD The ATCA-9305 uses a Programmable Logic Device (PLD) to provide control logic for the local bus. The PLD implements various registers for reset, hardware, and LPC bus communication between the processors. MPC8548 PLD REGISTER SUMMARY The PLD registers start at address FC40,000016. As a rule, registers retain their values through all resets except for power-on and front panel reset. Table 5-1 lists the 8-bit PLD registers followed by the register bit descriptions.
Management Processor CPLD: MPC8548 PLD Register Address Offset (hex): Mnemonic: Register Name: 0x84 CGDO Cavium GPIO Data Out 0x88 CGDI Cavium GPIO Data In 5-13 0x8C IGCR IPMP/IPMC GPIO Control 5-14 0xD0 LPC1 Low Pin Count (LPC) Bus Control 5-14 0xD4 LPCD LPC Data 5-15 0xD8 SIRQI1 Serial IRQ Interrupt 1 [15:8] 5-15 0xDC SIRQI2 Serial IRQ Interrupt 2 [7:0] 5-15 (continued) See Page: 5-13 1. Scratch 1 (0x40) is a read/write register for storage only.
Management Processor CPLD: MPC8548 PLD Register PLD Version This read-only register tracks PLD revisions. Register 5-3: PLD Version (0x08) Bits: Function: Description: 7 0 6 0 This is hard coded in the PLD and changes with every released code change. Version starts at 0016.
Management Processor CPLD: MPC8548 PLD Register Register 5-5: Hardware Configuration 0 (0x10) Bits: Function: 7 0 Description: 6 P33P P33 (StrataFlash) is Present 5 RST_IND_CLR Clear the Reset Indication to the IPMC controller 4 CAVF1 Cavium Frequency 1 3 CAVF0 Cavium Frequency 0 2 PQCF1 MPC8548 Core Frequency 1 1 PQCF0 MPC8548 Core Frequency 0 0 PQDDRF MPC8548 DDR SDRAM Fast Jumper Settings These read-only bits may be read by software to determine the current jumper settings.
Management Processor CPLD: MPC8548 PLD Register Register 5-7: LED (0x1C) Bits: Function: Description: 7 PQRED MPC8548 red LED Lit on power-up and turned off when the monitor finishes boot up and Power-on Self Testing (POST) 6 PQGREEN MPC8548 green LED 5 SWLEDCLK Ethernet Switch LED Clock 4 SWLEDDAT Ethernet Switch LED Data 3 DEBUGLED3 LED CR22 2 DEBUGLED2 LED CR21 1 DEBUGLED1 LED CR19 0 DEBUGLED0 LED CR18 Reset Event This read-only register contains the bit corresponding to the
Management Processor CPLD: MPC8548 PLD Register Register 5-9: Reset Command 1 (0x24) Bits: Function: Description: 7 WBR Reset the Whole Board 6 PQCR Reset the MPC8548 Complex 5 CAV1CR Reset the Cavium CN5860 1 Complex 4 CAV2CR Reset the Cavium CN5860 2 Complex 3 SWICR Reset the switch BCM5680x Complex 2 I2C R Reset the I2C on the MPC8548 1 RTMR Reset the (optional) RTM 0 reserved Reset Command 2 The write-only Reset Command 2 register forces one of several types of MPC8548 reset
Management Processor CPLD: Bits: Function: 1 reserved 0 reserved MPC8548 PLD Register Description: (continued) Reset Command 4 The write-only Reset Command 4 register forces one of several types of Cavium 2 resets, as shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the PLD performs that particular reset, and the bit is automatically cleared.
Management Processor CPLD: MPC8548 PLD Register Note: The board powers down and powers back up when the Cavium processors power is back up (bits 0 or 1 are cleared).
Management Processor CPLD: MPC8548 PLD Register Register 5-16: Boot Device Redirection (0x50) Bits: Function: Description: 7 SELFRS Self Refresh Started 6 BOOTSEL1 IPMC successful boot indication (BOARD_BOOTED) 5 reserved 4 BSJ 3 NFBS Nand Flash Busy Signal 2 BDS Active boot device is socket 1 BDF1 Active boot device is flash 2 0 BDF0 Active boot device is flash 1 Boot from Socket Jumper A shunt on J9 [1:2] selects the 512KB socketed ROM as the boot device, see Fig. 2-6.
Management Processor CPLD: MPC8548 PLD Register Table 5-2: Low Frequency Timer Settings Frequency: Set Register: 0 Off Never interrupts 1 Hz 19999 (0x4E1F) These frequencies require the use of both registers 10 Hz 1999 (0x7CF) 100 Hz 199 (0xC7) 1 KHz 19 (0x13) 10 KHz 1 Comments: This equals two 50 μs time units (default) RTM GPIO State This read-only register reads the current state of the GPIO pins.
Management Processor CPLD: MPC8548 PLD Register Register 5-20: RTM Control (0x68) Bits: Function: 7 0 Description: 6 0 5 0 4 RTMP RTM is Present 3 RTMID3 RTM Identification bits 3:0 2 RTMID2 1 RTMID1 0 RTMID0 0000 = Test RTM (factory only) 1000 = 20GbE I/O RTM 1100 = 18GbE and 2x10GbE I/O RTM 1010 = Storage RTM Cavium 1 C_MUL Clock Divisor Control Use the C_MUL1 register to reduce the speed of the Cavium CN5860 processor 1 core.
Management Processor CPLD: MPC8548 PLD Register Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74) Bits: Function: Description: 7 CAVF1 Cavium 1 Frequency resistor set bit (read-only, see Register Map 5-21) 6 CAVF0 Cavium 0 Frequency resistor set bit (read-only) 5 CMULOE C_MUL Output Enable 4 P1CMUL4 3 P1CMUL3 2 P1CMUL2 These bits drive directly to the Cavium 2. The core clock speed is the number multiplied by 50 MHz. For example, the 800 MHz core is set to 16(0x10).
Management Processor CPLD: MPC8548 PLD Register Bits: Function: Description: (continued) 3 P2GPIO3OE Processor 2 GPIO3 Output Enable This is an input from the Cavium to reset the MIP3 2 P1GPIO5OE Processor 1 GPIO5 Output Enable (enabled is the default) Output enable is set for the TIC timer output to the Cavium 1 P1GPIO4OE Processor 1 GPIO4 Output Enable This is an input from the Cavium to reset the MIP2 0 P1GPIO3OE Processor 1 GPIO3 Output Enable This is an input from the Cavium to reset th
Management Processor CPLD: MPC8548 PLD Register IPMP/IPMC GPIO Control This register provides access (if required) to signals between the KSL CPLD and the IPMP, as well as to signals between the KSL CPLD and the IPMC. The lower two bits can request request the power down of a Cavium core from the sticky reset register.
Management Processor CPLD: MPC8548 PLD Register Register 5-29: LPC Data (0xD4) Bits: Function: Description: 7:0 - LPC Data Serial IRQ Interrupt 1 This is interrupt register1 for the LPC bus. Register 5-30: Serial IRQ Interrupts 1 (0xD8) Bits: Function: Description: 7:0 - Interrupts Serial IRQ Interrupt 2 This is interrupt register2 for the LPC bus.
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Section 6 Ethernet Interface The ATCA-9305 supports multiple Ethernet interfaces. This chapter describes the Broadcom BCM56802 switch, PHYS BCM5482 and BCM5461S, Ethernet address, LEDs and connectors. BROADCOM BCM56802 SWITCH The BCM56802 is a 16-port, 10-GbE multi-layer switch based on the StrataXGS® architecture. The switch operates at 66 MHz with a 32-bit PCI bus for processor communication. SERDES functionality includes 10-Gbps XAUI and 1-Gbps SGMII PHY interfaces.
Ethernet Interface: Ethernet Switching Figure 6-1: Ethernet Switching Interface Diagram RJ45 RJ45 BCM5461S BCM5461S MPC8548 Management Processor BCM5461S 3 SGMII Stratix II GX #1 6 XAUI Stratix II GX #2 5 XAUI XAUI 13 Stratix II GX #3 XAUI 14 Stratix II GX #4 BCM56802 XAUI 10 Gb Switch Ports SGMII 2 SGMII 1 XAUI 8 7 XAUI 11-12 15 -18 10G Fabric To Optional RTM BCM5482 Base J23 J30 SPI-0 Cavium Octeon CN5860 SPI-1 Processor 2 10G - 4 PORTS SPI-0 Cavium Octeon CN5860 Processor 1
Ethernet Interface: MPC8548 Management Processor Ethernet Port: Interface: Connection: (continued) 3 SGMII 1 GB Switch PHY to front panel RJ45 connector 4 SGMII 1 GB Management processor PHYs to front panel RJ45 connector 5 XAUI 10 GB Stratix II GX bridge 2 6 XAUI 10 GB Stratix II GX bridge 1 7 XAUI 10 GB Back plane Fabric 8 XAUI 10 GB Back plane Fabric 9 — not used 10 — not used 11 XAUI 10 GB BCM56802 to J30 to optional RTM 13 XAUI 10 GB Stratix II GX bridge 3 14 XAUI 10
Ethernet Interface: MPC8548 Management Processor Ethernet 00 80 F9 xx yy zz 00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the port (one byte), 0x97(port 1) or 0x98 (port 2), followed by the serial number (two byte hexadecimal). The ATCA-9305 has been assigned the Ethernet address range 00:80:F9:97:00:00 to 00:80:F9:98:FF:FF. The format is shown in Table 6-3.
Ethernet Interface: MPC8548 Management Processor Ethernet Pin: P1 Signal: P3 Signal: (continued) 12 TSEC1_LINKSPD2 (yellow LED 2) FP1_LINKSPD2 (yellow LED 2) 13 TSEC1_CHSGND FP1_CHSGND 14 TSEC1_CHSGND FP1_CHSGND 10009109-01 ATCA-9305 User’s Manual 6-5
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Section 7 System Management The ATCA-9305 provides an intelligent hardware management system, as defined in the AdvancedTCA Base Specification (PICMG® 3.0). This system implements an Intelligent Platform Management Controller (IPMC) based on the BMR-H8S-AMCc® reference design from Pigeon Point Systems. It also has an inter-integrated circuit (I2C) controller to support an Intelligent Platform Management Bus (IPMB) that routes to the ATCA backplane.
System Management: IPMI Messaging Figure 7-1: IPMC Connections Block Diagram UART & LPC IPMI MESSAGING All IPMI messages contain a Network Function Code field, which defines the category for a particular command. Each category has two codes assigned to it–one for requests and one for responses. The code for a request has the least significant bit of the field set to zero, while the code for a response has the least significant bit of the field set to one.
System Management: IPMI Messaging Table 7-1: Network Function Codes Hex Code Value(s): Name: Type: Name: 00, 01 Chassis chassis device requests/responses 00 = command/request, 01 = response: common chassis control and status functions 02, 03 Bridge bridge requests/responses 02 = request, 03 = response: message contains data for bridging to the next bus. Typically, the data is another message, which also may be a bridging message. This function is only present on bridge nodes.
System Management: IPMI Messaging IPMI Completion Codes All IPMI response messages contain a hexadecimal Completion Code field that indicates the status of the operation.
System Management: Code: IPMB Protocol (continued) Description: Device-Specific (OEM) Codes 01-7E 01-7E Device specific (OEM) completion codes–command-specific codes (also specific for a particular device and version). Interpretation of these codes requires prior knowledge of the device command set.
System Management: SIPL Protocol • The seventh byte and beyond contain parameters for specific commands (if required). • The final byte is the two’s-complement checksum of all of the message data after the first checksum. An IPMI response message (see Table 7-4) is similar to an IPMI request message. The main difference is that the seventh byte contains the Completion Code, and the eighth byte and beyond hold data received from the controller (rather than data to send to the controller).
System Management: Message Bridging Figure 7-2: Extension Command Request Example [B8 [B8 00 00 01 01 0A 0A 40 40 00 00 12] 12] Data Data Pigeon Point IANA IANA Command Code Command rqSeq (00 (001616)) // Bridge Bridge (0022)) rqSeq NetFnCode Code (2E (2E1616)) // LUN LUN (00 (0022)) NetFn Figure 7-3: Extension Command Response Example [BC 00 01 00 0A 40 00 34] Data Pigeon Point IANA Completion Code Command Code rqSeq (0016) / Bridge (002) NetFn Code (2F16) / LUN (002) MESSAGE BRIDGING The Message B
System Management: Message Bridging The following example illustrates how the Send/Get Message and Get Address Info commands can be used by the payload software to get the physical location of the board in the shelf: 1 The payload software sends the Get Address Info command to the BMR-H8S-AMCc, requesting address information for FRU device 0. Using the SIPL protocol: [B0 xx 01 00] 2 The BMR-H8S-AMCc returns its IPMB address in the Get Address Info reply.
System Management: Standard Commands dling, if it is necessary. If the Receive Message Queue is full, the ATCA-9305 IPMC rejects all requests coming to LUN 10 with the C0h (Node Busy) completion code and discards all responses coming to this LUN. STANDARD COMMANDS The Intelligent Peripheral Management Controller (IPMC) supports standard IPMI commands to query board information and to control the behavior of the board.
System Management: Command: Standard Commands (continued) Set Sensor Thresholds 7-10 ATCA-9305 User’s Manual netFn: LUN: Cmd: Sensor/Event 04, 05 26 Get Sensor Thresholds Sensor/Event 04, 05 27 Set Sensor Event Enable Sensor/Event 04, 05 28 Get Sensor Event Enable Sensor/Event 04, 05 29 Rearm Sensor Events Sensor/Event 04, 05 2A 2B Get Sensor Event Status Sensor/Event 04, 05 Get Sensor Reading Sensor/Event 04, 05 2D Set Sensor Type Sensor/Event 04, 05 2E Get Sensor Ty
System Management: Command: OEM Boot Options (continued) netFn: LUN: Cmd: Get Power Level PICMG 2C, 2D 12 Bused Resource (Release, Query, Force, Bus Free) PICMG 2C, 2D 17 The IPMC implements many standard IPMI commands. For example, software can use the watchdog timer commands to monitor the system’s health. Normally, the software resets the watchdog timer periodically to prevent it from expiring.
System Management: IPMC Watchdog Timer Commands IPMC WATCHDOG TIMER COMMANDS The IPMC implements a standardized ‘Watchdog Timer’ that can be used for a number of system time-out functions by System Management Software (SMS) or by the monitor. Setting a time-out value of zero allows the selected time-out action to occur immediately. This provides a standardized means for devices on the IPMB to perform emergency recovery actions.
System Management: IPMC Watchdog Timer Commands Monitor POST Time-out: In this mode, the time-out occurred while the watchdog timer was being used by the monitor for some purpose other than FRB-2 or OS Load Watchdog. OS Load Time-out: The last reset or power cycle was caused by the timer being used to ‘watchdog’ the interval from ‘boot’ to OS up and running. This mode requires system management software, or OS support. The monitor should clear this flag if it starts this timer during POST.
System Management: IPMC Watchdog Timer Commands Reset Watchdog Timer Command The Reset Watchdog Timer command is used for starting and restarting the Watchdog Timer from the initial countdown value that was specified in the Set Watchdog Timer command. If a pretime-out interrupt has been configured, the Reset Watchdog Timer command will not restart the timer once the pretime-out interval has been reached. The only way to stop the timer once it has reached this point is via the Set Watchdog Timer command.
System Management: IPMC Watchdog Timer Commands Table 7-9: Set Watchdog Timer Command Type: Byte: Data Field: Request Data 1 Timer Use [7] 1b=don’t log [6] 1b=the don’t stop timer on Set Watchdog Timer command (new for IPMI v1.5) new parameters take effect immediately. If timer is already running, countdown value will get set to given value and countdown will continue from that point. If timer is already stopped, it will remain stopped. If the pretime-out interrupt bit is set, it will get cleared.
System Management: IPMC Watchdog Timer Commands Type: Byte: Data Field: (continued) Request Data (continued) 4 Timer Use Expiration flags clear (0b=leave alone, 1b=clear timer use expiration bit) [7] reserved [6] reserved [5] OEM [4] SMS/OS [3] OS Load [2] Monitor/POST [1] Monitor FRB-2 [0] reserved 5 Initial countdown value, lsbyte (100 ms/count) 6 Initial countdown value, msbyte 1 Completion Code Response Data 1. Potential race conditions exist with implementation of this option.
System Management: IPMC Watchdog Timer Commands Type: Byte: Data Field: (continued) Response Data 2 Timer Use [7] 1b=don’t log [6] 1b=timer is started (running) 0b=timer is stopped [5:3] reserved [2:0] timer use (logged on expiration if “don’t log” bit = 0) 000b=reserved 001b=Monitor FRB-2 010b=Monitor/POST 011b=OS Load 100b=SMS/OS 101b=OEM 110b, 111b=reserved 3 Timer Actions [7] reserved [6:4] pretime-out interrupt 000b=none 001b=SMI 010b=NMI/Diagnostic Interrupt 011b=Messaging Interrupt (this wou
System Management: FRU LEDs Type: Byte: Data Field: (continued) Response Data 8 Present countdown value, lsbyte. The initial countdown value and present countdown values should match immediately after the countdown is initialized via a Set Watchdog Timer command and after a Reset Watchdog Timer has been executed. Note that internal delays in the IPMC may require software to delay up to 100 ms before seeing the countdown value change and be reflected in the Get Watchdog Timer command.
System Management: FRU LEDs Get FRU LED Properties Command This command allows software to determine which LEDs are under IPMC control. Table 7-12: Get FRU LED Properties Command Type: Byte: Data Field: Request Data 1 PICMG Identifier—indicates that this is a PICMG defined group extension command. Use value 00h. 2 FRU Device ID Response Data 1 Completion Code 2 PICMG Identifier—indicates that this is a PICMG defined group extension command. Use value 00h.
System Management: 7-20 ATCA-9305 User’s Manual FRU LEDs Type: Byte: Data Field: (continued) Response Data 1 Completion Code CCh If the LED ID contained in the Request data is not present on the FRU 2 PICMG Identifier—indicates that this is a PICMG defined group extension command. Use value 00h. 3 LED Color Capabilities—when a bit is set, the LED supports the color.
System Management: FRU LEDs Set FRU LED State Command The Set FRU LED State command allows the state of the FRU LEDs to be controlled by the management system. Table 7-14: Set FRU LED State Command Type: Byte: Data Field: Request Data 1 PICMG Identifier—indicates that this is a PICMG defined group extension command. Use value 00h.
System Management: FRU LEDs Type: Byte: Data Field: (continued) Request Data 6 Color When Illuminated—sets the override color when LED Function is 01h-FAh and FFh. This byte sets the Local Control color when LED Function is FCh. This byte may be ignored during Lamp Test or may be used to control the color during the lamp test when LED Function is FBh.
System Management: FRU LEDs Type: Byte: Data Field: (continued) Response Data 3 LED States Bits [7:3] reserved, set to 0 Bit [2] 1b if Lamp Test has been enabled Bit [1] 1b if override state has been enabled Bit [2] 1b if IPMC has a Local control state 4 Local Control LED Function 00h LED is off (default if Local Control not supported) 01h-FAh LED is blinking Off duration specified by this byte, on duration specified by byte 5 (in tens of milliseconds) FBh-FEh reserved FFh LED is on 5 On Duration
System Management: Type: Response Data Vendor Commands Byte: Data Field: (continued) 9 Override State Color Bits [7:4] reserved, set to 0 Bits [3:0] 0h reserved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h-Fh reserved 10 Lamp Test Duration—is optional if Lamp Test is not in effect (hundreds of milliseconds). VENDOR COMMANDS The IPMC supports additional IPMI commands that are specific to Pigeon Point and/or Emerson.
System Management: Command: Vendor Commands (continued) Set Local FRU LED State netFn: LUN: Cmd: OEM 2E, 2F 18 Get Local FRU LED State OEM 2E, 2F 19 Update Discrete Sensor OEM 2E, 2F 1A 1B Update Threshold Sensor OEM 2E, 2F Reserved for Message Listeners OEM 30, 31 10 Add Message Listener OEM 30, 31 11 Remove Message Listener OEM 30, 31 12 Get Message Listener List OEM 30, 31 13 Update Firmware Progress Sensor OEM 30, 31 F0 Get Status The IPMC firmware notifies the
System Management: 7-26 ATCA-9305 User’s Manual Vendor Commands (continued) Type: Byte: Data Field: Response Data 5 Bit [7] Graceful Reboot Request If set to 1, indicates that the payload is requested to initiate the graceful reboot sequence Bit [6] Diagnostic Interrupt Request If set to 1, indicates that a payload diagnostic interrupt request has arrived Bit [5] Shutdown Alert If set to 1, indicates that the payload is going to be shutdown Bit [4] Reset Alert If set to 1, indicates that the paylo
System Management: Vendor Commands (continued) Type: Byte: Data Field: Response Data 7 Bits [4:7] Clock Bus 2 Events These bits indicate pending Clock Bus 2 requests arrived from the carrier controller: 0 Clock Bus 2 Query 1 Clock Bus 2 Release 2 Clock Bus 2 Force 3 Clock Bus 2 Free Bits [0:3] Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the carrier controller: 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free 8 Bits [4:7] reserved
System Management: Vendor Commands (continued) Type: Byte: Data Field: Response Data 5 Bit [7] Echo On If this bit is set, the IPMC enables echo for the given serial interface Bits [6:4] reserved Bits [3:0] Baud Rate ID The baud rate ID defines the interface baud rate as follows: 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps (unsupported) 4 115200 bps (unsupported) Set Serial Interface Properties The Set Serial Interface Properties command is used to set the properties of a particular serial inter
System Management: Vendor Commands Get Debug Level The Get Debug Level command gets the current debug level of the IPMC firmware.
System Management: Vendor Commands (continued) Type: Byte: Data Field: Request Data 4 Bits [7:5] reserved Bit [4] IPMB Dump Enable If set to 1, the IPMC provides a trace of IPMB messages that are arriving to/going from the IPMC via IPMB-0 or IPMB-L Bit [3] Payload Logging Enable If set to 1, the IPMC provides a trace of SIPL activity on the Payload interface onto the Serial Debug interface Bit [2] Alert Logging Enable If set to 1, the IPMC outputs important alert messages onto the Serial Debug inter
System Management: Type: Vendor Commands (continued) Byte: Data Field: 4 Hardware Address If set to 00, the ability to override the hardware address is disabled NOTE: A hardware address change only takes effect after an IPMC reset. See “Reset IPMC” on page 7-33. Response Data 1 Completion Code 2:4 PPS IANA Private Enterprise ID, MS Byte first 0x00400A = 16394 (Pigeon Point Systems) Get Handle Switch The Get Handle Switch command reads the state of the Hot Swap handle of the IPMC.
System Management: Vendor Commands Get Payload Communication Time-Out The Get Payload Communication Time-Out command reads the payload communication time-out value.
System Management: Vendor Commands Disable Payload Control The Disable Payload Control command disables payload control from the Serial Debug interface.
System Management: Vendor Commands Bused Resource To send a Bused Resource command to the carrier controller, the payload uses the Bused Resource command of the SIPL.
System Management: Vendor Commands Table 7-33: Bused Resource Status Command Type: Byte: Data Field: Request Data 1:3 PPS IANA Private Enterprise ID, MS Byte first 0x00400A = 16394 (Pigeon Point Systems) 4 Command Types for Carrier Controller to Board 0 Query if board has control of the bus (0=In control, 1= No control) 1 Release request a board to release control of the bus (0=Ack, 1=Refused, 2=No control) 2 Force board to release control of bus immediately (0=Ack, 1=No control) 3 Bus Free inform
System Management: Vendor Commands The IPMC does not reset the payload on receiving the Graceful Reset command or time-out. If the IPMC participation is necessary, the payload must request the IPMC to perform a payload reset. The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence.
System Management: Vendor Commands To avoid deadlocks that may occur if the payload software does not respond, the IPMC provides a special time-out for the payload shutdown sequence. If the payload does not send the Graceful Reset command within a definite period of time, the IPMC assumes that the payload shutdown sequence is finished, and sends a Module Quiesced Hot Swap event to the ATCA-9305 controller.
System Management: Vendor Commands Set Local FRU LED State The Set Local FRU LED State command is used to change the local state of a FRU LED.
System Management: Vendor Commands Get Local FRU LED State The Get Local FRU LED State command is used to read the local state of a FRU LED.
System Management: Vendor Commands Update Discrete Sensor The Update Discrete Sensor command is used to change the state of a discrete sensor controlled by the payload.
System Management: Boot Device Redirection (BDR) (continued) Type: Byte: Data Field: Request Data 5 Update flags 0 0=sensor initialization is complete 1=sensor is in the initial update state 1:2 reserved, set to 0 3 0=globally disable events from the sensor 1=leave the global event enable bit intact 4 0=globally enable events from the sensor 1=leave the global event enable bit intact 5 0=globally disable sensor scanning 1=leave the global scanning enable bit intact 6 0=globally enable sensor scannin
System Management: Boot Device Redirection (BDR) Figure 7-4: Boot Device Diagram 512 KB socketed flash installed on ATCA-9305? No Yes Yes Initial boot attempt is from ATCA-9305 soldered flash bank 1 No Jumper J11 [1:2] shunt installed? Flash bank 2 fail? Flash bank 1 fail? No No Yes Yes Boot device is 512 KB socketed flash BDR Watchdog disabled Secondary boot attempt is from ATCA9305 soldered flash bank 2 Boot from flash bank 2 Boot from flash bank 1 Note: The Boot Device Redirection mechani
System Management: Message Listeners Management Controller: The controller provides a signals to reset the payload. Payload: This provides signals to the controller indicating when the payload has reset for any reason, that the payload is powered, and that the payload has finished its monitor booting sequence. By default, a powered payload enables the watchdog and disables when the payload is not powered.
System Management: Message Listeners Add Message Listener The Add Message Listener command adds a specified Network Function and Command to the Message Listener List. The command returns completion code (0x00) and IANA. If this command does not complete successfully (e.g., due to a full list), it returns 0xCD and IANA. Table 7-42: Add Message Listener Command Type: Byte: Data Field: Request Data 1:3 Emerson Network Power, Embedded Computing Inc.
System Management: System Firmware Progress Sensor Get Message Listener List The Get Message Listener List command returns the entire list of subscribed Message Listeners. The command returns completion code (0x00) and IANA. Table 7-44: Get Message Listener List Command Type: Byte: Data Field: Request Data 1:3 Emerson Network Power, Embedded Computing Inc. IANA Private Enterprise ID 0x0065CD = 26061 (Emerson Network Power, Embedded Computing Inc.
System Management: Entities and Entity Associations The command returns 0xC0 when the IPMC is busy and will retry until the command is successful. If this command returns 0xCC, the sensor ID is invalid. There is only one sensor on the board, so the sensor ID should always be “0”. When updated, the shelf manager is notified. Table 7-45: Update System Firmware Progress Sensor Command Type: Byte: Data Field: Request Data 1:3 Emerson Network Power, Embedded Computing Inc.
System Management: Entities and Entity Associations Figure 7-6: IPMB Entity Structure FRU 0 r(82, 0, A0, 0) Inflow Temp Outflow Temp Hot Swap IPMB Physical BMC Watchdog F/W Progress SDRAM POST IIC Bus POST Flash POST EthSwitch POST Version change Async Pld Rst Payload Power r(82, 0, 03, 0) - Cavium 1 Cavium 1 Temp Cav1 SDRAM POST Cav1 IIC POST Cav1 Boot r(82, 0, 03, 1) - Cavium 2 Cavium 2 Temp Cav2 SDRAM POST Cav2 IIC POST Cav2 Boot r(82, 0, 14, 0) - Power Module -48V -48V Curr -48V Src A -48V Src B +3.
System Management: Sensors and Sensor Data Records SENSORS AND SENSOR DATA RECORDS The ATCA-9305 implements a number of sensors as described in the following tables. All values are hexadecimal.
System Management: Sensors and Sensor Data Records Name: Sensor Type: Event Reading Type: Enity ID: Entity Instance: Event Gen: Cav1 IIC POST Processor = 07 Predictive-failure Discrete = 04 0x03 0x60 Yes Cav1 Boot Processor = 07 Predictive-failure Discrete = 04 0x03 0x60 Yes Cav2 SDRAM POST Memory = 0C Sensor specific discrete = 6F 0x03 0x61 Yes Cav2 IIC POST Processor = 07 Predictive-failure Discrete = 04 0x03 0x61 Yes Cav2 Boot Processor = 07 Predictive-failure Discrete =
System Management: FRU Inventory Byte:1 Field: Description: 9 Event Dir/Event Type Upper bit indicates direction (0 = Assert, 1= Deassert); Lower 7 bits indicate type of threshold crossing or state transition 10 Event Data 0 Data for sensor and event type 11 Event Data 1 (Optional) Data for sensor and event type 12 Event Data 2 (Optional) Data for sensor and event type 13 Chk2 Checksum #2 (continued) 1. Each byte has eight bits.
System Management: E-Keying Item: Description: (continued) Board Serial Number Variable, formatted as “730-XXXX” Board Part Number Variable, formatted as “10XXXXXX-YY-Z” FRU File ID Variable, for example: “fru-info.
System Management: HPM.1 Firmware Upgrade Base Point-to-Point Connectivity The ATCA-9305 supports two 10/100/1000BASE-T ports on Base Interface Channels 0 and 1, and two 10 GbE XAUI ports to the Fabric channels. Depending on the board configuration, either two or six 10 GbE XAUI ports route to the optional rear transition module (RTM). Table 7-50 shows the Point-to-point Connectivity Record Link Descriptors for the ATCA9305.
System Management: IPMC Headers HPM.1 Reliable Field Upgrade Procedure The HPM.1 upgrade procedure is managed by a utility called the Upgrade Agent. The Impitool utility is used as an Upgrade Agent for upgrading the ATCA-9305 IPMC firmware. The Upgrade Agent communicates with the IPMC firmware via the payload serial interface or IPMC-0, and uses the AdvancedTCA commands that are described in the HPM.1 specification for upgrading the firmware.
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Section 8 Back Panel Connectors There are multiple connectors on the ATCA-9305, reference Fig. 2-2 for their location. The back panel connectors, Zones 1 through 3, are described in this chapter. Whether individual back panel connectors are populated on the ATCA-9305 depends on the specific product configuration. ZONE 1 Connector P10 provides the AdvancedTCA Zone 1 power (dual redundant -48 VDC) and system management connections.
Back Panel Connectors: Zone 2 Pin: Signal: Insertion Sequence: 18 no connect third 19 no connect third 20 no connect third 21 no connect third 22 no connect third 23 no connect third 24 no connect third 25 P10_CHS_GND first 26 Logic ground first 27 ENABLE_B fourth 28 -48RTNA first 29 -48RTNB first 30 no connect first 31 no connect first 32 ENABLE_ A fourth 33 -48A second 34 -48B third ZONE 2 Zone 2 (ZD) defines backplane connector J23, which supports t
Back Panel Connectors: Zone 3 Table 8-2: Zone 2 Connector, J23 Pin Assignments Row: Interface: 1 Fabric Channel 2 2 3 Fabric Channel 1 4 AB: CD: EF: GH: TX2+ TX2- RX2+ RX2- TX3+ TX3- RX3+ TX0+ TX0- RX0+ RX0- TX1+ TX1- RX1+ RX3RX1- TX2+ TX2- RX2+ RX2- TX3+ TX3- RX3+ RX3- TX0+ TX0- RX0+ RX0- TX1+ TX1- RX1+ RX1- 5 Base Channel 1 TRD0+ TRD0- TRD1+ TRD1- TRD2+ TRD2- TRD3+ TRD3- 6 Base Channel 2 TRD0+ TRD0- TRD1+ TRD1- TRD2+ TRD2- TRD3+ TRD3- 7-10
Back Panel Connectors: Zone 3 Table 8-4: Zone 3 Connector, J31 Pin Assignments A: B: C: D: E: F: G: H: 1 RTM_10G3 _ RX0_P RTM_10G3 _ RX0_N RTM_10G5 _ RX0_P RTM_10G5 _ RX0_N RTM_10G4 _ RX0_P RTM_10G4 _ RX0_N RTM_10G6 _ RX0_P RTM_10G6 _ RX0_N 2 RTM_10G3 _ RX1_P RTM_10G3 _ RX1_N RTM_10G5 _ RX1_P RTM_10G5 _ RX1_N RTM_10G4 _ RX1_P RTM_10G4 _ RX1_N RTM_10G6 _ RX1_P RTM_10G6 _ RX1_N 3 RTM_10G3 _ RX2_P RTM_10G3 _ RX2_N RTM_10G5 _ RX2_P RTM_10G5 _ RX2_N RTM_10G4 _ RX2_P RTM_10G4 _
Section 9 Management Processor Monitor The ATCA-9305 monitor is based on the Embedded PowerPC Linux Universal Boot (U-Boot) Project program, available under the GNU General Public License (GPL). For instructions on how to obtain the source code for this GPL program, please visit http://www.emersonembeddedcomputing.com/post-sales_support/218, send an e-mail to support@artesyncp.com, or call Emerson at (800) 327-1251.
Management Processor Monitor: Command-Line Features Figure 9-1: Example MPC8548 Monitor Start-up Display U-Boot 1.1.4 (Jan Hardware initialization Monitor command prompt 8 2007 - 16:07:48)1.0 CPU: 8548_E, Version: 2.0, (0x80390020) Core: E500, Version: 2.0, (0x80210020) Clock Configuration: CPU: 999 MHz, CCB: 399 MHz, DDR: 199 MHz, LBC: 49 MHz Board: ATCA-9305 ATCA Blade Emerson Network Power, Embedded Computing Inc. cPLD Ver: 2 I2C: ready Clearing ALL of memory ................
Management Processor Monitor: Basic Operation LED Code: Power-up Status: LED Value: CHECKBOARD get processor and bus speeds done 0x03 SDRAM_INIT RAM / ECC init done 0x04 AFTER_RELOC U-Boot relocated to RAM done 0x05 MISC_R final init including Ethernet done 0x06 GONE_TO_PROMPT — 0x00 BASIC OPERATION The monitor performs various configuration tasks upon power-up or reset. This section describes the monitor operation during initialization of the ATCA-9305 board. The flowchart (see Fig.
Management Processor Monitor: Basic Operation Figure 9-2: Power-up/Reset Sequence Flowchart Power-up or Reset U-Boot Monitor Default Board Initialization U-Boot Monitor PCI Monarch, Enumerate U-Boot Monitor Configure Ethernet Switch Initialize IPMC Execute POST Boot Caviums Boot Cavium processor according to configuration parameters U-Boot Monitor Start Autoboot Sequence (Boot Operating System) Operating System Boot Boot OS image according to configuration parameters POST Diagnostic Results The ATC
Management Processor Monitor: Monitor Recovery and Table 9-2: POST Diagnostic Results–Bit Assignments Bit: Diagnostic Test: Description: 0 SDRAM Verify address and data lines are intact 1 Flash Verify size and initialization of soldered flash 2 I2C Verify all local I2C devices are connected to the I2C bus Verify PCI communication with switch 3 Ethernet Switch 4 Reserved 5 PCIe Time-out PCIe enumeration skipped by user 6 DOC Embedded Flash Drive (EFD) Verify presence and ability to ac
Management Processor Monitor: Monitor Recovery and Recovering the Monitor 1 Make sure that a monitor ROM device is installed in the PLCC socket on the ATCA-9305. 2 Verify there is a shunt on J9, across pins 1 and 2. 3 Issue the following command, where serial_number is the board’s serial number, at the monitor prompt: ATCA-9305 (1.0) => moninit serial_number moninit will also reset environment variables to the default state.
Management Processor Monitor: Monitor Command ATCA-9305 (1.0) => setenv ethport eTSEC1 Optionally, save your settings: ATCA-9305 (1.0) => saveenv TFTP the new monitor (binary) image to memory location 0x100000: ATCA-9305 (1.0) => tftpboot 100000 path_to_file_on_tftp_server Update the monitor: ATCA-9305 (1.0) => moninit serial_number 100000 If moninit( ) fails, burn the new monitor to a ROM and follow the recovery steps in the “Recovering the Monitor” section.
Management Processor Monitor: Boot Commands Command Help Access all available monitor commands by pressing the ? key or entering help. Access the monitor online help for individual commands by typing help . The full command name must be entered to access the online help. Typographic Conventions In the following command descriptions, text in Courier shows the command format. Square brackets [ ] enclose optional arguments, and angled brackets < > enclose required arguments.
Management Processor Monitor: Boot Commands To use network download commands (e.g., bootp, bootvx, rarpboot, tftpboot), the environment variables listed in Table 9-4 must be configured. To set a static IP, these environment variables must be specified through the command line interface.
Management Processor Monitor: Definition: Boot Commands dhcp [loadaddress] [bootfilename] To use the dhcp command, your DHCP server must be configured with the variables designated in Table 9-5. Table 9-5: DHCP Ethernet Configuration Environment Variable: Description: ipaddr Local IP address for the board, configured by DHCP e.g., 192.168.1.1 serverip TFTP/NFS server address value must be configured after the DHCP IP address is acquired2 e.g., 192.168.1.
Management Processor Monitor: File Load Commands FILE LOAD COMMANDS The file load commands load files over the serial port. loadb The loadb command loads a binary file over the serial port. The command takes two optional parameters: offset: The address offset parameter allows the file to be stored in a location different than what is indicated within the binary file by adding the value off to the file’s absolute address.
Management Processor Monitor: Memory Commands cmp The cmp command compares count objects between addr1 and addr2. Any differences are displayed on the console display. Definition: cmp [.b, .w, .l] addr1 addr2 count cp The cp command copies count objects located at the source address to the target address. Note: If the target address is located in the range of the flash device, it will program the flash with count objects from the source address.
Management Processor Monitor: Memory Commands 00080030: ffff ffff ffff ffff ffff ffff ffff ffff ................ mm The mm command modifies memory one object at a time. Once started, the command line prompts for a new value at the starting address. After a new value is entered, pressing ENTER auto-increments the address to the next location. Pressing ENTER without entering a new value leaves the original value for that address unchanged.
Management Processor Monitor: 00080020: 00080030: 00080040: 00080050: 00080060: 00080070: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff Flash Commands ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ................ ................ ................ ................ ................ ................
Management Processor Monitor: EEPROM/I2C Commands Definition: Print information for all flash memory banks. flinfo Print information for the flash memory in bank # N. flinfo N protect The protect command enables or disables the flash sector protection for the specified flash sector. Protection is implemented using software only. The protection mechanism inside the physical flash part is not being used. Definition: Protect all of the flash sectors in the address range from start to end.
Management Processor Monitor: EEPROM/I2C Commands reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 (right-shifted 7-bit address) and places it in memory at address 0x100000. Definition: Read/write cnt bytes from devaddr EEPROM at offset off. eeprom read devaddr addr off cnt eeprom write devaddr addr off cnt icrc32 The icrc32 computes a CRC32 checksum. Definition: icrc32 chip address[.0, .1, .2] count iloop The iloop command reads in an infinite loop on the specified address range.
Management Processor Monitor: IPMC Commands iprobe The iprobe command probes to discover valid primary I2C bus chip addresses. Definition: iprobe IPMC COMMANDS IPMI Baseboard Management Controller (BMC) watchdog is supported and serviced throughout the monitor boot process. The BMC watchdog is disabled if the monitor goes to the monitor prompt. bootdev The bootdev command gets or sets the initial boot bank. Get prints out the flash bank set as initial boot device.
Management Processor Monitor: IPMC Commands fru set internal The fru create command loads a default fru image to a blank fru device. fru create default fru create fruinit The fruinit command initializes the following fru data fields: part number, build date, and serial number in the board and product sections.
Management Processor Monitor: Environment Parameter ENVIRONMENT PARAMETER COMMANDS The monitor uses on-board, non-volatile memory for the storage of environment parameters. Environment parameters are stored as ASCII strings with the following format. = Some environment variables are used for board configuration and identification by the monitor. The environment parameter commands deal with the reading and writing of these parameters.
Management Processor Monitor: Test Commands setenv name value Removes the environment variable name from the environment. setenv name TEST COMMANDS The commands described in this section perform diagnostic and memory tests. diags The diags command runs the Power-on Self-test (POST). Definition: diags mtest The mtest command performs a simple SDRAM read/write test. Definition: mtest [start [end [pattern]]] um The um command is a destructive memory test.
Management Processor Monitor: Other Commands bdinfo The bdinfo command displays the Board Information Structure. Definition: bdinfo coninfo The coninfo command displays the information for all available console devices. Definition: coninfo crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address. Definition: crc32 address count date The date command will set or get the date and time, and reset the RTC device. Definition: Set the date and time. date [MMDDhhmm[[CC]YY][.
Management Processor Monitor: Other Commands help The help (or ?) command displays the online help. Without arguments, all commands are displayed with a short usage message for each. To obtain more detailed information for a specific command, enter the desired command as an argument. Definition: help [command …] iminfo The iminfo command displays the header information for an application image that is loaded into memory at address addr.
Management Processor Monitor: Other Commands moninit[.1, .2] Initialize environment variables and serial number in NVRAM but do not update the monitor in NOR flash. moninit[.1, .2] noburn Initialize environment variables and serial number in NVRAM and copy the monitor from into NOR flash. moninit[.1, .2] pci The pci command enumerates the PCI bus. It displays enumeration information about each detected device.
Management Processor Monitor: Other Commands phy eTSEC2 w 0x1a 0 ping The ping command sends a ping over Ethernet to check if the host can be reached. The port used is defined by the ethport environment variable. If all is selected for ethport, the ping process cycles through each port until a connection is found or all ports have failed. Definition: ping host reset The reset command performs a hard reset of the CPU by writing to the reset register on the board.
Management Processor Monitor: Definition: Other Commands showpci sleep The sleep command executes a delay of N seconds. Definition: Delay execution for N seconds (N is a decimal value). sleep N switch_reg The switch_reg command reads or writes to the Ethernet core switch registers. The values changed via this command are not persistent and clear after a hard or soft reset. Option values are as follows: switch (core or fp), port (0 - 25), block (1-7), and sub-block (0-15).
Management Processor Monitor: MPC8548 Environment MPC8548 ENVIRONMENT VARIABLES Press the ‘s’ key on the keyboard during reset to force the default monitor environment variables to be loaded during hardware initialization but before diagnostic testing.
Management Processor Monitor: Variable: Default Value: MPC8548 Environment Description: (continued) eth1addr 00:80:F9: 98:00:0000:80:F9: 98:FF:FF ATCA-9305 board Ethernet address for TSEC_2 port, the last digits are the board serial number in hex. fru_id undefined Corresponds to ATCA-9305 processing resources Valid options: Not defined in default configuration— reported at bootup from the IPMC gatewayip 0.0.0.
Management Processor Monitor: Troubleshooting Table 9-7: Optional Environment Variables Variable1: Description: app_lock_base Assigns where to start block lock protection at the base of NOR (soldered) flash. If assigned region does not fall within the NOR flash area, no user/application locking will occur, except for the monitor block-locking protection. app_lock_size Size of user NOR (soldered) flash protection area.
Management Processor Monitor: Download Formats Binary The binary formats (and associated commands) include: • Executable binary files (go) • VxWorks and QNX® ELF (bootm, bootvx, or bootelf) • Compressed (gzipped) VxWorks and QNX ELF (bootm) • Linux kernel images (bootm) • Compressed (gzipped) Linux kernel images (bootm) Motorola S-Record S-Record download uses the standard Motorola S-Record format. This includes load address, section size, and checksum all embedded in an ASCII file.
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Section 10 Acronyms AMC ASCII ATCA BMC CIO Cmd CPU CRC CSA DDR EC ECC EIA EMC ESD ETSI EXP FCC FRU GbE GNU GPL I2C IEC IPMB IPMI ISP ITP JTAG KCS LED LPC LUN MAC NEBS netFn NSP Advanced Mezzanine Card American Standard Code for Information Interchange Advanced Telecom Computing Architecture or AdvancedTCA Baseboard Management Controller Common I/O (RLDRAM) Command code Central Processing Unit Cyclic Redundancy Code Canadian Standards Association Double Data Rate European Community Error-correcting Code E
Acronyms: (continued) OEM PCI PCIe PHY PLD POST RLDRAM RMA SCP SDR SDRAM SEL SERDES SIO SO-CDIMM SPI-4.
Index A E L air flow rate . . . . . . . . . . . . . . . . . . . 2-9 E-keying . . . . . . . . . . . . . . . . . . . . . 9-1 environment parameter commands, monitor. . . . . . . . . . . . . . . . . . . . . 9-19 environment variables . . . . . . . . . . 9-6 equipment for setup . . . . . . . . . . . . 2-8 ESD prevention . . . . . . . . . . . . . . . . 2-1 Ethernet address . . . . . . . . . . . . . . . . 3-5, 6-3 RJ45 connectors . . . . . . . . . . . . . 6-4 LEDs Ethernet ports . . . . . . . . . . . . . .
Index (continued) start-up display . . . . . . . . . . 3-6, 9-2 test commands . . . . . . . . . . . . .9-20 TFTP booting . . . . . . . . . . . . . . . 9-1 troubleshooting . . . . . . . . . . . .9-28 typographic conventions . . . . . . 9-8 U-Boot . . . . . . . . . . . . . . . . . . . . 9-1 updates . . . . . . . . . . . . . . . . . . . . 9-6 monitor commands autoscr . . . . . . . . . . . . . . . . . . .9-20 base . . . . . . . . . . . . . . . . . . . . .9-20 bdinfo . . . . . . . . . . . . . . . . . . . .
Index (continued) U W Z UL certifications . . . . . . . . . . . . . . . 1-5 watchdog timer . . . . . . . . . . . . . . 7-12 watchdog, BMC . . . . . . . . .9-17, 9-26 zone 1-3 connectors . . . . . . . . . . . .
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Notes ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ________________________________________
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