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Embedded Computing for

Business-Critical Continuity

MVME2500

Installation and Use

P/N: 6806800L01H

January 2014

Summary of content (146 pages)

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Embedded Computing for Business-Critical ContinuityTM MVME2500 Installation and Use P/N: 6806800L01H January 2014
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© 2014 Emerson All rights reserved. Trademarks Emerson, Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co. © 2014 Emerson Electric Co. All other product or service names are the property of their respective owners. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
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Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1 1.2 1.3 1.4 1.5 2 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 2.2 2.
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Contents Contents 3.5 4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.1 4.2 4.3 4.4 4 3.4.1.3 USB Connector (J5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.1.4 VMEBus P1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.1.5 VMEBus P2 Connector . . . . . . . . . . . . . .
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Contents 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.4.1 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.2 Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents Contents 5 Memory Maps and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 5.2 5.3 5.4 5.5 5.6 6 Boot System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.1 6.2 6.3 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 6.4 6.5 6.6 7 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.1 7.2 7.3 7.4 7.5 7.6 7.7 A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents Contents Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 2-1 Table 2-2 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 3-20 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Key Features of the MVME2500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Table 5-20 Table 5-21 Table 5-22 Table 5-23 Table 5-24 Table 5-25 Table 5-26 Table 5-27 Table 6-1 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table B-1 Table B-2 Table B-3 10 PLD Month Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures Figure 1-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 4-1 Figure 4-2 Figure 4-3 Figure A-1 Serial Number Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Front Panel LEDs, Connectors and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 12 MVME2500 Installation and Use (6806800L01H)
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About this Manual Overview of Contents This manual is divided into the following chapters and appendices.  Introduction gives an overview of the features of the product, standard compliances, mechanical data, and ordering information.  Hardware Preparation and Installation outlines the installation requirements, hardware accessories, switch settings, and installation procedures.  Controls, LEDs, and Connectors describes external interfaces of the board. This includes connectors and LEDs.
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About this Manual About this Manual 14 Term Definition DUART Dual UART EEPROM Erasable Programmable Read-Only Memory FCC Federal Communications Commission GB GigaByte Gbit Gigabit Gbps Gigabits per second I/O Input/Output IEEE Institute of Electrical and Electronics Engineers LED Light Emitting Diode MHz Megahertz MCP Multi-Chip Package MRAM Magnetoresistive Random Access Memory OS Operating System PCB Printed Circuit Board PCI Peripheral Component Interconnect PCI-E PCI E
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About this Manual Term Definition USB Universal Serial Bus VITA VMEbus International Trade Association VME Versa Module Eurocard XMC PCI Express Mezzanine Card Conventions The following table describes the conventions used throughout this manual.
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About this Manual About this Manual Notation Description | Logical OR Indicates a hazardous situation which, if not avoided, could result in death or serious injury Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered.
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About this Manual Summary of Changes This manual has been revised and replaces all prior editions. Part Number Publication Date Description 6806800L01A June 2010 First edition 6806800L01B October 2010  This version includes updates and revisions for the EA release of the MVME2500.  Table 1.3. Added mechanical data.  Table 4-3. Removed the following commands: brd_reset, irqinfo, mac. Added soft_reset.  Table 4-1. Removed: L2 SRAM, L1 for stack and Boot Page entries.
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About this Manual About this Manual Part Number Publication Date Description 6806800L01E July 2011  Updated Table "Available Board Variants" on page 22.  Updated Appendix B, Related Documentation, on page 129.  Changed title of Section 3.4.1 to Front Panel Connectors.  Edited Front Panel Serial Port (J4).  Updated Figure "Component Layout" on page 35 to include proper label for XMC connectors.  Updated Safety Notes and Sicherheitshinweise.
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Chapter 1 Introduction 1.1 Overview The MVME2500 is a VMEbus board based on the Freescale QorlQ P2010 (single-core) or P2020 (dual-core) processor. It has a 6U form-factor and has an expansion slot for an optional PCI Mezzanine Card (PMC) or PCI eXpress Mezzanine Card (XMC). It comes with either 1 GB or 2 GB of DDR3 SDRAM, and is offered with either IEEE 1101.10 compliant or SCANBE ejector handles. The front panel I/O configuration consists of two RJ45 10/100/1000BASE-T Ethernet ports, a USB 2.
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Introduction Table 1-1 Key Features of the MVME2500 (continued) Function Features Front panel I/O  Micro DB9 RS-232 serial console port  USB 2.
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Introduction Table 1-1 Key Features of the MVME2500 (continued) 1.2 Function Features Operating System  Based from BSP provided by Freescale which is based from standard Linux version 2.6.32-rc3  Development tool is ltib 9.1.1 (Linux Target Image Builder) from Freescale  VxWorks Standard Compliances The product is designed to meet the following standards. Results are pending until testing is finished.
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Introduction 1.3 Mechanical Data The following table provides details about the dimensions and weight of the board. Table 1-3 Mechanical Data 1.4 Feature Value Height 233.44 mm (9.2 inches) Depth 160.0 mm (6.3 inches) Front Panel Height 261.8 mm (10.3 inches) Width 19.8 mm (0.8 inches) Max. Component Height 14.8 mm (0.
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Introduction As of the printing date of this manual, the following board accessories are available.
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Introduction 1.5 Product Identification The following graphics shows the location of the serial number label.
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Chapter 2 Hardware Preparation and Installation 2.1 Overview This chapter provides installation and safety instructions for this product. Installation instructions for the optional PMC and transition module are also included. A fully implemented MVME2500 consists of the base board plus:  PCI Mezzanine Card (PMC) or PCI-E Mezzanine Card (XMC) for added versatility  Rear transition module  SATA kit The following are the things that need to be done before using the board.
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Hardware Preparation and Installation 2.2 Unpacking and Inspecting the Board Read all notices and cautions prior to unpacking the product.  Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life.  Before touching the board or electronic components, make sure that you are working in an ESD-safe environment. Shipment Inspection 1. Verify that you have received all items of your shipment. 2.
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Hardware Preparation and Installation 2.3.1 Environmental Requirements Operating temperatures refer to the temperature of the air circulating around the board and not to the component temperature.
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Hardware Preparation and Installation Product Damage 2.3.2  High humidity and condensation on the board surface causes short circuits.  Do not operate the board outside the specified environmental limits.  Make sure the board is completely dry and there is no moisture on any surface before applying power. Power Requirements The board uses +5.0 V from the VMEbus backplane. On board power supply generates the required voltages for the various ICs.
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Hardware Preparation and Installation The following table shows the power available when the MVME2500 is installed in either a three row or five row chassis and when PMCs are present. Chassis Type Available Power Power With PMCs Three Row 70 W maximum below 70 W Five Row 90 W maximum below 90 W Keep below power limit. Cooling limitations must be considered. 2.3.3 Equipment Requirements The following are recommended to complete a MVME2500 system: 2.
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Hardware Preparation and Installation 2.5 Installing Accessories 2.5.1 Rear Transition Module The MVME2500 does not support hot swap. Remove power to the rear slot or system before installing the module. A PCMI/O Module (PIM) needs to be manually configured and installed before placing the transition module. Damage of Circuits  Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life.
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Hardware Preparation and Installation 4. Install the top and bottom edge of the transition module into the rear guides of the chassis. 5. Ensure that the levers of the two injector/ejectors are in the outward position. 6. Slide the transition module into the chassis until resistance is felt. 7. Move the injector/ejector levers in an inward direction. 8. Verify that the transition module is properly seated and secure it to the chassis using the two screws adjacent to the injector/ejector levers. 9.
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Hardware Preparation and Installation 1. Attach an ESD strap to your wrist. Attach the other end of the strap to the chassis as a ground. Make sure that it is securely fastened throughout the procedure. 2. Remove the PMC/XMC filler plate from the front panel cut-out. 3. Slide the front bezel of the PMC/XMC into the cut-out from behind. The front bezel of the PMC/XMC module will be flushed with the board when the connectors on the module align with the mating connectors on the board. 4.
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Hardware Preparation and Installation Damage of Circuits  Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life.  Before touching the board or electronic components, make sure that you are working in an ESD-safe environment. Product Damage  Only use injector handles for board insertion to avoid damage to the front panel and/or PCB. Deformation of the front panel can cause an electrical short or other board malfunction. 1.
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Hardware Preparation and Installation 2.7 Completing the Installation The board is designed to operate as an application-specific computer blade or an intelligent I/O board/carrier. It can be used in any slot in a VME chassis. Once the board is installed, you are ready to connect peripherals and apply power to the board. Product Damage  RJ-45 connectors on modules are either twisted-pair Ethernet (TPE) or E1/T1/J1 network interfaces.
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Chapter 3 Controls, LEDs, and Connectors 3.1 Board Layout The following figure shows the components and connectors on the MVME2500.
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Controls, LEDs, and Connectors 3.2 Front Panel The following components are found on the MVME2500 front panel.
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Controls, LEDs, and Connectors 3.2.1 Reset Switch The MVME2500 has a single push button switch that has both the abort and reset functions. Pressing the switch for less than three seconds generates an abort interrupt to the P20x0 QorIQ PIC. Holding it down for more than three seconds will generate a hard reset. The VME SYSRESET is generated if the MVME2500 is the VMEbus system controller. 3.
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Controls, LEDs, and Connectors Table 3-1 Front Panel LEDs Label Function Location Color Description USER 1 User Defined Front panel Off By default Yellow User Software Controllable. Refer to the "User LED Register." Red User Software Controllable. Refer to the "User LED Register." Off Normal operation after successful firmware boot. Red One or more on-board power rails has failed and the board has shutdown to protect the hardware.
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Controls, LEDs, and Connectors 3.3.2 Onboard LEDs The onboard LEDs are listed below. To view its location on the board, see Figure 3-1 on page 35. Figure 3-4 Onboard LEDs Table 3-2 Onboard LEDs Status 3.4 Label Function Color Description D9 Power Fail Red This indicator is illuminated when one or more of the onboard voltage rails fails. D33 User Defined Amber Controlled by the FPGA. Used for boot-up sequence indicator. D34 User Defined Amber Controlled by the FPGA.
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Controls, LEDs, and Connectors 3.4.1 Front Panel Connectors The following connectors are found on the outside of the MVME2500. These connectors are divided between the front panel connectors and the backplane connectors. The front panel connectors include the J1 and J5 connectors. The backplane connectors include the P1 and P2 connectors. 3.4.1.1 RJ45 with Integrated Magnetics (J1) The MVME2500 uses an X2 RJ45.
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Controls, LEDs, and Connectors Table 3-3 Front Panel Tri-Speed Ethernet Connector (J1) (continued) 3.4.1.
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Controls, LEDs, and Connectors 3.4.1.3 USB Connector (J5) The MVME2500 uses upright USB receptable mounted in the front panel. Table 3-5 USB Connector (J5) 3.4.1.4 Pin Name Signal Description 1 +5 V 2 Data - 3 Data + 4 GND MTG Mounting Ground MTG Mounting Ground MTG Mounting Ground MTG Mounting Ground VMEBus P1 Connector The VME P1 connector is a 160-pin DIN. The P1 connector provides power and VME signals for 24-bit address and 16-bit data.
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Controls, LEDs, and Connectors Table 3-6 VMEbus P1 Connector (continued) Pin Row A Row B Row C Row D Row Z 10 SYSCLK BGIN3 SYSFAIL GA0 GND 11 GND BGOUT3 BERR GA1 NC 12 DS1 BR0 SYSRESET +3.3V (not used) GND 13 DS0 BR1 LWORD GA2 NC 14 WRITE BR2 AM 5 +3.3V (not used) GND 15 GND BR3 ADD 23 GA3 NC 16 DTACK AM 0 ADD 24 +3.3V (not used) GND 17 GND AM 1 ADD 25 GA4 NC 18 AS AM 2 ADD 26 +3.
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Controls, LEDs, and Connectors 3.4.1.5 VMEBus P2 Connector The VME P2 connector is a 160-pin DIN. Row B of the P2 connector provides power to the MVME2500 and to the upper eight VMEbus address lines and additional 16 VMEbus data lines.
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Controls, LEDs, and Connectors Table 3-7 VMEbus P2 Connector (continued) Pin Row A Row B Row C Row D Row Z 23 PMC IO 46 DATA 24 PMC IO 45 GE4_2 - Serial 3 RTS 24 PMC IO 48 DATA 25 PMC IO 47 GE4_2+ GND 25 PMC IO 50 DATA 26 PMC IO 49 GND Serial 4 RX 26 PMC IO 52 DATA 27 PMC IO 51 GE4_1 - GND 27 PMC IO 54 DATA 28 PMC IO 53 GE4_1 + Serial 4 TX 28 PMC IO 56 DATA 29 PMC IO 55 GND GND 29 PMC IO 58 DATA 30 PMC IO 57 GE4_0 - Serial 4 CTS 30 PMC IO 60 DATA 31 PMC IO
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Controls, LEDs, and Connectors Table 3-8 Flash Programming Header (P7) (continued) Pin Signal Description GND 10 3.4.2.2 Master OUT Slave IN (MOSI) SATA Connector (J3) The onboard customized SATA connector is compatible with the Emerson SATA kit, namely VME-64GBSSDKIT and IVME7210-MNTKIT.
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Controls, LEDs, and Connectors Table 3-9 Custom SATA Connector (J3) (continued) 3.4.2.3 Pin Signal Description Pin Signal Description 19 NC 39 +3.3V 20 GND 40 +5V PMC Connectors The MVME2500 supports only one PMC site. It utilizes J14 to support PMC I/O that goes to the RTM PMC. The tables below show the pinout detail of J11, J12, J13 and J14. See Figure 3-1 for the location of the PMC connectors.
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Controls, LEDs, and Connectors Table 3-10 PMC J11 Connector (continued) Pin Signal Description Pin Signal Description 18 +5V 50 +5V 19 +3.3V 51 GND 20 AD 31 52 CBE0 21 AD 28 53 AD 6 22 AD 27 54 AD 5 23 AD 25 55 AD 4 24 GND 56 GND 25 GND 57 +3.3V 26 CBE3 58 AD 3 27 AD 22 59 AD 2 28 AD 21 60 AD 1 29 AD 19 61 AD 0 30 +5V 62 +5V 31 +3.
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Controls, LEDs, and Connectors Table 3-11 PMC J12 Connector (continued) Pin Signal Description Pin Signal Description 10 NC 42 SERR 11 BUSMODE2 (Pulled UP) 43 CBE1 12 +3.3V 44 GND 13 PCI RESET 45 AD 14 14 BUSMODE3 (PULLED DWN) 46 AD 13 15 +3.3V 47 M66EN 16 BUSMODE4 (PULLED DWN) 48 AD 10 17 NC 49 AD 8 18 GND 50 +3.3V 19 AD 30 51 AD 7 20 AD 29 52 REQB 21 GND 53 +3.3V 22 AD 26 54 GNTB 23 AD 24 55 NC 24 +3.
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Controls, LEDs, and Connectors Table 3-12 PMC J13 Connector (continued) 50 Pin Signal Description Pin Signal Description 2 GND 34 AD48 3 GND 35 AD 47 4 CBE7 36 AD 52 5 CBE6 37 AD 45 6 CBE5 38 GND 7 CBE4 39 +3.3V 8 GND 40 AD 40 9 +3.3V 41 AD 43 10 PAR64 42 AD 42 11 +3.
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Controls, LEDs, and Connectors Table 3-12 PMC J13 Connector (continued) Pin Signal Description Pin Signal Description 29 AD 51 61 NC 30 AD 50 62 GND 31 AD 49 63 GND 32 GND 64 NC Table 3-13 PMC J14 Connector Pin Signal Description Pin Signal Description 1 PMC IO 1 33 PMC IO 33 2 PMC IO 2 34 PMC IO 34 3 PMC IO 3 35 PMC IO 35 4 PMC IO 4 36 PMC IO 36 5 PMC IO 5 37 PMC IO 37 6 PMC IO 6 38 PMC IO 38 7 PMC IO 7 39 PMC IO 39 8 PMC IO 8 40 PMC IO 40 9 PMC IO
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Controls, LEDs, and Connectors Table 3-13 PMC J14 Connector (continued) 3.4.2.
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Controls, LEDs, and Connectors Table 3-14 JTAG Connector (P6) (continued) Pin Signal Description Pin Signal Description 19 GPO0 20 NC 21 NC 22 SCAN 2 TMS 23 NC 24 SCAN 2 TDO 25 SCAN 2 TCK 26 +3.3V FROM +5V 27 GND 28 SCAN 2 TDI 29 NC 30 NC 31 SCAN 3 TMS 32 SCAN 3 TCK1 33 SCAN 3 TDO 34 SCAN 3 TCK 2 35 +2.5V 36 SCAN 3 TCK 3 37 SCAN 3 TDI 38 GND 39 SCAN 3 TRST 40 SCAN 3 TCK3 41 SCAN 4 TCK 1 42 SCAN 4 TMS 43 GND 44 SCAN 4 TDO 45 SCAN 4 TCK 2 46 +3.
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Controls, LEDs, and Connectors 3.4.2.5 COP Connector (P6) The COP header is used for the CPU debug. The pin assignment is dictated by Freescale and is compatible with the processor’s debugging tool. Table 3-15 COP Header (P10) 3.4.2.
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Controls, LEDs, and Connectors Table 3-16 SD Connector (J2) (continued) 3.4.2.7 Pin Signal Description 2 COMMAND 3 GND 4 VCC (+3.3V) 5 CLOCK 6 GND 7 DATA 0 8 DATA 1 9 DATA 2 10 WRITE PROTECT 11 CARD DETECT 12 GND XMC Connector (XJ2) The MVME2500 has one XMC connector (XJ2) that supports XMC cards with J15 connector. It can also support XMC cards with J16 connector without encountering any mechanical interference.
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Controls, LEDs, and Connectors Table 3-17 XMC Connector (XJ2) Pinout (continued) Pin Row A Row B Row C Row D Row E Row F 9 NC NC NC NC NC +3.3V 10 GND GND JTAG TDO GND GND GA 0 11 TX0 TX0 - BIST (PULLED UP) TX1 + TX1 - +3.3V 12 GND GND GA 1 GND GND PRESENT 13 NC NC NC NC NC +3.3V 14 GND GND GA 2 GND GND I2C DATA 15 NC NC NC NC NC +3.
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Controls, LEDs, and Connectors Table 3-18 P20x0 Debug Header (continued) 3.5 Pin Signal Description 8 TRIG_IN 9 MSRCID4 10 GND Switches These switches control the configuration of the MVME2500. Board Malfunction 3.5.1  Switches marked as “reserved” might carry production-related functions and can cause the board to malfunction if their settings are changed.  Do not change settings of switches marked as “reserved”.
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Controls, LEDs, and Connectors Note that this switch is wired in parallel with the geographical address pins on the 5-row connector. These switches must be in the "OFF" position when installed in a 5-row chassis in order to get the correct address from the P1 connector. This switch also includes the SCON control switches.
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Controls, LEDs, and Connectors 3.5.2 SMT Configuration Switch (S2) This eight position SMT configuration switch controls the flash bank write-protect, selects the flash boot image, and controls the safe start ENV settings. The default setting on all switch positions is "OFF" and is indicated by brackets in Table 3-20.
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Controls, LEDs, and Connectors Table 3-20 Geographical Address Switch Settings (continued) SW2 DEFAULT Signal Name Description Notes 6 OFF (WP Enabled) MASTER_WP_DISA BLED Write-Protect Disable switch For I2C write-protect only. 7 OFF (Front) GBE_MUX_SEL User Defined switch that will select if the GBE PHY will function on the front panel or on the Back PLANE 8 OFF (CPU Reset Deasserted) Reserved 60 Should be "OFF" for normal operation.
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Chapter 4 Functional Description 4.1 Block Diagram The MVME2500 block diagram is illustrated in Figure 4-1. All variants provide front panel access to one serial port via a micro-mini DB-9 connector, two 10/100/1000 Ethernet port (one is configurable to be routed on the front panel or to the rear panel) through a ganged RJ45 connector and one Type A USB Port. It includes Board Fail LED indicator, user-defined LED indicator and a ABORT/RESET switch. Figure 4-1 4.
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Functional Description This section describes the protocol and interfaces provided in the QorIQ P20x0 integrated and is utilized by the MVME2500. 4.2.1 e500 Processor Core The QorIQ integrated processors offer dual high performance e500v2 core (P2020) and a single e500v2 core (P2010). It operates from 800 MHz up to 1.2GHz core frequency.
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Functional Description 4.2.3  Automatic DRAM initialization sequence or software-controlled initialization sequence and automatic DRAM data initialization.  Write leveling for DDR3 memories and supports up to eight posted refreshes. PCI Express Interface The PCI Express interface is compatible with the PCI Express Base Specification Rev. 1.0a. The PCI Express controller connects the internal platform to a 2.5 GHz serial interface.
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Functional Description 4.2.8 DUART The chipset provides two universal asynchronous receiver/transmitter (UART), each of which acts independently of the other. Each UART is clocked by the CCB clock and is compatible with PC16522D. As a full-duplex interface, it provides a 16-byte FIFO for both transmitter and receiver mode. 4.2.9 DMA Controller The DMA controller transfers blocks of data between the various interfaces and functional blocks of P20x0 that are independent of the e500 cores.
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Functional Description 4.2.13 Common On-Chip Processor (COP) The COP is the debug interface of the QorIQ P20x0 Processor. It allows a remote computer system to access and control the internal operation of the processor. The COP interface connects primarily through the JTAG and has additional status monitoring signals. The COP has additional features like breakpoints, watch points, register and memory examination/modification and other standard debugging features. 4.2.
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Functional Description See Real-Time Clock Battery, on page 77 for more information on the real time clock back-up battery. 4.4.2 Internal Timer The processor's internal timer is composed of eight global timers divided into two groups of four timers each. Each time has four individual configuration registers and they cannot be cascaded together. 4.4.3 Watchdog Timer The onboard FPGA provides programmable 16-bit watchdog timers.
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Functional Description 4.6 SPI Bus Interface The enhanced serial peripheral interface (eSPI) allows the device to exchange data with peripheral devices such as EEPROMs, RTC, Flash and the like. The eSPI is a full-duplex synchronous, character-oriented channel that supports a simple interface such as receive, transmit, clock and chip selects. The eSPI receiver and transmitter each have a FIFO of 32 Bytes. P20x0 supports up to four chip selects and RapidS full clock cycle operation.
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Functional Description  Factory Pre-Programming - Programming the SPI Flash usually takes a while. Ideally, the SPI Flash should be pre-programmed in the factory before shipment.  ICT Programming - This programming is done on exposed test points using a bed of nails tester. The board power should be switched on before programming. The switch S2-8 should also be powered on to successfully detect the SPI Flash chip. 4.6.
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Functional Description The MVME2500 FPGA controls the chip select to SPI devices A and B. The FPGA chip select control is based on the Switch Bank (S2-2). Figure 4-2 SPI Device Multiplexing Logic At power-up, the selection of the SPI boot device is strictly based upon the Switch Bank (S2-2) setting. Depending on the S2-2 setting, SPI_SEL0 is routed to one of two SPI devices. The selected SPI device must contain a boot image.
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Functional Description The MVME2500 supports automatic switch over. If booting one device is not successful, the watchdog will trigger the board reset and it will automatically boot on the other device. 4.6.4 Crisis Recovery The MVME2500 provides an independent boot firmware recovery mechanism for the operating system. The firmware recovery can be performed without leaving the firmware environment.
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Functional Description Only 115200 bps and 9600 bps are supported. The default baud rate on the front panel serial is 9600 kbps. 4.8 Rear UART Control The MVME2500 utilizes the Exar ST16C554 quad UART (QUART) to provide four additional ports to the RTM. These devices feature 16 bytes of transmit and receive first-in first-out (FIFO) with selectable receive FIFO trigger levels and data rates of up to 1.5 Mbps. Each UART has a set of registers that provide the user with operating status and control.
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Functional Description PMC/XMC sites are keyed for 3.3V PMC signaling. PMC and XMC add-on cards must have a hole in the 3.3 V PMC keying position in order to be populated on the MVME2500. The XMC specification accommodates this since it is expected that carrier cards will host both XMC and PMC capable add-on cards. MVME2500 utilizes the P20x0 x2 link PCI Express interface. It is designed such that the same PCI-E interface is used for either PMC or XMC through Pericom’s PI2PCIE2412.
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Functional Description The MVME2500 uses Marvell's 88SE6121B2-NAA2C000 SATA controller and supports up to 1.5 Gbps (SATA Gen 1). For status indicators, it has an onboard green LED, D12 and D13 for SATA link and SATA activity status respectively. 4.11 VME Support The MVME2500 can operate in either System Controller (SCON) mode or non-SCON mode, as determined by the the switch setting of S1-1 and S1-2.
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Functional Description The RTM I2C address can be configured by the user and should not contain duplicate addresses to avoid conflict. For more information, see I2C Bus Device Addressing, on page 118. 4.14 Reset/Control FPGA The FPGA provides the following functions: 4.
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Functional Description Table 4-1 Voltage Supply Requirement Voltage Rail Requirement Voltage Rail Minimum Maximum +2.5 V 2.375 V 2.625 V +1.8 V 1.7 V 1.9 V +1.5 V 1.425 V 1.575 V +1.2 V 1.14 V 1.26 V +1.2 V_SW 1.14 V 1.26 V +1.05 V 1.0 V 1.1 V 4.15.2 Power Up Sequencing Requirements The power up sequence describes the voltage rail power up timing, which is designed to support all the chip supply voltage sequencing requirement.
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Functional Description 4.16 Clock Structure A total of three IDT chips, a discrete oscillator and crystal to support all the clock requirements of MVME2500. Figure 4-3 4.17 Clock Distribution Diagram Reset Structure MVME2500 reset will initiate after the power up sequence if the 1.5 V power supply is "GOOD". When the board is at "ready" state, the reset logic will monitor the reset sources and implement the necessary reset function.
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Functional Description 4.17.1 Reset Sequence The timing of the reset sequence supports each chip reset requirements with respect to the power supply. 4.18 Thermal Management The MVME2500 utilizes two on-board temperature sensors: one for the board and the other for the CPU temperature sensor. The board temperature sensor is located near the dual RJ45 connector near the front panel. The CPU temperature sensor is located near the P2020 CPU.
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Functional Description 4.20 Debugging Support The following information shows the details of Emerson debugging support as applied to the MVME2500. 4.20.1 POST Code Indicator The following table shows the LED status of the POST Codes. For the location of the POST Code LEDs, see Onboard LEDs, on page 39. Logic 1 means LED is "ON", Logic 2 means LED is "OFF" Table 4-3 POST Code Indicator on the LED Sequence D33 D32 D35 Description 1 0 0 0 U-boot has been copied from SPI flash to CPU cache.
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Functional Description The JTAG board provides three different connectors for the ASSET hardware, flash programming and the MVME2500 JTAG connector. The board is equipped with TTL buffers to help improve the signal quality as it traverses over the wires. 4.20.3 Custom Debugging Custom debugging makes use of the common on-chip processor. Refer to Common On-Chip Processor (COP), on page 65 for details. 4.21 Rear Transition Module (RTM) The MVME2500 is compatible with the MVME721x RTM.
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Functional Description 80 MVME2500 Installation and Use (6806800L01H)
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Chapter 5 Memory Maps and Registers 5.1 Overview System resources including system control and status registers, external timers, and the QUART are mapped into 16 MB address range accessible from the MVME2500 local bus through the P20x0 QorIQ LBC. 5.2 Memory Map The following table shows the physical address map of the MVME2500.
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Memory Maps and Registers 5.3 Flash Memory Map The table below lists the memory range designated to U-boot and ENV variables. Table 5-2 Flash Memory Map 5.4 Description Memory Area U-boot 0x00000000 0x0008ffff Reserved 0x00090000 0x0009ffff ENV Variables 0x00100000 0x0011ffff Available Flash 0x00120000 0x007fffff Linux Devices Memory Map The table below lists the memory ranges designated to different devices in Linux.
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Memory Maps and Registers Table 5-3 Linux Devices Memory Map Device Memory Range Memory Area Size FPGA 0xffdf0000 0xffdf0fff 4 KB ecm local access window CCSR 0xffe00000 0xffe00ffff 4 KB ecm (Error Correction Module) CCSR 0xffe01000 0xffe01fff 4 KB Memory Controller CCSR 0xffe02000 0xffe02fff 4 KB I2C1 CCSR 0xffe03000 0xffe030ff 256 B I2C2 CCSR 0xffe03100 0xffe031ff 256 B UART0 CCSR 0xffe04500 0xffe045ff 256 B UART1CCSR 0xffe04600 0xffe046ff 256 B ELBC CCSR 0xffe05000 0xffe05fff
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Memory Maps and Registers 5.5 Programmable Logic Device (PLD) Registers 5.5.1 PLD Revision Register The MVME2500 provides a PLD revision register that can be read by the system software to determine the current version of the timers/registers PLD. Table 5-4 PLD Revision Register REG PLD Revision Register - 0xFFDF0000 Bit 7 Field PLD Rev OPER R RESET 03 6 5 4 3 2 1 0 Field Description PLD_REV 5.5.2 8-bit field containing the current timer/register PLD revision.
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Memory Maps and Registers 5.5.3 PLD Month Register The MVME2500 PLD provides an 8-bit register which contains the build month of the timers/registers PLD. Table 5-6 PLD Month Register 5.5.4 REG PLD Year Register - 0xFFDF0005 Bit 7 Field PLD Rev OPER R RESET 0A 6 5 4 3 2 1 0 PLD Day Register MVME2500 PLD provides an 8-bit register which contains the build day of the timers/registers PLD. Table 5-7 PLD Day Register 5.5.
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Memory Maps and Registers Table 5-8 PLD Sequence Register 5.5.6 REG PLD Revision Register - 0xFFDF0007 Bit 7 Field PLD Rev OPER R RESET 02 6 5 4 3 2 1 0 PLD Power Good Monitor Register The MVME2500 PLD provides an 8-bit register which indicates the instantaneous status of the supply’s power good signals.
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Memory Maps and Registers 5.5.7 PWR_V3P3_PWRGD 3.3V Supply power good indicator PWR_V2P5_PWRGD 2.5V Supply power good indicator PWR_V1P2_SW_PWRG D 1.2V SW Supply power good indicator PWR_V1P5_PWRGD 1.5V Supply power good indicator 1 - Supply Good and Stable 0 - Otherwise PLD LED Control Register The MVME2500 PLD provides an 8-bit register which controls the eight LEDs.
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Memory Maps and Registers 5.5.8 PLD PCI/PMC/XMC Monitor Register The MVME2500 PLD provides an 8-bit register which indicates the status of the PCI/PMC/XMC interface signals.
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Memory Maps and Registers 5.5.9 PLD U-Boot and TSI Monitor Register The MVME2500 PLD provides an 8-bit register which indicates the status of the U-Boot's normal environment switch and TSI interface signals.
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Memory Maps and Registers Table 5-13 PLD Boot Bank Register REG PLD Boot Bank - 0xFFDF0050 Field SPI_GOODReg (write 0xA4 into this reg to indicate successful loading of the UBoot.
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Memory Maps and Registers 5.5.11 PLD Write Protect and I2C Debug Register The MVME2500 PLD provides an 8-bit register which is used to indicate the status of I2C and SPI write-protect manual switches and is used to control the SPI write-enable. I2C debug ports are also provided in this register which can be used in controlling the bus’ status.
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Memory Maps and Registers I2C_DEBUG_EN I2C debug ports (I2C_1_D and I2C_1_C) enable 1 - Drive Enabled 0 - Drive Disabled SERIAL_FLASH_WP SPI devices write-protect register 1 - Write-protect enabled 0 - Write-protect disabled I2C_1_D I2C debug port-Data I2C_DEBUG_EN=0 HiZ - Tri-Stated I2C_DEBUG_EN-1 1 - Driven High 0 - Driven Low I2C_1_C I2C debug port-Clock I2C_DEBUG_EN=0 HiZ - Tri-Stated I2C_DEBUG_EN-1 1 - Driven High 0 - Driven Low When SERIAL_FLASH_WP is set to "Low", this port will automaticall
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Memory Maps and Registers 5.5.12 PLD Test Register 1 The MVME2500 PLD provides an 8-bit general purpose read/write register which can be used by the software for PLD testing or general status bit storage. Table 5-15 PLD Test Register 1 REG PLD Test Register 1- 0xFFDF0080 Bit 7 Field TEST_REG1 OPER R/W RESET 00 6 5 4 3 2 1 0 Field Description TEST_REG1 General purpose 8-bit R/W field 5.5.
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Memory Maps and Registers 5.5.14 PLD GPIO2 Interrupt Register The Abort switch, Tick Timer 0, 1 and 2 interrupts are ORed together. The MVME2500 provides an interrupt register that the system software reads to determine which device the interrupt originated from. GPIO2 will be driven "low" if any of the interrupts asserts.
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Memory Maps and Registers 5.5.15 PLD Shutdown and Reset Control and Reset Reason Register The MVME2500 provides an 8-bit register to execute the shutdown and reset commands. The board's reset reason is also included in this register.
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Memory Maps and Registers CPU_RESET CPU_HRESET_REQ_L Reset Reason 1 - Reset is due to CPU_HRESET_REQ_L signal 0 -None WD_TIMEOUT Watchdog Timeout Reset Reason 1 - Reset is due to watchdog timing out 0 - None LRSTO TSI LRSTO Reset Reason 1 - Reset is due to LRSTO signal 0 - None Sft_RST Soft Reset - Reset Reason 1 - Reset is due to Soft_RST register being set, or the front panel switch being pressed more than three 0 - None 5.5.
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Memory Maps and Registers 5.5.17 PLD Watchdog Control Register The MVME2500 provides a watchdog control register. Table 5-20 PLD Watchdog Control Register REG PLD Watch Dog Timer Load - 0xFFC80604 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Watchdog_EN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPER R/W R RESET 0000 Field Description EN Enable. If cleared, the watchdog timer is disabled. If set, the watchdog timer is enabled. 5.
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Memory Maps and Registers Field Description Count 5.6 Count. These bits define the watchdog timer count value. When the watchdog counter is enabled, it will count up from zero (reset value) with a 1 ms resolution until it reaches the COUNT value set by this register. Watchdog will generate a soft reset signal if it bites. Setting this register to 0xEA60 or 60,000 counts will provide a watchdog timeout of 60 seconds.
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Memory Maps and Registers 5.6.2 Control Registers Table 5-23 Control Registers Tick Timer 0 Control Register - 0xFFC80202 Tick Timer 1 Control Register - 0xFFC80302 REG Tick Timer 2 Control Register - 0xFFC80402 Bit 15 14 13 12 11 10 9 8 7 Field RSVD RSVD RSVD RSVD RSVD INTS CINT ENINT OVF OPER R/W RESET 0x0000 6 5 4 3 2 1 0 RSVD COVF COC ENC Field Description ENC Enable counter. When the bit is set, the counter increments.
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Memory Maps and Registers 5.6.3 Compare High and Low Word Registers The tick timer counter is compared to the Compare Register. When the values are equal, the tick timer interrupt is asserted and the overflow counter increments. If the clear-on-compare mode is enable, the counter is also cleared.
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Memory Maps and Registers 5.6.4 Counter High and Low Word Registers When enabled, the tick timer counter register increments every microsecond. Software may read or write the counter at any time.
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Memory Maps and Registers 102 MVME2500 Installation and Use (6806800L01H)
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Chapter 6 Boot System 6.1 Overview The MVME2500 uses Das U-Boot, a boot loader software based on the GNU Public License. It boots the blade and is the first software to be executed after the system is powered on. Its main functions are:  Initialize the hardware  Pass boot parameters to the Linux kernel  Start the Linux kernel  Update Linux kernel and U-Boot images This section describes U-Boot features and procedures that are specific to the MVME2500.
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Boot System U-Boot aborts the boot sequence and enters into a command line interface mode. Enter the command setenv bootdelay -1; saveenv to disable the U-Boot auto-boot feature and let the U-Boot directly enter the command line interface after the next reboot/power up. 6.3 Boot Options 6.3.1 Booting from a Network In this mode, U-Boot downloads and boots the Linux kernel from an external TFTP server and mounts a root file system located on a network server. 1.
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Boot System 6.3.2 Booting from an Optional SATA Drive 1. Make sure that the kernel, dtb, and ramdisk are saved in the SATA drive with ext2 partition. 2. Configure U-Boot environment variable: setenv File_uImage setenv File_dtp setenv File_ramdisk saveenv 3.
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Boot System 6.3.4 Booting from an SD Card 1. Make sure that the kernel, dtb, and ramdisk are saved in the SD card with FAT partition. 2. Configure the U-Boot environment variable: setenv File_uImage setenv File_dtp setenv File_ramdisk saveenv 3. Initialize SD card: mmcinfo 4.
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Boot System 3. TFTP the files from the server to local memory, then boot: run vxboot 6.4 Using the Persistent Memory Feature Persistent memory means that the RAM's memory is not deleted during a reset. Power cycling, or by temporarily removing the power and then powering up the blade again, will delete the memory content. Persistent memory feature is enabled by default.
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Boot System 6.5 MVME2500 Specific U-Boot Commands Table 6-1 MVME2500 Specific U-Boot Commands 108 Command Description base Print or set address offset bdinfo Print board info structure boot Boot default, i.e., run 'bootcmd' bootd Boot default, i.e.
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Boot System Table 6-1 MVME2500 Specific U-Boot Commands (continued) Command Description help Print online help i2c I2C sub-system iminfo Print header information for application image imxtract Extract a part of a multi-image interrupts Enable or disable interrupts itest Return true/false on integer compare loadb Load binary file over serial line (kermit mode) loads Load S-Record file over serial line loady Load binary file over serial line (ymodem mode) loop Infinite loop on address ra
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Boot System Table 6-1 MVME2500 Specific U-Boot Commands (continued) 6.
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Boot System sf probe 0 4. Erase 0x90000 bytes starting at SPI address 0: sf erase 0 0x90000 5.
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Boot System 112 MVME2500 Installation and Use (6806800L01H)
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Chapter 7 Programming Model 7.1 Overview This chapter includes additional programming information for the MVME2500. 7.2 Reset Configuration The MVME2500 supports the power-on reset (POR) pin sampling method for processor reset configuration. Each option and the corresponding default setting are described in the following table.
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Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION 6 Boot Sequence LGPL3/LFWP, LGPL5 11 CFG_BOOT_SEQ[1:0] = BOOT SEQUENCE DISABLED 7 Memory Debug Config DMA2_DACK0 1 Debug information from the DDR SDRAM controller is driven on the MSPCID and MDVAL signs (default) 8 DDR Debug Config DMA2_DDONE0 1 Debug information is not driven on ECC pins. ECC function in their normal mode (default).
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Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION 18 ETSEC2 SGMII Mode LGPL1 1 eTSEC2 Ethernet interface operates in standard parallel interface mode and uses the TSEC_2’pins (default). 19 ETSEC3 SGMMI Mode TSEC_1588_ALARM _OUT2 1 eTSEC3 Ethernet interface operates in standard parallel interface mode and uses the TSEC_3’pins (default).
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Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION 24 BOOT ROM Location TSEC1_TXD[6:4], TSEC1_TX_ER 011X On-chip boot ROM-SPI configuration (x=0), SDHC (x=1) 25 Host/Agent Config LWE1/LBS1, LA[18:19] 111 The processor acts as the host/root complex for all PCI-E/Serial Rapid IO interfaces (default). 26 I/O Port Select TSEC1_TXD[3:1], TSEC2_TX_ER 0010 PCI-E 1 (x1) (2.5 Gbps) SerDes lane 0 REMARKS PCI-E 2 (x1) (2.
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Programming Model 7.3 Interrupt Controller The MVME2500 uses the MPC8548E integrated programmable interrupt controller (PIC) to manage locally generated interrupts. Currently defined external interrupting devices and interrupt assignments, along with corresponding edge/levels and polarities, are shown in the following table.
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Programming Model 7.4 I2C Bus Device Addressing The following table contains the I2C devices used for the MVME2500 and its assigned device address. Table 7-3 I2C Bus Device Addressing I2C Bus Address Device Function Size Notes 0x50 SPD 256 x 8 0x4C ADT 7461 Temperature Sensor N/A 0x68 DS 1375 real-time clock N/A 0x54 VPD 8192 x 8 1 0x52 User configuration 65536 x 8 1 0x53 User configuration 65536 x 8 1 0x55 RTM EEPROM 8192 X 8 1, 2 0x56 XMC EEPROM N/A 3 1.
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Programming Model Table 7-4 PHY Types and MII Management Bus Address 7.6 Ethernet Port Function / Location PHY Types PHY MIIM Address TSEC2 Gigabit Ethernet port routed to front or back panel, set by GBE_MUX_SEL in S2 BCM54616 7 TSEC3 Gigabit Ethernet port routed to back panel BCM54616 3 Other Software Considerations This section provides programming information in relation to various board components. 7.6.
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Programming Model 7.6.4 LBC Timing Parameters The following table defines the timing parameters for the devices on the local bus.
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Programming Model SETA External address termination 0 - Access is terminated internally by the memory controller unless the external device asserts LGTA earlier to terminate the access. TRLX Timing Relaxed 0 - Normal timing is generated by the GPCM. EHTR Extended hold time on read accesses. 0 - The memory controller generates normal timing. No additional cycles are inserted EAD External address latch delay 0 - No additional bus clock cycles (LALE asserted for one bus clock cycle only) 7.
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Programming Model Table 7-6 Clock Distribution (continued) Device Clock Signal Frequency Clock Tree Source VIO BCM54616S SW_25MHZ_CLK 25Mhz ICS83905AGILF +3.3V XMC CLK_XMC1 100MHz ICS9FG108 DIFF QorIQ P20x0 SD_REF_CLK 100MHz ICS9FG109 DIFF TSI384 CLK_PCIEC1 100MHz ICS9FG110 DIFF TSI384 CLK_PCIEC3 100MHz ICS9FG111 DIFF 88SE6121 CLK_88SE6121_PCIE_100MH Z 100MHz ICS9FG112 DIFF FPGA CLK_CPLD 1.8432MHz Oscillator +3.3V USB CLK_USB_1_24MHZ 24MHz Oscillator +3.
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Programming Model 7.7.2 Real Time Clock Input The RTC clock input is driven by a 1 MHz clock generated by the FPGA. This provides a fixed clock reference for the QorIQ P20x0 PIC timers which the software can use as a known time reference. 7.7.3 Local Bus Controller Clock Divisor The local bus controller (LBC) clock output is connected to the FPGA for LBC bus transaction. It is also the source of 1 MHz (CPU_RTC) and FPGA tick timers.
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Programming Model 124 MVME2500 Installation and Use (6806800L01H)
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Appendix A A Replacing the Battery A.1 Replacing the Battery The figure below shows the location of the board battery.
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Replacing the Battery The battery provides seven years of data retention, summing up all periods of actual data use. Emerson therefore assumes that there is usually no need to replace the battery except, for example, in case of long-term spare part handling. Board/System Damage  Incorrect replacement of lithium batteries can result in a hazardous explosion.  When replacing the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models.
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Replacing the Battery Replacement Procedure To replace the battery, proceed as follows: 1. Remove the old battery. 2. Install the new battery with the plus sign (+) facing up. 3. Dispose of the old battery according to your country’s legislation and in an environmentally safe way.
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Replacing the Battery 128 MVME2500 Installation and Use (6806800L01H)
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Appendix B B Related Documentation B.1 Emerson Network Power - Embedded Computing Documents The publications listed below are referenced in this manual. You can obtain electronic copies of Emerson Network Power - Embedded Computing publications by contacting your local Emerson sales office. For released products, you can also visit our Web site for the latest copies of our product documentation. 1. Go to www.Emerson.com/EmbeddedComputing.The Emerson Embedded Computing website opens. 2.
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Related Documentation B.2 Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user manuals. As an additional help, a source for the listed document is provided. Please note that while these sources have been verified, the information is subject to change without notice. Table B-2 Manufacturers’ Publications B.3 Company Document Freescale Freescale Semiconductor, QorIQ™ P2020 Integrated Processor Reference Manual, Rev.
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Related Documentation Table B-3 Related Specifications Organization Document IEEE IEEE 802.3 LAN/MAN CSMA/CD Access Method IEEE 802.3-2005 IEEE Standard for a Common Mezzanine Card (CMC) Family IEEE Std 1386-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC) IEEE Std 1386.1-2001 IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1-2001 Low Pin Count Interface Specification (LPC) Revision 1.
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Related Documentation 132 MVME2500 Installation and Use (6806800L01H)
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Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
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Safety Notes Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. Changes or modifications not expressly approved by Emerson Network Power could void the user's authority to operate the equipment. Board products are tested in a representative system to show compliance with the above mentioned requirements.
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Safety Notes Make sure all software is completely shut down before removing power from the board or removing the board from the chassis. Product Damage Only use injector handles for board insertion to avoid damage to the front panel and/or PCB. Deformation of the front panel can cause an electrical short or other board malfunction. Product Damage Inserting or removing modules with power applied may result in damage to module components.
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Safety Notes Battery Board/System Damage Incorrect exchange of lithium batteries can result in a hazardous explosion. When exchanging the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models. If the respective battery model is not available, contact your local Emerson sales representative for the availability of alternative, officially approved battery models. Data Loss Exchanging the battery can result in loss of time settings.
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Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
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Sicherheitshinweise EMV Das Produkt wurde in einem Emerson Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Produktes in Gewerbe- sowie Industriegebieten gewährleisten. Das Produkt arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung.
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Sicherheitshinweise Beschädigung von Schaltkreisen Elektrostatische Entladung und unsachgemäßer Ein- und Ausbau des Produktes kann Schaltkreise beschädigen oder ihre Lebensdauer verkürzen. Bevor Sie das Produkt oder elektronische Komponenten berühren, vergewissern Sie sich, daß Sie in einem ESD-geschützten Bereich arbeiten. Fehlfunktion des Produktes Schalter, die mit 'Reserved' gekennzeichnet sind, können mit produktionsrelevanten Funktionen belegt sein.
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Sicherheitshinweise Kabel und Stecker Beschädigung des Produktes Bei den RJ-45-Steckern, die sich an dem Produkt befinden, handelt es sich entweder um Twisted-Pair-Ethernet (TPE) oder um E1/T1/J1-Stecker. Beachten Sie, dass ein versehentliches Anschließen einer E1/T1/J1-Leitung an einen TPE-Stecker das Produkt zerstören kann.  Kennzeichnen Sie deshalb TPE-Anschlüsse in der Nähe Ihres Arbeitsplatzes deutlich als Netzwerkanschlüsse.
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Sicherheitshinweise Datenverlust Wenn die Batterie wenig oder unzureichend mit Spannung versorgt wird, wird der RTC initialisiert. Tauschen Sie die Batterie aus, bevor sieben Jahre tatsächlicher Nutzung vergangen sind. Schäden an der Platine oder dem Batteriehalter Wenn Sie die Batterie mit einem Schraubendreher entfernen, können die Platine oder der Batteriehalter beschädigt werden. Um Schäden zu vermeiden, sollten Sie keinen Schraubendreher zum Ausbau der Batterie verwenden.
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Sicherheitshinweise 142 MVME2500 Installation and Use (6806800L01H)
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Index A T abbreviations 13 accessories 30 timers 65 FPGA tick timer 66 internal timer 66 real time clock 65 watchdog timer 66 B block diagram 61 board accessories 23 board configuration 29 C chipset 61 conventions 15 D disposal 26 disposal of product 21 E environmental requirements 27 I installating and removing the board 32 installation 31 M memory system memory 65 P PMC 31 PMC/PrPMC 31 product 21 related standards 21 R related data sheets 130 documents 129 specifications 130 replacing the batt
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Index 144 MVME2500 Installation and Use (6806800L01H)
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HOW TO REACH LITERATURE AND TECHNICAL SUPPORT: For literature, training, and technical assistance and support programs, visit www.emersonnetworkpower.com/embeddedcomputing Emerson Network Power. The global leader in enabling Business-Critical Continuity™ AC Power Systems Connectivity DC Power Systems Embedded Computing Embedded Power Integrated Cabinet Solutions www.emersonnetworkpower.