User’s Manual from Emerson Network Power ™ Embedded Computing PmPPC7448: PowerPC™-Based Processor PMC Module September 2007
The information in this manual has been checked and is believed to be accurate and reliable. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others. Emerson.
Regulatory Agency Warnings & Notices The Emerson PmPPC7448 meets the requirements set forth by the Federal Communications Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information is provided as required by this agency. This device complies with part 15 of the FCC Rules.
Regulatory Agency Warnings & Notices (continued) EC Declaration of Conformity According to EN 45014:1998 Manufacturer’s Name: Emerson Network Power Embedded Computing Manufacturer’s Address: 8310 Excelsior Drive Madison, Wisconsin 53717 Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC Directive and 1999/5/EC, RTTE Directive and their amending directives, Product: PowerPC™-Based Processor PMC Module Model Name/Number: PmPPC7448/10005277-xx has been desi
Contents 1 Overview Components and Features . . . . . . . . . . . 1-1 Functional Overview . . . . . . . . . . . . . . . . 1-3 Physical Memory Map . . . . . . . . . . . . . . . 1-4 Additional Information . . . . . . . . . . . . . . 1-6 Product Certification . . . . . . . . . . . . . 1-6 UL Certification. . . . . . . . . . . . . . . . . . 1-7 RoHS Compliance. . . . . . . . . . . . . . . . 1-8 Terminology and Notation . . . . . . . . 1-8 Technical References. . . . . . . . . . . . .
Contents (continued) Interrupt Pending Register (IPR) . . . 7-4 Product ID Register (PIR). . . . . . . . . . . . . .7-5 EReady Register (ERdy) . . . . . . . . . . . . . . .7-5 Revision Registers . . . . . . . . . . . . . . . . . . .7-5 Hardware Version Register (HVR) . . 7-6 PLD Version Register (PVR) . . . . . . . 7-6 Board Configuration Registers . . . . . . . . .7-6 8 Serial Input/Output Multi-Protocol Serial Controllers (MPSC)8-1 Serial DMA (SDMA) Channels . . . . . . . . . .
Contents (continued) saveenv . . . . . . . . . . . . . . . . . . . . . .11-17 setenv. . . . . . . . . . . . . . . . . . . . . . . .11-17 Test Commands . . . . . . . . . . . . . . . . . . 11-17 diags . . . . . . . . . . . . . . . . . . . . . . . . .11-18 mtest . . . . . . . . . . . . . . . . . . . . . . . .11-18 um. . . . . . . . . . . . . . . . . . . . . . . . . . .11-18 Other Commands. . . . . . . . . . . . . . . . . 11-18 autoscr . . . . . . . . . . . . . . . . . . . . . . .11-18 base . . . . . . . . .
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Figures Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Figure 1-2: PmPPC7448 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Figure 2-1: Component Map, Top (Rev. 06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2-2: Component Map, Bottom (Rev. 06). . . . . . . . . . . . . . . . . . . . . . .
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Tables Table 1-1: Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Table 1-2: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Table 1-3: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . .
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Registers Register 3-1: MPC7448 Hardware Implementation Dependent, HID0 . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Register 3-2: MPC7448 Hardware Implementation Dependent, HID1 . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Register 3-3: CPU Machine State Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Register 3-4: L2 Cache Control Register (L2CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section 1 Overview The Emerson PmPPC7448 module is a Processor PCI Mezzanine Card (PPMC). It is based on the Freescale® Semiconductor PowerPC™ MPC7448 central processor unit and provides additional processing power for the baseboard, which must be compatible with PPMC architecture. The PmPPC7448 module supports various memory configurations, programmable user Flash memory, a PCI bridge/controller, three Ethernet interfaces, two serial ports, as well as a real-time clock, and EEPROM.
Overview: Components and Features Note: GbE ports (0 and 1) are routed through the PHYs directly to connector P14. Therefore, magnetics are required on the Rear Transition Module (RTM) or baseboard. CPLD: The PmPPC7448 uses a Complex Programmable Logic Device (CPLD) to implement various memory-mapped registers and to control access to the Flash, ROM socket, and enumeration of Monarch/non-Monarch systems. RTC: The real-time clock is an ST®Microelectronics M41T00 Serial Access Timekeeper®.
Overview: Functional Overview FUNCTIONAL OVERVIEW The following block diagram provides a functional overview for the PmPPC7448: Figure 1-1: General System Block Diagram Mini-USB P1 Front Panel Mini-USB P2 DMC Connector MPX Bus up to 166 MHz Flash 32/64 MB Port 2 (portdbg) 10/100 PHY MII Device Bus Mini USB Connector 10/100 Magnetics COP Debug Development Mezzanine Card (DMC) Motorola MPC7448 Microprocessor 512 K Socketed Flash Jumpers Marvell MV64460 System Controller MPP Bits LEDs (4) Dev
Overview: Physical Memory Map PHYSICAL MEMORY MAP Fig.
Overview: Physical Memory Map Table 1-1 summarizes the physical addresses for the PmPPC7448 and provides a reference to more detailed information: Table 1-1: Address Summary Hex Physical Address: Access Mode: Description: See Page: FF80,0000 R/W Boot Mirror – – FF80,0000 R/W Boot Mirror F854,0000 – Reserved – MV64460 SRAM 5-3 F850,0000 F830,0000 – Reserved – F820,E000 R/W PCI Reset Out Enable register 7-2 F820,D000 W DMC LED register 10-10 F820,C000 R Board Configuration re
Overview: Additional Information ADDITIONAL INFORMATION This section lists the PmPPC7448 hardware regulatory certifications and briefly discusses the terminology and notation conventions used in this manual. It also lists general technical references. Mean time between failures (MTBF) has been calculated at 309,632 hours using Telcordia Issue 1 Method I Case 3.
Overview: Additional Information Type: EMC Specification: FCC Part 15, Class B – Title 47, Code of Federal Regulations, Radio Frequency Devices ICES 003, Class B – Industry Canada Interference-causing Equipment Standard for Digital Apparatus, Radiated and Conducted Emissions NEBS: Telcordia GR-1089 level 3 – Emissions and Immunity (circuit pack level testing only) AS/NZS 3548 003, Class A – Standard for radiated and conducted emissions for Australia and New Zealand EN55022, Class B – Information Technolo
Overview: Additional Information RoHS Compliance The PmPPC7448 is compliant with the European Union’s RoHS (Restriction of Use of Hazardous Substances) directive created to limit harm to the environment and human health by restricting the use of harmful substances in electrical and electronic equipment.
Overview: Additional Information Device / Interface: Ethernet Document: 3 (continued) KSZ8721CL 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver Data Sheet (Micrel® Inc., Rev. 1.2, M9999-041405 April 2005) http://www.micrel.com BCM5461S 10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet (Broadcom® Corporation, 5461S-DS05-R 09/02/04) http://www.broadcom.
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Section 2 Setup This chapter describes the physical layout of the boards, the setup process, and how to check for proper operation once the boards have been installed. This chapter also includes troubleshooting, service, and warranty information. ELECTROSTATIC DISCHARGE Before you begin the setup process, please remember that electrostatic discharge (ESD) can easily damage the components on the PmPPC7448 hardware.
Setup: PmPPC7448 Circuit Board The following figures show the component maps for the PmPPC7448 circuit board. Figure 2-1: Component Map, Top (Rev.
Setup: PmPPC7448 Circuit Board R123 R122 CR11 R526 R527 CR10 R132 R131 C191 R351 R350 C195 RN170RN167 R49 R394 Y2 R433 R290 R422 R425 R442 R474 R436 R426 R481 R430 C297 R435 R434 U35 C277 R452 R390 C239 R395 R407 R415 R414 RN178 R419 R502 C278 CR24 R456 10006757-02 R444 U29 R443 R495 R431 C334 R446 C243 RN172 R392 R391 RN174 RN173 R570 R569 R571 R572 R574 R573 R575 R576 R440 R447 U37 U28 R408 R416 R421 R420 C254 C259 R469 R423 R428 C258 R427 C264 C269 R432 R453 C270
Setup: PmPPC7448 Circuit Board Connectors The PmPPC7448 has the following connectors: P1: This mini-USB (universal serial bus) is the connection to the front panel 10/100 PHY Ethernet (port 2). Refer to Table 6-2 for the pin assignments. P2: P2 is a mini-USB connector for the front panel serial port. Refer to Table 8-2 for the pin assignments. P3: This is an 80-pin PCB-to-PCB male connector on the bottom side of the PmPPC7448.
Setup: PmPPC7448 Circuit Board LEDs The PmPPC7448 has fifteen green light-emitting diodes (LEDs) on the back side of the board (see Fig. 2-3).
Setup: PmPPC7448 Circuit Board Front Panel The PmPPC7448 has a single-wide PPMC front panel with an Electromagnetic Interference (EMI) gasket. Note: The electromagnetic compatibility (EMC) tests used a PmPPC7448 model that includes a front panel assembly from Emerson.
Setup: PmPPC7448 Circuit Board Reset The reset signals are routed to the CPLD, unless stated otherwise. See Chapter 7 for the reset registers. The following sources can reset the PmPPC7448: Power-on: This causes a hard reset to the entire board, including the PCI interfaces. Front panel: This reset switch is accessible through a small hole in the front panel and causes a hard reset to the entire board, including the PCI interfaces. Caution: Use minimal force when pressing the front panel reset switch.
Setup: PmPPC7448 Setup Figure 2-5: Reset Diagram DEBUG_HRESET DEBUG_SRESET DEBUG_TRST DMC_PD P11/P12 Development Mezzanine Card ENET_RST* DMC_BOOT_SRC PMC_CPLD_PCI_REQ64* PMC_CPLD_PCI_DEVSEL* PMC_CPLD_PCI_STOP* PMC_CPLD_PCI_TRDY* Ethernet RGMII (port0) Ethernet MII (portdbg) Ethernet RGMII (port1) MPC7448_HRESET* MPC7448_SRESET* MPC7448 MPC7448_TRST* PMC_CPLD_PCI_RST* PMC_RESET_OUT* CPLD CPLD_MV_64EN* PER_AD(31:0)* MV_SYSRST* MV_INIT_ACT POR_RST* MV_WDE FLASH_RP* Voltage Monitor MV6446
Setup: PmPPC7448 Setup Caution: Do not install the board in a rack or remove the board from a rack while power is applied, at risk of damage to the board. ! Power Requirements Be sure your power supply is sufficient for the PmPPC7448 circuit board. Standard power is 3.3 volts, however a dual power supply option is available. Table 2-2 lists the board’s specific power requirements. Table 2-2: Power Requirements Voltage: Range: Current (typical): +3.3 V +/- 5% 5.
Setup: PmPPC7448 Setup Installing the Module Most PPMC-compatible baseboards have two sets of four connectors (J11, J12, J13, J14 and J21, J22, J23, J24), as defined by the PMC standard P1386.1. This allows the PmPPC7448 to be installed in either PPMC slot. Fig. 2-6 shows the location of these connectors and the location of the PmPPC7448 modules on the baseboard.
Setup: Troubleshooting 3 Align the P11 and P12 connectors and gently press the module into place until firmly mated. Caution: To avoid damaging the module and/or baseboard, do not force the module onto the baseboard. ! Figure 2-7: Installing the Module P14 P13 P12 P11 J14 J13 J12 J11 PMC1 J22 1 J2 Serial Reset PmPPC7448 J24 3 J2 PMC2 Tighten these two screws first. 4 Using four M2.5x5 mm panhead screws (Emerson part #10006275-00), secure the PmPPC7448 module from the bottom of the baseboard.
Setup: Troubleshooting ❐ Be sure the PmPPC7448 module is seated firmly on the PPMC host and that the PPMC host is seated firmly in the card cage. ❐ Verify the boot jumper setting if the DMC is installed (see page 10-9). ❐ Be sure the system is not overheating. ❐ Check the cables and connectors to be certain they are secure. ❐ Check your power supply for proper DC voltages. If possible, use an oscilloscope to look for excessive power supply ripple or noise (over 50 mVpp below 10 MHz).
Setup: Troubleshooting Figure 2-8: Serial Number and Product ID on Bottom Side 684- XXXXXX 00000000-00 D PRODUCTOF XXXXX Serial Number MMYY X Product ID Product Repair If you plan to return the board to Emerson Network Power for service, visit http://www.emersonembeddedcomputing.com/contact/productrepair.html on the internet or send e-mail to serviceinfo@artesyncp.com to obtain a Return Merchandise Authorization (RMA) number.
Setup: Troubleshooting Emerson Network Power, Embedded Computing Test and Repair Services Department 8310 Excelsior Drive Madison, WI 53717 RMA #____________ Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA number.
Section 3 Central Processing Unit This chapter is an overview of the processor logic on the PmPPC7448. It includes information on the CPU, exception handling, and cache memory. The PmPPC7448 utilizes the Freescale MPC7448 RISC microprocessor, for more detailed information reference the Freescale Semiconductor MPC7450 RISC Microprocessor Family User’s Manual. The following table outlines some of the key features for the MPC7448 CPU.
Central Processing Unit: Processor Reset Figure 3-1: MPC7448 Block Diagram Instruction Unit Completion Unit Vector Permute Unit Branch Processing Unit Instruction MMU Tags I 32-KB Cache Data MMU Tags D32-KB Cache Instruction Queue VR Issue GPR Issue FPR Issue Integer Unit 2 Integer Unit 1 (3) Floating Point Unit Vector Integer Unit 2 Load/Store Unit Vector Integer Unit 1 Memory Subsystem Vector FPU L1 Service Queues 1 MB L2 Cache Controller System Bus Interface PROCESSOR RESET Circui
Central Processing Unit: Processor Initialization Hardware Implementation Dependent 0 Register The Hardware Implementation Dependent 0 (HID0) register contains bits for CPU-specific features. Most of these bits are cleared on initial power-up of the PmPPC7448. Please refer to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of the HIDx registers.
Central Processing Unit: Processor Initialization XAE: Extended Addressing Enabled 0 Disabled; the 4 MSB bits of the 36-bit physical address are cleared, 32-bit physical address is used 1 Enabled; the 32-bit effective address is translated to a 36-bit physical address NHR: Not Hard Reset (software use only) 0 A hard reset occurred if software had previously set this bit 1 A hard reset has not occurred ICE/DCE: Instruction and Data Cache Enable 0 Instruction and data caches are neither accessed nor updated
Central Processing Unit: Processor Initialization BHT: Branch History Table Enable 0 Disabled 1 Allows use of dynamic prediction 2048-entry BHT NOPDST: No-op the dst, dstt, dstst, and dststt instructions 0 Instructions enabled 1 Instructions are no-oped globally and all previously executed dst streams are cancelled NOPTI: No-op the dcbt/dcbtst instructions 0 Instructions enabled 1 Instructions are no-oped globally Hardware Implementation Dependent 1 Register One of the functions of the Hardware Implement
Central Processing Unit: Exception Handling HRESET*: HID1[ECLK]: HID1[BCLK]: CLK_OUT: Negated 0 1 Bus/2 Negated 1 0 Core Negated 1 1 Core/2 PAR: Disable Precharge for ARTRY*, SHD0*, and SHD1* pins 0 Signals driven high when negated 1 Signals not driven high when negated DFS4: Dynamic Frequency Switching divide-by-four mode 0 Disabled 1 Enabled DFS2: Dynamic Frequency Switching divide-by-two mode 0 Disabled 1 Enabled PC5: PLL Configuration bit 5 (PLL CFG[5]), read only PC0: PLL Configuratio
Central Processing Unit: Exception Handling Instruction Fetch: Synchronous precise exceptions are taken in strict program order. Instruction Dispatch/Execution: Imprecise exceptions are delayed until higher priority exceptions are taken. Post-Instruction Execution: Maskable asynchronous exceptions are delayed until higher priority exceptions are taken.
Central Processing Unit: Exception Processing Priority: Exception: Notes: (continued) 9 Data Storage (DSI) Due to eciwx, ecowx with EAR(E)=0 (DSISR[11]) 10 Data Storage (DSI) Due to lwarx/stwcx 11 Data Storage (DSI) Due to BAT/page protection violation (DSISR[4]) or lwarx/stwcx to BAT entry 12 Data Storage (DSI) Due to any access except cache operations to SR[T]=1 (DSISR[5]) or T=0->T=1 crossing 13 Data TLB miss on store Due to store miss in DTLB with HID0[STEN]=1 14 Data TLB miss-on-lo
Central Processing Unit: Exception Processing Register 3-3: CPU Machine State Register (MSR) 0 5 6 reserved 7 12 VEC reserved 13 14 15 PO W R ILE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EE PR FP ME FE0 SE BE FE1 R IP IR DR R PM M RI LE VEC: AltiVec vector unit available 0 Prevents AltiVec instructions dispatch 1 Executes AltiVec instructions POW: Power Management enable—setting this bit enables the programmable power management modes: nap, doze, or sl
Central Processing Unit: Cache Memory FE0: FE1: FP Exception Mode: (continued) 1 0 Imprecise recoverable 1 1 Precise SE: Single-Step Trace enable 0 Executes instructions normally 1 Single-step trace exception generated BE: Branch Trace enable 0 Executes instructions normally 1 Branch type trace exception generated IP: Exception Prefix 0 Places the exception vector table at the base of RAM (0000,000016) 1 Places the exception vector table at the base of ROM (FFF0,000016) IR/DR: Instruction and Dat
Central Processing Unit: Cache Memory L2 Cache The internal 1 megabyte L2 cache is an eight-way set associative instruction and data cache with ECC capability. The L2 cache is fully pipelined to provide 32 bytes per clock to the L1 caches. The L2 Cache Control register (L2CR) configures and operates the L2 cache. The L2CR is read/write and contents are cleared during power-on reset.
Central Processing Unit: Cache Memory L2HWF: L2 Hardware Flush 0 Flush disabled 1 Flush enabled LVRAME: LVRAM enable 0 LVRAM mode disabled 1 LVRAM mode enabled LVRAMM: LVRAM mode (read-only) 000 Reserved if LVRAM mode is enabled 001 Mode 1 010 Mode 2 011 Mode 3 100 Mode 4 101 Mode 5 110 Mode 6 111 Mode 7 The L2 cache is cleared following a power-on or hard reset. Before enabling the L2 cache, configuration parameters must be set in the L2CR and the L2 tags must be globally invalidated.
Section 4 On-Card Memory Configuration The PmPPC7448 includes the following memory devices: • Up to 64 megabytes of Flash memory • Synchronous DRAM (SDRAM) configurations up to 2 gigabytes • Eight kilobytes of non-volatile memory BOOT MEMORY CONFIGURATION The PmPPC7448 boot default is the on-board Flash which occupies the physical address space beginning at E800,000016.
On-Card Memory Configuration: On-Card SDRAM If booting from user Flash, the MV64460 controller initially maps one megabyte addressing of Flash memory (beginning at FF80,000016) at the top of the address space. When an 8-bit Flash device is installed in the PLCC socket, it always appears at F800,000016 (and is mirrored at FF80,000016 when the socket is the boot device). Caution: When removing socketed PLCC devices, always use an extraction tool designed specifically for that task.
On-Card Memory Configuration: NVRAM Allocation Table 4-3: NVRAM Memory Map Address Offset (hex): Window Size (bytes): Name: 0x1E14-0x1FFF Reserved 492 0x1E00-0x1E13 Test software flags 20 0x1DDC-0x1DFF Boot verify parameters 24 0x1DD8-0x1DDB Power-on self-test (POST) diagnostic results 4 0x1800-0x1DD7 Monitor configuration parameters 1508 0x1600-0x17FF Operating system 512 0x0000-0x15FF User defined 5632 10006757-02 PmPPC7448 User’s Manual 4-3
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Section 5 System Controller The Marvell MV64460 is an integrated system controller with a PCI interface and communication ports for high performance embedded control applications.
System Controller: CPU Interface CPU INTERFACE CPU interface features include: • 32-bit address and 64-bit data buses • Support for Symmetrical Multi-Processing (SMP) in both 60x and MPX bus modes • Support for up to four slave devices on the same 60x bus • 166 MHz CPU bus frequency • CPU address remapping to the PCI • Support for access, write, and caching protection to a configurable address range • Support for up to 16 pipelined address transactions CPU Interface Registers The PmPPC7448 monitor config
System Controller: Device Controller Interface • Up to 166 MHz clock frequency • Support for 256 megabytes to 2 gigabytes • Up to two gigabytes address space per DRAM bank • Supports both physical bank (M_CS[3:0]) and virtual bank (M_BA[1:0]) interleaving The MV64460 has a number of SDRAM registers. Refer to the Marvell web site for available documentation. Internal SRAM The MV64460 integrated SRAM occupies two megabits of space for general purpose memory.
System Controller: Internal (IDMA) Controller Device Control Registers Each bank has its own parameters register and can be programmed to 8, 16, or 32-bits wide. The device interface consists of 128 bytes of write buffer and 128 bytes of read buffer. INTERNAL (IDMA) CONTROLLER Each of the four DMA engines can move data between any source and any destination, such as the SDRAM, device, PCI_0, or CPU bus.
System Controller: PCI Interface PCI Configuration Space The PCI slave supports Type 00 configuration space header as defined in the PCI specification. The MV64460 is a multi-function device and the header is implemented in all five functions. The PCI interface implements the configuration header and this space is accessible from the CPU or PCI bus. PCI Subsystem Device and Vendor ID Assignment The PmPPC7448 has been assigned the following PCI identification number.
System Controller: PCI Interface Figure 5-3: Example PCI0 Address Map, Monarch CPU PCI0 I/O PCI0 Memory B400,0000 B000,0000 B000,0000 8000,0000 8000,0000 PCI Memory Space Max SDRAM Size SDRAM Size 0400,0000 0000,0000 8000,0000 0000,0000 0000,0000 0000,0000 Figure 5-4: Example PCI0 Address Map, Non-Monarch (Default) PCI0 I/O PCI0 Memory CPU B400,0000 B000,0000 B000,0000 8000,0000 PCI Memory Space Max SDRAM Size SDRAM Size 0400,0000 0000,0000 5-6 PmPPC7448 User’s Manual 8000,0000
System Controller: PCI Bus Control Signals PCI Interface Registers PCI0 and PCI1 contain the same set of internal registers, but are located at different offsets. A CPU access to the MV64460 PCIx Configuration register is performed via the PCIx Configuration Address and Data registers. Only PCI0 is functional on the PmPPC7448.
System Controller: PCI Bus Control Signals C/BE[7:4]*: BUS COMMAND and BYTE ENABLES During the address phase, the actual bus command is transferred, otherwise these bits are reserved. During a data phase the lines are used as byte enables. CLK: CLOCK This input signal to PPMC modules provides timing for PCI transactions. DEVSEL*: DEVICE SELECT This sustained three-state signal indicates when a device on the bus has been selected as the target of the current access.
System Controller: PCI Bus Control Signals PRESENT*: PRESENT When grounded, this input signal indicates to a carrier that a PPMC module is installed. RESET_OUT*: RESET OUTPUT This output signal may be used to support a reset button or other reset source on the PPMC module. It is an open drain output from the PPMC module that becomes an input to the reset logic on the carrier card. To avoid reset loops, do not use RST* to generate RESET_OUT*.
System Controller: PMC Connector Pinouts PMC CONNECTOR PINOUTS Each connector has 64 pins (see Fig. 5-6 on page 5-12). P11 and P12 Pin Assignments P11 and P12 support the 32-bit PCI bus connectors (see Table 5-1). Fig. 5-5 illustrates the MV64460 JTAG signals routed from connector P12.
System Controller: PMC Connector Pinouts Pin: P11 Signal: P11 Signal: Pin: P11 Signal: P12 Signal: 37 DEVSEL* GND 38 +5 V STOP* 39 GND_PCIXCAP PERR* 40 Not connected GND 41 Not connected +3.3 V 42 Not connected SERR* 43 PAR C/BE1* 44 GND GND 45 V(I/O) AD14 46 AD15 AD13 47 AD12 M66EN 48 AD11 AD10 49 AD9 AD8 50 +5 V +3.3 V 51 GND AD7 52 C/BE0* Not connected 53 AD6 +3.
System Controller: PMC Connector Pinouts Pin: P13 Signal: P14 Signal: Pin: P13 Signal: P14 Signal: 35 AD47 Not connected 36 AD46 Not connected 37 AD45 Not connected 38 GND Not connected 39 V(I/O) Not connected 40 AD44 Not connected 41 AD43 Not connected 42 AD42 Not connected 43 AD41 Not connected 44 GND Not connected 45 GND Not connected 46 AD40 Not connected 47 AD39 Not connected 48 AD38 Not connected 49 AD37 GPIO0 50 GND GPIO1 51 GND GPIO2 52 AD3
System Controller: Doorbell Registers DOORBELL REGISTERS The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts on both the PCI and CPU buses. There are two types of doorbell registers: Outbound: These are set by the MV64460’s local CPU to request an interrupt service on the PCI bus. Inbound: These are set by an external PCI agent to request interrupt service from the local CPU.
System Controller: 66 MHz Bus Operation 66 MHZ BUS OPERATION Conventional PCI: In order for the PCI bus to operate at 66 MHz, all devices on the bus must be capable of that speed. When the M66EN signal (connector P12 pin 47) is high for a particular PCI device, it indicates that the device can operate at 66 MHz. For 33 MHz modules, M66EN is grounded, so the signal will be high only when all devices on the PCI bus are capable of operating at 66 MHz.
Section 6 Ethernet Interface The PmPPC7448 provides three independent full duplex Ethernet ports. Using the Marvell MV64460, these ports are configured to one 10/100 Mbps Media Independent Interface (MII) and two 10/100/1000 Mbps Gigabit MII (GMII). The two gigabit Ethernet ports (ports 0 and 1) are routed through PMC connector P14. The 10/100 Mbps Ethernet port (port 2) is routed to the front panel mini-USB connector.
Ethernet Interface: Ethernet Address ETHERNET ADDRESS The Ethernet address for your board is a unique identifier on a network and must not be altered. The address consists of 48 (MAC[47:0]) bits divided into two equal parts. The upper 24 bits define a unique identifier that has been assigned to Emerson Network Power by IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
Ethernet Interface: Ethernet Connection (P1) Figure 6-1: Front Panel Ethernet Connector (P1) Pin 1 Table 6-2: Front Panel Ethernet Pin Assignments (P1) Pin: Signal: Pin: Signal: 1 Ethernet 1 transmit positive 2 Ethernet 1 transmit negative 3 Ethernet 1 receive positive 4 Ethernet 1 receive negative 5 Signal ground 6-9 Connector housing ground Figure 6-2: Ethernet Cable Assembly ETHERNET Mini-B USB RJ45 Connector Caution: The Mini-USB cable connection to P1 does not have a locking mech
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Section 7 CPLD This chapter lists the registers implemented by the complex programmable logic device (CPLD). RESET REGISTERS The reset signals are routed to and distributed by the CPLD. To support this functionality, the CPLD includes two registers; one indicates the reason for the last reset, and the other forces one of several types of reset. Reset Event Register (RER) This read-only register contains the cause of the latest reset.
CPLD: Reset Registers Register 7-2: Reset Command Register (RCR) at 0xf820,1000 7 6 5 4 3 2 1 0 SCL SDA R I2C FR SR R HR SCL: Serial I2C Clock 1 Tri-states the PLD 0 Drives logic low SDA: Serial I2C Data/Address 1 Tri-states the PLD 0 Drives logic low R: Reserved (default is 00) I2C: I2C reset 1 Causes the I2C bus to be reset into a known state 0 No I2C reset (default) FR: Flash Reset command 1 Causes Flash to be reset 0 No Flash reset (default) SR: Soft Reset command 1 Causes a soft rese
CPLD: Interrupt Registers SW: Software PCI reset driven when on-board hard reset is caused by a write to the Reset Command register. 1 Enabled 0 Disabled WD: WatchDog PCI reset driven when on-board reset is caused by a timeout of the WatchDog timer. 1 Enabled 0 Disabled COPH: Hard RESET PCI reset driven when reset is caused by a COP HRESET. 1 Enabled 0 Disabled PCI0: PCI reset driven when on-board reset is caused by the assertion of PCI0 reset (PCI RESET).
CPLD: Interrupt Registers Interrupt Enable Register (IER) Register 7-4: PmPPC7448 Interrupt Enable Register (IER) at 0xf820,2000 7 6 5 4 3 2 Reserved 1 0 SR0EN PR0EN R: Reserved (default is 000) SR0EN: PCI0 SERR Enable interrupt routed from PCI0 SERR to MV64460 1 Enabled to generate an interrupt 0 Disabled (default) PR0EN: PCI0 PERR Enable interrupt routed from PCI0 PERR to MV64460 1 Enabled to generate an interrupt 0 Disabled (default) Interrupt Pending Register (IPR) This register allows so
CPLD: Product ID Register (PIR) PRODUCT ID REGISTER (PIR) This read-only register identifies the board as PmPPC7448. Register 7-6: PmPPC7448 Product ID Register (PIR) at 0xf820,4000 7 6 5 4 3 2 1 0 PIDR PIDR: Product Identification register 0516 PmPPC7448 EREADY REGISTER (ERDY) The PmPPC7448 provides a register for status and control of enumeration. In a Monarch system, the register is readable to indicate that other boards in the system are ready for enumeration.
CPLD: Board Configuration Registers Hardware Version Register (HVR) Register 7-8: Hardware Version Register (HVR) at 0xf820,7000 7 6 5 4 3 2 1 0 HVR HVR: Hardware Version number This is hard coded in the PLD and changes with every major PCB version. Version starts at 0016. PLD Version Register (PVR) Register 7-9: PLD Version Register (PVR) at 0xf820,8000 7 6 5 4 3 2 1 0 PVR PVR: PLD code Version number This is hard coded in the PLD and changes with every major code change.
CPLD: Board Configuration Registers DMC: Development Mezzanine Card installation option 1 DMC is installed 0 DMC is not installed Register 7-11: PmPPC7448 Board Configuration 1 (BCR1) at 0xf820,a000 7 6 5 4 Reserved 3 2 Boot DMC 1 0 Reserved R: Reserved, default is 0 Boot DMC: Boot from Development Mezzanine Card ROM or PPMC Flash 1 Boot from DMC PLCC ROM 0 Boot from PPMC Flash (default) Register 7-12: PmPPC7448 Board Configuration 0 (BCR0) at 0xf820,9000 7 6 5 4 SysCLK 3 2 1 0 Reser
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Section 8 Serial Input/Output The PmPPC7448 has two EIA-232 serial ports. These ports operate between 9600 and 115,200 baud. Software selects the speed and these settings are stored in non-volatile memory. Serial port one is always routed to the Development Mezzanine Card (DMC) serial connector as 12 volts; build options include connections to the front panel serial connector, or the P14 connector. When routed to P14, there is the option of either EIA-232 or TTL signaling levels.
Serial Input/Output: I2C Interface BRGx Tuning Register A baud tuning mechanism adjusts the generated clock rate to the receive clock rate. When baud tuning is enabled, the baud tuning mechanism monitors for a start bit (for example high-to-low transition). Once the start bit is found, the baud tuning machine measures the bit length by counting up until the next Low-to-High transition.
Serial Input/Output: I/O Connection Table 8-2: Front Panel Serial Port Pin Assignments (P2) Pin: Signal: Pin: 1 Not connected 2 1 3 Transmit (Tx) Data Output, EIA-232 (alternate is Rx)1 4 Not connected 5 Ground 6-9 Connector housing ground 1 Signal: Receive (Rx) Data Input, 1 EIA-232 (alternate is Tx) 1.Signals (pins 2 and 3) can be switched as a factory build option.
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Section 9 Real-Time Clock The standard real-time clock (RTC) for the PmPPC7448 is provided by an M41T00 device from STMicroelectronics. This device has an integrated year-2000-compatible RTC, power sense circuitry, and uses eight bytes of non-volatile RAM for the clock/calendar function. The M41T00 is powered from the +3.3 volt rail during normal operation. Caution: A supercapacitor on the PmPPC7448 provides backup operation in the event of a power failure.
Real-Time Clock: Clock Operation 1 Seconds register 2 Minutes register 3 Century/Hours register 4 Day register 5 Date register 6 Month register 7 Years register 8 Control register The M41T00 clock continually monitors the supply voltage (Vcc) for an out of tolerance condition.
Real-Time Clock: Clock Operation ST: Stop bit 1=Stops the oscillator 0=Restarts the oscillator within one second CEB: Century Enable Bit 1=Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century 0=CB will not toggle CB: Century Bit Day: Day of the week Date: Day of the month OUT: Output level 1=Default at initial power-up 0=FT/OUT (pin 7) driven low when FT is also zero FT: Frequency Test bit 1=When oscillator is running at 32,768 Hz, the FT/OUT pin will toggle at 512 Hz 0=The FT/
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Section 10 Development Mezzanine Card The Development Mezzanine Card (DMC) is an optional plug-on card mounted on the back of the PmPPC7448 board to expedite product development. This chapter describes the physical layout of the DMC, the setup process, and how to check for proper operation once the board has been installed.
Development Mezzanine Card: DMC Circuit Board Figure 10-1: DMC Component Maps, Top and Bottom (Revision 01) P2 CPLD JTAG R3 U2 CR4 R6 R5 R4 CR2 CR1 CR3 P4 2 R COPYRIGHT 2002 R29 R28 R7 R38 R36 10002939-00 TECHNOLOGIES P7 R13 R14 R15 R16 R1 R2 2 P3 COP/JTAG R9 R10 R11 R12 1 1 R32 C11 R20 C3 C4 C1 R19 C5 R33 R34 R17 R35 C10 R37 C13 C12 R31 U5 9 1 C7 R21 R24 U3 C9 R30 C6 JP1 R18 R25 R26 R23 10 2 SPARE JP4 JP3 BOOT ENET F1 PORT 1 C2 9 10 PORT 0 C8
Development Mezzanine Card: Connectors It is useful to have these numbers available when you contact Technical Support or Test and Repair Services at Emerson Network Power. CONNECTORS The DMC has the following connectors: P1: This 80-pin PCB-to-PCB female connector on the bottom side of the DMC routes memory, CPLD, and CPU signals from the PmPPC7448 to the DMC for development use. See Table 102 for the pin assignments. P2: This mini-USB 9-pin connector provides the EIA-232 interface.
Development Mezzanine Card: Connectors Pin: Signal: Pin: Signal: 19 LA7 20 LA6 21 LA5 22 LA4 23 LA3 24 LA2 25 BADDR2 26 BADDR1 27 BADDR0 28 AD7 29 AD6 30 AD5 31 AD4 32 AD3 33 AD2 34 AD1 35 AD0 36 FILT_TX 37 FILT_RX 38 GND 39 CPU_VIO (DMC JTAG) 40 3.3 V 41 3.
Development Mezzanine Card: Connectors DMC_OE*: Output Enable for DMC Flash is an input to DMC. WE0*: Write Enable for DMC Flash is an input to DMC. LA(17:2): Latched Address for DMC Flash is an input to DMC. BADDR(2:0): Burst Address for DMC Flash is an input to DMC. AD(7:0): Multiplexed Address/Data bus for DMC Flash data is an output from DMC. FILT_TX: Serial IO Transmit (console port) is an input to DMC. FILT_RX: Serial IO Receive (console port) is an output from DMC.
Development Mezzanine Card: Connectors P2 EIA-232 Interface Use the standard serial cable, Emerson part number C0007662-00, to access connector P2. Pin assignments are listed in Table 10-3.
Development Mezzanine Card: PmPPC7448 to DMC JTAG PMPPC7448 TO DMC JTAG Figure 10-4: PmPPC7448 to DMC JTAG Block Diagram Development Mezzanine Card (DMC) TDI MPC7448_TDO MPC7448_TDI COP Debug TDO 2 TDI TRST* TCK TMS MPC7448_TCK MPC7448_TMS TCK TMS TDO DEBUG_SRESET* DEBUG_HRESET* MPC7448_CKSTP_OUT* DEBUG_HRESET_B* MPC7448_SRESET_OUT* MPC7448_HRESET_OUT* MPC7448_TRST_OUT* DEBUG_TRST* DEBUG_TRST_B* SRESET* MPC7448_SRESET* Convert 3.3 V 1.8V DEBUG_SRESET_B* HRESET* Convert 1.8 V 3.
Development Mezzanine Card: PmPPC7448 to DMC JTAG Table 10-4: DMC P3 Pin Assignments Pin: Signal: Pin: Signal: 1 MPC7448_TDO 2 Not connected 3 MPC7448_TDI 4 DEBUG_TRST* 5 Not connected 6 JTAG_PWR (1.8 V) Not connected 7 MPC7448_TCK 8 9 MPC7448_TMS 10 Not connected 11 DEBUG_SRESET* 12 13 DEBUG_HRESET* 14 GND 22 Key 15 MPC7448CKSTP_OUT* 16 GND 2. Pin 14 is not installed.
Development Mezzanine Card: DMC Jumpers (JP1) Table 10-5: DMC P4 Pin Assignments Pin: Signal: Pin: Signal: 1 CPLD_TCK 2 GND 3 CPLD_TDO 4 Fused 3.3 V 5 CPLD_TMS 6 Not connected 7 Not connected 8 Not connected 9 CPLD_TDI 10 GND CPLD_TCK: Test Clock Input—this is the clock input to the boundary scan test (BST) circuitry. Some operations occur at the rising edge, while others occur at the falling edge.
Development Mezzanine Card: Debug/Status LEDs JP3: This is a user-defined jumper. JP4: JP4 is the MV64460 serial ROM configuration jumper. If JP4 is installed, the MV64460 will not try to configure from the serial ROM. Jumper Setting Register These read-only bits may be read by software at location F820,6000 to determine the current DMC jumper (JP1) settings.
Development Mezzanine Card: DMC Setup DMC SETUP You need the following items to set up and check the operation of the Emerson DMC. ❐ A compatible PPMC board, such as the Emerson PmPPC7448 ❐ Card cage and power supply ❐ CRT terminal When you unpack the board, save the antistatic bag and box for future shipping or storage. Caution: Do not install the board in a rack or remove the board from a rack while power is applied, at risk of damage to the board.
Development Mezzanine Card: DMC Setup Figure 10-8: DMC Location on PmPPC7448 R3 CR4 R4 CR2 R5 R6 CR1 CR3 10002939-00 10006757-02 R1 R2 R29 R28 R7 R38 R36 R13 R14 R15 R16 C9 2 R32 C11 R20 R9 R10 R11 R12 1 P3 COP/JTAG 2 U2 R19 C5 R17 R34 R33 R18 C12 R31 C3 C4 C1 1 CPLD JTAG U5 R27 C6 9 1 R35 C10 R37 C13 R25 R24 R26 R23 2 SPARE JP4 JP3 BOOT ENET PmPPC7448 User’s Manual PORT 1 U3 P4 10-12 10 JP1 9 10 PORT 0 C2 F1 P6 RJ45 Mini-USB R30 P5 RJ45 C7 R21
Development Mezzanine Card: Troubleshooting TROUBLESHOOTING In case of difficulty, use this checklist: ❐ Be sure the PmPPC7448 module is seated firmly on the baseboard and that the baseboard is seated firmly in the card cage. ❐ Verify the boot jumper settings (see Fig. 10-7). ❐ If booting from EEPROM (U2), make sure the device is properly oriented in the socket. ❐ Be sure the system is not overheating. ❐ Check your power supply for proper DC voltages.
Development Mezzanine Card: Troubleshooting Emerson Network Power Test and Repair Services Department 8310 Excelsior Drive Madison, WI 53717 RMA #____________ Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA number.
Section 11 Monitor The PmPPC7448 monitor is based on the Universal Boot (U-Boot) program, available under the GNU General Public License (GPL). For instructions on how to obtain the source code for this GPL program, please visit http://www.emersonembeddedcomputing.com, send an email to support@artesyncp.com, or call Emerson at 1-800-327-1251. This chapter describes the monitor’s basic features, operation, and configuration sequences.
Monitor: Basic Operation Figure 11-1: Example Monitor Start-up Display U-Boot 0.4.0 (Jul 30 2007 - 10:57:37)1.8 Hardware initialization CPU: MPC7448 v2.1 @ 1399.999 MHz Board: PM/PPC-7448 BusHz: 133333333 I2C: ready DRAM: DDR SDRAM in slot 0 DDR SDRAM in slot 1 ECC (Clearing..) 2048 MB FLASH: [32MB@e8000000] 32 MB PCI: Bus Host Waiting For EREADY ('q' to exit w/o enum).
Monitor: Basic Operation Figure 11-2: Power-up/Reset Sequence Flowchart RESET Initialize HID0 Initialize MSR Enable icache LED 0001 Initialize flash Initialize malloc area Relocate the base of the MV64460 internal registers Initialize the U-Boot environment Initialize PCI 7448 floating point register initialization Init. serial port per baudrate environment var.
Monitor: Monitor Recovery and Updates POST Diagnostic Results The PmPPC7448 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in I2C NVRAM at the offset 0x1DD8-0x1DDB. Each bit indicates the results of a specific test, therefore this field can store the results of up to 32 diagnostic tests. Table 11-1 assigns the bits to specific tests.
Monitor: Monitor Recovery and Updates 1 Issue the following command, where serial_number is the board’s serial number, at the monitor prompt: PM/PPC-7448 (1.8) => moninit serial_number If the monitor recovers, skip to step 5. If moninit() fails, continue on to the next step. 2 Perform the following tasks: Unprotect the Flash: PM/PPC-7448 (1.8) => protect off all Erase the monitor region of soldered Flash: PM/PPC-7448 (1.
Monitor: Monitor Recovery and Updates PM/PPC-7448 (1.8) => moninit serial_number 100000 If moninit( ) fails, burn the new monitor to a ROM and follow the recovery steps in “Recovering the Monitor” on page 11-4. Restoring the PmPPC7448 Monitor Using the KatanaQP To restore the PmPPC7448 monitor image from the soldered flash, the monitor image can be copied to the KatanaQP carrier’s RAM, to the soldered flash, and finally to the socket flash (EEPROM) via a PCI interface.
Monitor: Monitor Recovery and Updates KatanaQp(1.0.a) => protect off e8100000 e8a3ffff KatanaQp(1.0.a) => erase e8100000 e8a3ffff KatanaQp(1.0.a) => cp.b 90100000 e8100000 200000 6 From the KatanaQP console, compare the copied data to the original. KatanaQp(1.0.a) => cmp.b 90100000 e8100000 200000 7 Verify that the checksum is correct. KatanaQp(1.0.a) => imi e8100000 The PmPPC7448 monitor image has been successfully copied to the KatanaQP’s soldered flash.
Monitor: Accessing the Console Over Ethernet ACCESSING THE CONSOLE OVER ETHERNET To interact with the monitor command line over Ethernet, use the NetConsole feature built into the monitor and an appropriate client application. This feature sends and receives UDP packets to and from a designated host on the network.
Monitor: Boot Commands Command Syntax The monitor uses the following basic command syntax: • The command line accepts three different argument formats: string, numeric, and symbolic. All command arguments must be separated by spaces with the exception of argument flags, which are described below. • Monitor commands that expect numeric arguments assume a hexadecimal base. • All monitor commands are case sensitive. • Some commands accept flag arguments.
Monitor: Boot Commands bootelf The bootelf command boots from an ELF image in memory, where address is the load address of the ELF image. DEFINITION: bootelf [address] bootm The bootm command boots an application image stored in memory, passing any entered arguments to the called application. When booting a Linux kernel, arg can be the address of an initrd image. If addr is not specified, the environment variable loadaddr is used as the default.
Monitor: Memory Commands dhcp The dhcp command invokes a Dynamic Host Configuration Protocol (DHCP) client to obtain IP and boot parameters by sending out a DHCP request and waiting for a response from a server. DEFINITION: dhcp [load address] [bootfilename] rarpboot The rarpboot command boots an image via a network connection using the RARP/TFTP protocol. If loadaddress or bootfilename is not specified, the environment variables loadaddr and bootfile are used as the default.
Monitor: Memory Commands DEFINITION: cmp [.b, .w, .l] addr1 addr2 count cp The cp command copies count objects located at the source address to the target address. If the target address is located in the range of the Flash device, it will program the Flash with count objects from the source address. The cp command does not erase the Flash region prior to copying the data. The Flash region must be manually erased using the erase command prior to using the cp command. DEFINITION: cp [.b, .w, .
Monitor: Memory Commands mm The mm command modifies memory one object at a time. Once started, the command line prompts for a new value at the starting address. After a new value is entered, pressing ENTER auto-increments the address to the next location. Pressing ENTER without entering a new value leaves the original value for that address unchanged. To exit the mm command, enter a non-valid hexadecimal value (such as x) followed by ENTER. DEFINITION: mm [.b, .w, .
Monitor: Flash Commands 00080070: ffffffff ffffffff ffffffff ffffffff ................ FLASH COMMANDS The Flash commands affect the StrataFlash devices on the PmPPC7448 circuit board. There is one Flash bank on the PmPPC7448 board. The following Flash commands access the individual Flash bank as Flash bank 1. To access the individual sectors within each Flash bank, the sector numbers start at 0 and end at one less than the total number of sectors in the bank.
Monitor: EEPROM/I2C Commands protect The protect command enables or disables the Flash sector protection for the specified Flash sector. Protection is implemented using software only. The protection mechanism inside the physical Flash part is not being used. DEFINITION: Protect all of the Flash sectors in the address range from start to end. protect on start end Protect all of the sectors SF (first sector) to SL (last sector) in Flash bank # N.
Monitor: EEPROM/I2C Commands eeprom read devaddr addr off cnt eeprom write devaddr addr off cnt icrc32 The icrc32 computes a CRC32 checksum. DEFINITION: icrc32 chip address[.0, .1, .2] count iloop The iloop command reads in an infinite loop on the specified address range. DEFINITION: iloop chip address[.0, .1, .2] [# of objects] imd The imd command displays I2C memory. For example: imd 53 1800.2 100 displays 100 bytes from offset 0x1800 of I2C device 0x53 (right-shifted 7-bit address). The .
Monitor: Environment Parameter Commands ENVIRONMENT PARAMETER COMMANDS The monitor uses on-board, non-volatile memory for the storage of environment parameters. Environment parameters are stored as ASCII strings with the following format. = Some environment variables are used for board configuration and identification by the monitor. The environment parameter commands deal with the reading and writing of these parameters.
Monitor: Other Commands diags The diags command runs the Power-On Self-Test (POST). DEFINITION: diags mtest The mtest command performs a simple SDRAM read/write test. DEFINITION: mtest [start [end [pattern]]] um The um command is a destructive memory test. The test will repeat indefinitely unless the ‘q’ key is pressed. The test must complete its current testing cycle before acknowledging the request to quit. DEFINITION: um [.b, .w, .
Monitor: Other Commands DEFINITION: coninfo crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address. DEFINITION: crc32 address count date The date command will set or get the date and time, and reset the real-time clock (RTC) device. DEFINITION: Set the date and time. date [MMDDhhmm[[CC]YY][.ss]] Display the date and time. date Reset the RTC device. date reset echo The echo command echoes args to console. DEFINITION: echo [args..
Monitor: Other Commands help The help (or ?) command displays the online help. Without arguments, all commands are displayed with a short usage message for each. To obtain more detailed information for a specific command, enter the desired command as an argument. DEFINITION: help [command …] iminfo The iminfo command displays the header information for an application image that is loaded into memory at address addr.
Monitor: Other Commands moninit pci The pci command enumerates the PCI bus if the PmPPC7448 is the Monarch board. It displays enumeration information about each detected device. The pci command allows you to display values for and access the PCI Configuration Space. DEFINITION: Display a short or long list of PCI devices on the bus specified by bus. pci [bus] [long] Show the header of PCI device bus.device.function. pci header b.d.f Display the PCI configuration space (CFG).
Monitor: Environment Variables script The script command runs a list of monitor commands out of memory. The list is an ASCII string of commands separated by the ; character and terminated with the ;; characters.
