User’s Manual from Emerson Network Power ™ Embedded Computing Katana®752i: Intelligent CompactPCI Blade for cPSB April 2008
The information in this manual has been checked and is believed to be accurate and reliable. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others. Emerson.
Regulatory Agency Warnings & Notices The Emerson Katana752i meets the requirements set forth by the Federal Communications Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information is provided as required by this agency. This device complies with part 15 of the FCC Rules.
(continued) EC Declaration of Conformity According to EN 45014:1998 Manufacturer’s Name: Emerson Network Power Embedded Computing Manufacturer’s Address: 8310 Excelsior Drive Madison, Wisconsin 53717 Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC Directive and 1999/5/EC, RTTE Directive and their amending directives, Product: Real-Time Processing Blade Model Name/Number: Katana752i/10006008-xx has been designed and manufactured to the following specifi
Contents 1 Overview Components and Features . . . . . . . . . . . 1-1 Functional Overview . . . . . . . . . . . . . . . . 1-4 Additional Information . . . . . . . . . . . . . . 1-5 Product Certification . . . . . . . . . . . . . 1-5 RoHS Compliance. . . . . . . . . . . . . . . . 1-6 Terminology and Notation . . . . . . . . 1-6 Technical References. . . . . . . . . . . . . 1-6 2 Setup Electrostatic Discharge . . . . . . . . . . . . . . 2-1 Katana®752i Circuit Board. . . . . . . . . . .
8 Local PCI Bus PCI Enumeration. . . . . . . . . . . . . . . . . . . . .8-1 PCI ID Select and Interrupts . . . . . . . . . . .8-1 Geographical Addressing . . . . . . . . . . . . .8-2 PCI Bus Control Signals . . . . . . . . . . . . . . .8-2 9 PTMC Interface PTMC Installation . . . . . . . . . . . . . . . . . . . .9-1 PTMC Connector Pinouts . . . . . . . . . . . . .9-3 10 Ethernet Interfaces Ethernet Address . . . . . . . . . . . . . . . . . . 10-1 Ethernet Ports . . . . . . . . . . . . . . . . . . . . .
Contents (continued) JFFS2 File Systems. . . . . . . . . . . . . . . . . 15-12 ls . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-12 fsinfo. . . . . . . . . . . . . . . . . . . . . . . . .15-12 fsload . . . . . . . . . . . . . . . . . . . . . . . .15-12 chpart . . . . . . . . . . . . . . . . . . . . . . . .15-12 Memory Commands . . . . . . . . . . . . . . 15-12 cmp. . . . . . . . . . . . . . . . . . . . . . . . . .15-13 cp . . . . . . . . . . . . . . . . . . . . . . . . . . .15-13 find . . . . .
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Figures Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Figure 2-1: Katana®752i Front Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2-2: Component Map, Top (Rev. 03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Figure 2-3: Component Map, Bottom (Rev. 03). . . . . . . . . . . . . . . . . . . . .
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Tables Table 1-1: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Table 1-2: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2: LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables x (continued) Katana®752i User’s Manual Table 11-17: Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 Table 11-18: System Firmware Progress OEM Event Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Table 12-1: HSL PLD Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Table 13-1: CT Clock Control Registers . . . . . .
Registers Register 4-1: 750GL Hardware Implementation Dependent, HID0. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Register 4-2: 750GL Hardware Implementation Dependent, HID1. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Register 4-3: 750GL Hardware Implementation Dependent, HID2. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Register 4-4: CPU Machine State (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section 1 Overview The Emerson Katana® 752i is an intelligent input/output (I/O) processing blade for use in a CompactPCI backplane. It is compatible with the CompactPCI Packet-Switched Backplane (cPSB) and has two PCI Telecom Mezzanine Card (PTMC) sites that can support two telecommunications interface cards, such as the Emerson PM/3Gv. The Katana®752i draws processing power from its IBM PowerPC® 750GL microprocessor, running at a speed of up to 1GHz. A Marvell system controller serves as a PCI bridge.
Overview: Components and Features SDRAM: The Katana®752i allows for a 72-bit Small-Outline Dual In-Line Memory Module (SODIMM) of up to two gigabytes to support the CPU. (Please contact Emerson for the availability of one- and two-gigabyte SO-DIMMs.) This SDRAM operates at a speed of up to 200 MHz and has Error Checking and Correction (ECC) code. Flash: The Katana®752i supports up to 128 megabytes soldered user Flash memory for the CPU.
Overview: Components and Features PTMC Sites: The Katana®752i has two standard PCI Telecom Mezzanine Card (PTMC) slots, which allow for the use of two compatible PTMC boards, such as the Emerson PM/3Gv telecommunications interface card. (Refer to the PM/3Gv User’s Manual for details on the PM/3Gv.) The Katana®752i complies with Configuration 2 of the PCI Telecom Mezzanine/Carrier Card Specification, PICMG 2.15.
32/64/128 MB Flash 512KB Socketed Flash μDB-9 RS232 RJ45 RJ45 1000BaseT 1000BaseT MAG PMC Site #1 32 bit/33/66MHz PCI 64 User I/O CT Bus per PT2MC PMC Site #2 J14 J13 J22 J21 J24 J23 Opt. Opt. KS8721CL KS8721CL J5 I/O User I/O MAG BCM 5461S 32 bit/33/66MHz PCI 64 User I/O CT Bus per PT2MC J11 Opt. TSI T8110 J12 Clock Buffer RMII GbE MAC/PHY PCI MAG MAG BCM BCM 5461S 5461S CT Bus Clocks J3 cPSB & I/O Opt J4 H.
Overview: Additional Information ADDITIONAL INFORMATION This section lists the Katana®752i hardware’s regulatory certifications and briefly discusses the terminology and notation conventions used in this manual. It also lists general technical references. Mean time between failures (MTBF) has been calculated at 500,674 hours using Telcordia SR-232, Issue 1, Reliability Prediction for Electronic Equipment at 40°C.
Overview: Additional Information Emerson maintains test reports that provide specific information regarding the methods and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or a poorly grounded chassis may adversely affect the Katana®752i hardware’s ability to comply with any of the stated specifications. The UL web site at ul.com has a list of Emerson’s UL certifications.
Overview: Additional Information Table 1-2: Technical References Device/Interface: Type: Document: 1 CompactPCI® Specification (PCI Industrial Computers Manufacturers Group, PICMG® 2.0 R3.0, Oct. 1, 1999) CompactPCI Hot Swap Specification (PICMG® 2.1 R2.0, Jan. 17, 2001) System Management Specification (PICMG® 2.9 R1.0, Feb. 2, 2000) PCI Telecom Mezzanine/Carrier Card Specification (PICMG® 2.15 R1.0, Apr. 11, 2001) Packet Switching Backplane Specification (PICMG® 2.16 R1.0, Sept.
Overview: Additional Information Device/Interface: Type: Document: 1 Ethernet BCM5461S BCM5461S 10/100/1000Base-T Gigabit Ethernet Transceiver Advance Data Sheet (Broadcom Corp., 5461S-DS04-R, April 27, 2004) (continued) http://www.broadcom.com 82544EI 82544EI Gigabit Ethernet Controller Datasheet and Hardware Design Guide; Application Note (AP-422) (Intel Corp., Doc. No. A44740-005, Rev. 0.80, Dec. 2003) http://www.intel.com KS8721CL KS8721CL 3.
Overview: Additional Information Device/Interface: Type: Document: 1 H.110 T8110 Ambassador® T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine (Agere Systems, April 2001 AY01-021CT1) (continued) http://www.agere.com H.110 Hardware Compatibility Specification: CT Bus (ECTF, revision 1.0) http://www.ectf.
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Section 2 Setup This chapter describes the physical layout of the boards, the setup process, and how to check for proper operation once the boards have been installed. This chapter also includes troubleshooting, service, and warranty information. ELECTROSTATIC DISCHARGE Before you begin the setup process, please remember that electrostatic discharge (ESD) can easily damage the components on the Katana®752i hardware.
Setup: Katana®752i Circuit Board Figure 2-1: Katana®752i Front Panel PMC Site #2 PMC Site #1 Note: PMC Site #1 is not available for standard 2-GB SO-DIMM configurations. However, it may be available for some custom 2-GB configurations. Please contact Artesyn for details.
Katana®752i User’s Manual C768 C769 C773 C774 U54 C19 C89 CR2 J7 R918 C807 R20 U5 U5S C109 C775 C772 R943 C770 C60 C4 L4 C765 C92 C767 CR3 L2 U3 C5 C6 C3 RN1 R5 U7 C111 J1 RN19 RN20 RN21 RN22 RN23 C112 C58 C59 RN2 C763 U1 C98 C113 R831 C764 RN24 RN25 RN26 RN27 RN28 RN29 C97 U23HC U23H U11 R1 L26 C805 R284 R288 R923 R921 R924 C45 R919 R920 R946 R932 R17 CR6 L3 CR5 C25 RN3 C61 C7 C114 C108 JP1 C692 R14 R13 R16 R15 R8 R7 R10 R9 R11 R12 C23 C20
Setup: Katana®752i Circuit Board Figure 2-3: Component Map, Bottom (Rev.
Setup: Katana®752i Circuit Board Figure 2-4: Jumper, Fuse, and Switch Locations, Top COPYRIGHT 2004 10006008-00 REV A J5 J22 J21 F4 F4 Fuse for 5-Volt Supply to RTM, 2.5A F3 F3 Fuse for 3.3-Volt Supply to RTM, 2.
Setup: Katana®752i Circuit Board Figure 2-5: Fuse, and LED Locations, Bottom R306 C623 C619 C646 R795 R794 C347 R693 R796 C636 R367 R761 R760 C780 C604 C645 RN62 R170 R67 R70 R87 R88 R916 R103 R110 R122 R917 R101 RN46 RN51 L10 L11 R907 R53 R57 R56 C150 R221 RN262 RN72 RN77 RN85 RN87 R42 R107 C182 RN261 C132 C131 U38 CR9 C130 R40 CR8 R22 R50 R59 R55 RN71 RN76 RN84 RN86 RN64 RN68 RN75 RN80 RN63 RN67 RN74 RN79 C171 R491 R490 R281 R247 RN101 RN180 RN168 RN113 RN114
Setup: Katana®752i Circuit Board Identification Numbers Before you install the Katana®752i circuit board in a system, you should record the following information: ❐ The board serial number:____________________________________________ . The board serial number appears on a bar code sticker located on the back of the board. ❐ The board product identification: _____________________________________ . This sticker is located near the board serial number.
Setup: Katana®752i Circuit Board J4 : J4 is a 90-pin connector that routes computer telephony (CT) bus signals to the CompactPCI backplane. See Chapter for pinouts. J5: J5 is a 110-pin connector that routes user input/output signals directly from the J24 connector at PTMC expansion site #2. It also routes optional RMII signals from both PTMC sites. See Chapter for pinouts. J6: J6 is a 3-pin header on the circuit board for the ejector switch (for factory use only).
Setup: Katana®752i Setup LED: Color: Signal Name: Comments: CR3 Green 750GL_LED4 programmable LED on front panel (via light pipe LP1) CR4 750GL_LED3 CR5 750GL_LED2 CR6 750GL_LED1 CR10 IPMI_STATUSOUT IPMI controller status CR32 GIG0_LINK_LED* Port 1 Gigabit Ethernet CR33 GIG0_LINK2* CR34 GIG0_ACT_LED* CR35 GIG0_LINK1* CR20 GIG1_ACT_LED* CR21 GIG1_LINK_LED* CR22 GIG1_LINK2* CR23 GIG1_LINK1* CR39 PMC0_ACTLED CR41 PMC0_LINKLED_R CR38 PMC1_ACTLED CR40 PMC1_LINKLED_R –
Setup: Troubleshooting Power Requirements The Emerson Katana®752i circuit board typically requires about 35 watts of power when performing a simple memory test with no PMC/PTMC modules installed. The exact power requirements for the Katana®752i circuit board depend upon the specific configuration of the board, including the CPU frequency, amount of memory installed on the board, and PTMC configuration.
Setup: Troubleshooting moninit noburn Executing the above command will set all environment variables to default values and erase any user-added environment variables. Please see “Environment Parameter Commands” on page 15-18, for additional information. Technical Support If you need help resolving a problem with your Katana®752i, visit http://www.emersonembeddedcomputing.com on the Internet or send e-mail to support@artesyncp.com.
Setup: Troubleshooting Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA number.
Section 3 Reset Logic This chapter provides a system-level overview of the reset logic for the Katana®752i. It also describes the various reset sources. GENERAL OVERVIEW The Katana®752i uses discrete logic on a programmable logic device (PLD) to implement the reset circuitry. Fig. 3-1 on the following page shows an overview of the reset signals and logic.
3.3V IPMI Power 2.5V PMC 3.3V LTC1728 Voltage Monitor 2.5V 3.3V 5V Default: Jumper Out = cPCI reset is disabled cPCI_RST core reset rstout_1 rstout_2 rstout_3 Zircon PM cPCI_RST_OU T Enable OSC_EN 1.8V Voltage Monitor Front Panel Push Button Voltage Monitor Oscillators OSC_E N pmc_rst por_rst aux_por_rst ipmi_rst eth_rst Pci1_rst Bcm5461_rst 750GL Complex FL_RP Soldered Flash RP PMC Site 1 reset PMC Site 2 reset Notes: 1. All discrete logic located inside PLD 2.
Reset Logic: Reset Sources RESET SOURCES The Katana®752i circuit board can be reset from the following sources: • Power-On Reset (POR) circuitry • CompactPCI Reset • Power Monitor Reset • 750GL Processor Reset (JTAG header) • Remote IPMI Reset • Front Panel Reset • Watchdog Timer Reset CompactPCI Reset Enable The Katana®752i has an optional configuration jumper at JP2 (see Fig. 2-4).
Reset Logic: Reset Sources Figure 3-2: 750GL Reset Logic hreset sreset flash_wp Soldered Flash trst COP/JTAG cop_hreset fl_rp cop_sreset PMC Sites cop_trst start_lrst pmc_rst cpu_hreset pwr_good pwr_good por_rst Device cpu_trst Bus ks8721_rst eth_rst PLD ipmi_rst por_rst cpci_rst 750GX GL reset reset KS8721CL PHY KS8721CL gt_pci0 HSL PLD gt_pci1 gt_sysrst IPMI trst start_rst (switch_rst) gt_wde cPCI sreset cpu_sreset Power rst hreset rst reset reset KS8721CL gt_wde sys
Section 4 Processor The Katana®752i processor complex consists of a processor and a system controller/PCI bridge device (see Chapter ) with associated memory and input/output interfaces. The processor complex supports soldered and socketed user Flash memory, DDR SDRAM, an EIA232 serial console port, and three 10/100/1000BaseT Ethernet ports. PROCESSOR OVERVIEW This chapter provides an overview of the processor logic on the Katana®752i.
Processor: Processor Overview Figure 4-1: 750GL Block Diagram Control Unit Completion Instruction Fetch Branch Unit 32KB I-Cache with Parity System Unit Dispatch BHT/BTIC GPRs FXU1 FXU2 FPRs LSU Rename Buffers Rename Buffers FPU 1MB 32KB D-Cache with Parity L2 Tags with Parity Physical Memory Map L2 Cache w/ECC Enhanced 60x BIU The Katana®752i monitor (see Chapter ) initializes the devices required to configure the memory map for the 750GL bus.
Processor: Processor Overview Figure 4-2: 750GL Memory Map 32-Bit Hex Address: FFFF,FFFF Boot Mirror FF80,0000 F834,0000 Reserved F830,0000 SRAM F821,0000 HSL PLD Registers F820,0000 Device Bus PLD Registers F811,0000 Reserved F810,0000 MV64460 Registers F808,0000 Reserved F800,0000 Flash Socket FLASH (up to 128MB) E800,0000 cPCI I/O Space E000,0000 cPCI Memory Space C000,0000 Reserved B400,0000 PMC PCI I/O Space B000,0000 PMC PCI Memory Space 8000,0000 SDRAM (up to 2GB) 0000,0000 1000
Processor: Processor Reset This table summarizes the physical addresses for the 750GL on the Katana®752i board and provides a reference to more detailed information.
Processor: Processor Initialization Hardware Implementation Dependent 0 Register The Hardware Implementation Dependent 0 Register (HID0) contains bits for CPU-specific features. Most of these bits are cleared on initial power-up of the Katana®752i. Please refer to the IBM PowerPC documentation for more detailed descriptions of the HIDx registers.
Processor: Processor Initialization BTIC: Branch Target Instruction Cache enable. ABE: Address Broadcast Enable (for cache ops, eieio, sync). BHT: Branch History Table enable. NOOPTI: No-op the dcbt/dcbst instructions. Hardware Implementation Dependent 1 Register The 750GL includes two phase-lock loops (PLL0 and PLL1), which allow the processor clock frequency to be changed to one of the PLL frequencies via software control.
Processor: Processor Initialization PR0: PLL0 Range select bits. PC1: PLL1 Configuration bits. PRI: PLL1 Range bits. Hardware Implementation Dependent 2 Register Parity is implemented for the following arrays: I-Cache, I-Tag, D-Cache, D-Tag, and L2 Tag. Status bits are set when a parity error is detected and cleared when the HID2 register is written.
Processor: Exception Handling EXCEPTION HANDLING Each CPU exception type transfers control to a different address in the vector table. The vector table normally occupies the first 2000 bytes of RAM (with a base address of 0000,000016) or ROM (with a base address of F800,000016). An unassigned vector position may be used to point to an error routine or for code or data storage. Table 4-4 lists the exceptions recognized by the processor from the lowest to highest priority.
Processor: Exception Processing Exception: Vector Address Hex Offset: Notes: (continued) – 00000 Reserved. EXCEPTION PROCESSING When an exception occurs, the address saved in Machine Status Save/Restore register 0 (SRR0) helps determine where instruction processing should resume when the exception handler returns control to the interrupted process.
Processor: Exception Processing FP: Floating-Point available. This bit is set on initial power-up. 0= Prevents floating-point instructions dispatch (loads, stores, moves). 1= Executes floating-point instructions. ME: Machine check Enable. 0= Machine check exceptions disabled. 1= Machine check exceptions enabled. FE0/FE1: These bits define the Floating-point Exception mode.
Processor: Cache Memory CACHE MEMORY The 750GL processor provides both level 1 (L1) and level 2 (L2) cache memory. This section describes this memory. L1 Cache The 750GL processor has separate, on-chip, 32-kilobyte, Level 1 (L1) instruction and data caches with eight-way, set-associative translation lookaside buffers (TLBs). The CPU supports the modified/exclusive/invalid (MEI) cache coherency protocol. The data bus width for bus interface unit (BIU) accesses of the L1 data cache array is 256 bits.
Processor: Cache Memory L2DO: L2 Data-Only. Setting this bit inhibits the caching of instructions in the L2 cache. All accesses from the L2 instruction cache are treated as cache-inhibited by the L2 cache. L2I: L2 global Invalidate. Setting this bit invalidates the L2 cache globally by clearing the L2 status bits. L2WT: L2 Write-Through. Setting this bit selects write-through mode (rather than default copy-back mode) so all writes to the L2 cache also write through to the 60x bus. L2TS: L2 Test Support.
Processor: JTAG/COP Headers JTAG/COP HEADERS The 750GL CPU provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. The internal common-on-chip (COP) debug processor allows access to internal scan chains for debugging purposes, and can also be used as a serial connection to the core for emulator support.
Processor: 4-14 JTAG/COP Headers Katana®752i User’s Manual Pin: Signal: I/O: Description: (continued) 15 CHKSTPO* Output Checkstop (halted) indication (see also Checkstop LED indicator, CR31, in Fig.
Section 5 System Controller The Katana®752i processor complex consists of a processor (see Chapter ) and a system controller/PCI bridge device with associated memory and input/output interfaces. This chapter describes the Marvell MV64460 system controller/PCI bridge device implementation. OVERVIEW The Discovery™ III PowerPC® System Controller (MV64460) from Marvell is an integrated system controller with a PCI interface and communication ports for high performance control applications.
System Controller: CPU Interface Figure 5-1: MV64460 Block Diagram CPU at up to 200 MHz CPU Interface + 2 Mb SRAM 4 DMA 2 XOR SCC, TWSI GPIO, SCC, TWSI, Int, Timers 10/100/1000 3 Ports Gb Ethernet + FIFO Interface DDR 72-bit at up to 200 MHz Device 32-bit at 66 MHz PCI PCI 64-bit at 33/66 MHz 64-bit at 33/66 MHz CPU INTERFACE CPU interface features include: • 32-bit address and 64-bit data buses • Support for Symmetrical Multi-Processing (SMP) in both 60x and MPX bus modes • Support for up
System Controller: SDRAM Controller 1 Read the CPU Configuration register. This guarantees that all previous transactions in the CPU interface pipe are flushed. 2 Program the register to its new value. 3 Read polling of the register until the new data is being read. Caution: Setting the CPU Configuration register must be done only once. For example, if the CPU interface is configured to support Out of Order (OOO) read completion, changing the ! register to not support OOO read completion is fatal.
System Controller: Internal (IDMA) Controller INTERNAL (IDMA) CONTROLLER Each of the four DMA engines can move data between any source and any destination, such as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by moving large amounts of data without significant CPU intervention. Read and write are handled independently and concurrently. TIMER/COUNTERS Each of the four 32-bit wide timer/counters can be selected to operate as a timer or a counter.
System Controller: PCI Interface PCI Identification The Katana®752i has been assigned the following PCI identification numbers. Table 5-1: PCI Identification Values Field: Value: Vendor ID 0x11AB Description: Marvell Device ID 0x6480 MV64460 System Controller Subsystem Vendor ID 0x1223 Emerson Network Power Subsystem Device ID 0x0048 Katana®752i PCI Read/Write The MV64460 becomes a PCI bus master when the CPU, IDMA, or MPSC SDMAs initiate a bus cycle to a PCI device.
System Controller: Doorbell Registers monitor the state of the PCI bus INTA*—INTD* signals (PCI1 only). The MV64460 contains registers that control the masking, unmasking, and priority of the PMC interrupts as inputs to the processor. DOORBELL REGISTERS The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts on both the PCI and CPU buses.
System Controller: On-Card Memory ON-CARD MEMORY The Katana®752i has various types of on-card memory to support the MV64460 system controller and the 750GL processor. It has user Flash, SDRAM for data storage, and several serial EEPROMs for non-volatile memory storage. The following subsections describe these memory devices. User Flash The Katana®752i user Flash memory interface supports soldered devices of 32, 64, or 128 megabytes for the processor complex.
System Controller: I2C Interface EEPROMs The MV64460 uses an 8-kilobyte serial EEPROM at hex location 5316 on the I2C bus to store configuration data. Also, the MV64460 provides a second 8-kilobyte serial EEPROM at hex location A616 on the I2C bus to provide additional non-volatile information such as board, monitor, and operating system configurations. All Emerson-specific data is stored in the upper 2 kilobytes of the device. The SROM data organization is allocated as follows.
I2C Interface System Controller: Figure 5-2: I2C Interface Diagram Marvell MV64460 Bridge Configurable address through software control MV1_SDA/SCL 0xA4 SODIMM ROM 0xD0 Real-time clock 0xA6 NVRAM 0xAE MV64460 initialization ROM mv1_port_sel Temperature sensor IPMI_SDA/SCL Temperature sensor 0x92 0xA2 IPMI Bootloader and FRU ROM 0xA0 PVT_SDA/SCL 0x90 ipmi_rst* MUX IPMI Bootcode ROM I2C #1 I2C #2 Configurable address through software control I2C #0 Backplane IPMB Qlogic ZirconPM
System Controller: GPIO Signal Definitions GPIO SIGNAL DEFINITIONS The MV64460 system controller on the Katana®752i has 32 general-purpose input output (GPIO) pins that are used for various purposes. The following table describes the GPIO pin assignments.
System Controller: Console Serial Port Pin: Direction: Description: (continued) 30 – unused 31 input MVL_PCI0_HS signal, ejector handle status; 1=latch closed, 0=latch open (For rev. 0 boards, software must debounce switch input.) CONSOLE SERIAL PORT The processor complex on the Katana®752i has an asynchronous console serial port on the front panel. This port operates at EIA-232 signal levels, but does not provide any handshaking functionality.
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Section 6 Device Bus PLD The processor complex on the Katana®752i has a programmable logic device (PLD) that provides control logic for the 750GL device bus. This PLD implements various registers relating to reset control, interrupt handling, product identification, PCI enumeration, and board configuration. This chapter describes the registers in the device bus PLD, which is also known as the MVC PLD. RESET REGISTERS The device bus PLD routes and distributes the reset signals.
Device Bus PLD: Interrupt Registers Register 6-2: Reset Command 7 6 5 4 3 SCL SDA PCI0 Reserved FR 2 1 Reserved 0 HR SCL: Direct control for I2C clock signal: 1=Tri-states the PLD 0=Drives logic low SDA: Direct control for I2C data signal: 1=Tri-states the PLD 0=Drives logic low PCI0 : PCI0 reset status, as set by JP1, pins 7-8; software should not overwrite this value: 1=cPCI functionality is disabled (MV64460 PCI0 interface held in reset) 0=cPCI functionality is enabled (MV64460 PCI0 inter
Device Bus PLD: Product Identification SREN: PCI SERR Enable interrupt routed from PCI SERR to MV64460: 1=Enabled to generate an interrupt 0=Disabled (default) PREN: PCI PERR Enable interrupt routed from PCI PERR to MV64460: 1=Enabled to generate an interrupt 0=Disabled (default) The Interrupt Pending register at hex location F820,300016 allows software to determine which source has caused an interrupt, as follows.
Device Bus PLD: Revision Registers Register 6-6: EReady 7 6 5 4 3 2 1 Reserved 0 ERdy ERdy: Monarch (read): 1=PCI devices are ready to be enumerated 0=PCI devices not ready to be enumerated Non-Monarch (write): 1=PMC is ready to be enumerated 0=PMC is not ready to be enumerated REVISION REGISTERS The Katana®752i device bus PLD provides two read only registers to track hardware and PLD revisions.
Device Bus PLD: Board Configuration Registers Note: Board Configuration 2 register is not implemented in the Katana®752i. Register 6-9: Board Configuration 3.
Device Bus PLD: Other Registers OTHER REGISTERS The IPMI Port Select register at hex location F820,E00016 allows access to the IPMI interface, as follows. Register 6-12: IPMI Port Select 7 6 5 4 PORT_SEL 3 2 1 0 Reserved PORT_SEL: IPMI Port Selection: Allow processor access to the IPMI controller and temperature sensors 1=Disabled (default) 0=Enabled The LED register at hex location F820,D00016 allows software to access the programmable LEDs (on the Katana®752i front panel), as follows.
Section 7 Real-Time Clock The processor complex on the Katana®752i has a standard real-time clock (RTC), consisting of an M41T00 device from STMicroelectronics. The M41T00 has an integrated year-2000compatible RTC, power sense circuitry, and uses eight bytes of non-volatile RAM for the clock/calendar function. It is powered from the +3.3 volt rail during normal operation. The M41T00 device connects to an I2C bus (see page 5-8).
Real-Time Clock: Clock Operation 1 Seconds register 2 Minutes register 3 Century/Hours register 4 Day register 5 Date register 6 Month register 7 Years register 8 Control register The M41T00 clock continually monitors the supply voltage (Vcc) for an out of tolerance condition.
Real-Time Clock: Clock Operation ST: Stop bit 1=Stops the oscillator 0=Restarts the oscillator within one second CEB: Century Enable Bit 1=Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century 0=CB will not toggle CB: Century Bit Day: Day of the week Date: Day of the month OUT: Output level 1=Default at initial power-up 0=FT/OUT (pin 7) driven low when FT is also zero FT: Frequency Test bit 1=When oscillator is running at 32,768 Hz, the FT/OUT pin will toggle at 0=The FT/OUT pin
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Section 8 Local PCI Bus The Katana®752i utilizes the Peripheral Component Interconnect (PCI) bus as the interface between the 750GL processor complex, PCI Telecom Mezzanine Card (PTMC) sites, optional T8110 time slot interchanger (TSI), and 82544 Ethernet media access controller (MAC). The Katana®752i complies with the PCI bus interface standard and the associated PMC mechanical interface standard. The Marvell MV64460 device functions as the PCI bridge and always performs local PCI bus arbitration.
Local PCI Bus: Geographical Addressing Table 8-1: ID Select Connections Katana®752i PCI Device IDSEL Address PTMC Site 1 (at J12) AD20 PTMC Site 2 (at J22) AD21 T8110 Time Slot Interchanger (TSI) AD22 MV64460 System Controller AD23 82544 Ethernet MAC AD24 The T8110 TSI connects to INTD. The MV64460 system controller connects to INTA. The Ethernet MAC connects to INTD. The PCI devices on the PTMC module(s) use the following connections.
Local PCI Bus: PCI Bus Control Signals ACK64*, REQ64*: These sustained three-state output signals tell a 64-bit PCI device whether to use the 64-bit or the 32-bit data width. Since the Katana®752i is a 32-bit board, these signals are tied off to indicate the 32-bit data width. AD00-AD31: ADDRESS and DATA bus (bits 0-31). These three-state lines are used for both address and data handling. A bus transaction consists of an address phase followed by one or more data phases.
Local PCI Bus: PCI Bus Control Signals PAR: PARITY. This is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is required by all PCI agents. This three-state signal is stable and valid one clock after the address phase, and one clock after the bus master indicates that it is ready to complete the data phase (either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains valid until one clock after the completion of the current data phase. PERR*: PARITY ERROR.
Section 9 PTMC Interface The Katana®752i Peripheral Component Interconnect (PCI) interface supports two PCI Telecom Mezzanine Card (PTMC) expansion sites. This chapter describes how to install PTMC modules and provides additional information about the PTMC signals. Each PTMC site can connect to two optional KS8721CL RMII PHY devices that route to the CompactPCI backplane connector J5 (see page 10-3).
PTMC Interface: PTMC Installation The following procedure describes how to attach a PTMC module to the Katana®752i baseboard: 1 Remove the screws from the standoffs on the PTMC module. 2 Hold the module at an angle and gently slide the faceplate into the opening on the baseboard. 3 Align the P11, P12, P13, and P14 connectors and gently press the module into place until firmly mated. Caution: To avoid damaging the module and/or baseboard, do not force the module onto the baseboard.
PTMC Interface: PTMC Connector Pinouts PTMC CONNECTOR PINOUTS PCI expansion site #1 has four 64-pin connectors, J11—J14 (see Fig. 2-2 on page 2-3 for connector locations). Table 9-1 shows the pin assignments.
PTMC Interface: 9-4 Katana®752i User’s Manual PTMC Connector Pinouts Pin J11 J12 J13 J14 35 GND TRDY* CT_D14 J3_A7 36 IRDY* +3.3V no connection J3_E6 37 DEVSEL* GND CT_D12 J3_D6 38 +5V STOP* GND J3_C6 39 GND PERR* PTENB* J3_B6 40 LOCK* GND no connection J3_A6 41 SDONE* +3.3V GND J3_E5 42 SBO* SERR* NETREF1 J3_D5 43 PAR CBE1* CT_C8B J3_C5 44 GND GND GND J3_B5 45 +3.
PTMC Interface: PTMC Connector Pinouts PCI expansion site #2 has four 64-pin connectors, J21—J24 (see Fig. 2-2 on page 2-3 for connector locations). Table 9-2 shows the pin assignments.
PTMC Interface: 9-6 Katana®752i User’s Manual PTMC Connector Pinouts Pin J21 J22 J23 J24 37 DEVSEL* GND CT_D12 J5_D6 38 +5V STOP* GND J5_C6 39 GND PERR* PTENB* J5_B6 40 LOCK* GND no connection J5_A6 41 SDONE* +3.3V GND J5_E5 42 SBO* SERR* NETREF1 J5_D5 43 PAR CBE1* CT_C8B J5_C5 44 GND GND GND J5_B5 45 +3.3V AD14 GND J5_A5 46 AD15 AD13 CT_D15 J5_E4 47 AD12 M66EN CT_D10 J5_D4 48 AD11 AD10 CT_D13 J5_C4 49 AD9 AD8 CT_D8 J5_B4 50 +5V +3.
Section 10 Ethernet Interfaces The Katana®752i supports four 10/100/1000BaseT Ethernet ports. The MV64460 system controller provides three Ethernet Media Access Control (MAC) units, and an Intel 82544EI Ethernet controller device provides direct access from the local PCI bus. Three Broadcom BCM5461S transceivers and an integrated PHY in the 82544EI provide interfaces for the 10/100/1000BaseT Ethernet ports.
Ethernet Interfaces: Ethernet Ports 001 = CPSB_1 (MAC address #2) 010 = CPSB_2 011 = FRNT_1 (ETH3) 100 = FRNT_2 (ETH4) 101 = reserved 110 = reserved 111 = reserved So for example, if the Katana®752i serial number is 1234, the CPSB_2 MAC address is: 00:80:F9:6C:07:52. ETHERNET PORTS The MV64460 system controller (see Chapter ) provides three 10/100/1000BaseT gigabit Ethernet (GbE) ports.
Ethernet Interfaces: Optional RMII PHY Devices Table 10-2: 82544EI Ethernet Port Pin Assignments, ETH4 Pin Signal Pin Signal 1 TRD0+ 5 TRD2+ 2 TRD0— 6 TRD2— 3 TRD1+ 7 TRD3+ 4 TRD1— 8 TRD3— Table 10-3: MV64460 Ethernet Port Pin Assignments, ETH3 Pin Signal Pin Signal 1 TRD0+ 5 TRD2+ 2 TRD0— 6 TRD2— 3 TRD1+ 7 TRD3+ 4 TRD1— 8 TRD3— OPTIONAL RMII PHY DEVICES In addition to the four GbE ports, the Katana®752i supports an option for two RMII PHY devices on the Katana®75
Ethernet Interfaces: Optional RMII PHY Devices Figure 10-1: RMII PHY to Transition Module PTMC Site 1 PTMC Site 2 Katana752i P13 P23 RMII RMII CR43 CR44 PHY 0x5 CR45 CR46 PHY 0x6 J5 Backplane J5 +2.5V Optional Rear Transition Module (i.e. TM/cSPAN-P8E) RJ45 10-4 Katana®752i User’s Manual RJ45 10006024-04 +2.
Section 11 IPMI Controller The Katana®752i implements a System Management Bus (SMB), as defined in the CompactPCI System Management Specification (see Table 1-2). It also supports the Intelligent Platform Management Interface (IPMI) Version 1.5 and Intelligent Platform Management Bus (IPMB) Version 1.0 specifications. At the core of SMB/IPMI interface is a Zircon PM device from QLogic Corporation.
IPMI Controller: SMB/IPMI Overview The Katana®752i system management interface uses the Zircon PM device’s general-purpose input/output (GPIO) pins for the following functions: • watchdog sensor input (from 750GL processor) • GPIO (to 750GL processor) • reset outputs (to 750GL processor) • IPMI reset control • cPCI Geographical Addressing inputs The Zircon PM controller also has input pins to sense all on-board voltage supplies. Fig.
IPMI Controller: SMB/IPMI Overview Figure 11-1: IPMB Connections Block Diagram Katana752i IPMI_OUT MV64460 Timer Out MV1_port_sel ipmi_rst* Temp Sensor IPMI Bootloader and FRU ROM I2C #1 Temp Sensor IPMI Bootcode ROM I2C #2 GPIO[0:23] A-to-D 6 IPMI Microcontroller IPMI Power 3 Voltage Monitor Reset A-to-D 5 A-to-D 4 A-to-D 3 A-to-D 2 A-to-D 1 5V 3.3 V 2.5 V 1.8 V (optional) CPU Core 1.
IPMI Controller: I/O Interface I/O INTERFACE The Zircon PM provides 24 user-definable input/output (I/O) pins. The following table shows how the Katana®752i implements these pins.
IPMI Controller: I2C Interfaces In addition to the General Purpose I/O, there are six analog-to-digital (A2D) input pins that are used for sensing the various power supplies on the board. The following table describes the Katana®752i implementation of these pins. Table 11-2: Zircon PM Analog-to-Digital Input Pin Functions Zircon PM Pin: Signal Name: Nominal Voltage: Function: A2D1 MON_PMC_3_3V 2.0V connects to the 3.3V PTMC power supply A2D2 MON_CPU_CORE 1.
IPMI Controller: IPMI Message Protocol The PICMG 2.9 specification defines addressing on the public and private IPMBs. It defines the slave addresses assigned to the chassis, power supplies, and peripheral boards based on geographical addressing. Table 11-3 lists the slave address of each peripheral board, based on its geographical address.
IPMI Controller: IPMI Message Protocol Byte: Bits: 7: 6: 5: 4: 6 7:N N+1 3: 2: 1: 0: Command Data Checksum The first byte contains the responder’s Slave Address, rsSA. The second byte contains the Network Function Code, netFn, and the responder’s Logical Unit Number, rsLUN. The third byte contains the two’s-complement checksum for the first two bytes. The fourth byte contains the requester’s Slave Address, rqSA.
IPMI Controller: IPMI Message Protocol IPMI Network Function Codes All IPMI messages contain a Network Function Code field, which defines the category for a particular command. Each category has two codes assigned to it–one for requests and one for responses. The code for a request has the least significant bit of the field set to zero, while the code for a response has the least significant bit of the field set to one.
IPMI Controller: IPMI Message Protocol IPMI Completion Codes All IPMI response messages contain a hexadecimal Completion Code field that indicates the status of the operation. Table 11-7 lists the Completion Codes (as defined in the IPMI specification) used by the Zircon PM.
IPMI Controller: IPMI Message Protocol Code: Description: (continued) Device-Specific (OEM) Codes 01-7E 01-7E Device specific (OEM) completion codes–command-specific codes (also specific for a particular device and version). Interpretation of these codes requires prior knowledge of the device command set.
IPMI Controller: IPMI Message Protocol Command: (continued) netFn: LUN: Cmd: 00 21 Get Device SDR Sensor/Event 04, 05 Reserve Device SDR Repository Sensor/Event 04, 05 00 22 Get Sensor Reading Factors Sensor/Event 04, 05 00 23 Set Sensor Thresholds Sensor/Event 04, 05 00 26 Get Sensor Thresholds Sensor/Event 04, 05 00 27 Get Sensor Reading Sensor/Event 04, 05 00 2D Set Sensor Type Sensor/Event 04, 05 00 2E Get Sensor Type Sensor/Event 04, 05 00 2F Get Device ID
IPMI Controller: IPMI Message Protocol Table 11-9: Get Sensor Reading Parameters Type: Byte: Data Field: Request Data 1 Sensor Number (hex) Response Data 1 Completion Code 2 Sensor Reading 41=PMC 3.3V Voltage Monitor 42=CPU_CORE Voltage Monitor 43=1.8V Voltage Monitor 44=2.5V Voltage Monitor 45=3.3V Voltage Monitor 46=5.0V Voltage Monitor 50=750GL Watchdog 60=Outflow Temperature Sensor 61=Inflow Temperature Sensor 70=750GL System Firmware Error Bits[0:7], byte of reading.
IPMI Controller: IPMI Message Protocol Type: Byte: Data Field: (continued) Response Data 4 Present Threshold Comparison Status For threshold-based sensors: Bits[7:6], Reserved. Returned as 1 (binary). Ignore on read.
IPMI Controller: IPMI Message Protocol Master Write-Read I2C (Application) The Master Write-Read I2C command allows for direct accesses to I2C devices. This command can read from or write to any of the Zircon PM’s private I2C devices, such as SROMs or temperature sensors. Typically, you would use it to update the Zircon PM’s firmware from the management controller. Table 11-10 shows the request/response data parameters for this command.
IPMI Controller: IPMI Message Protocol Write Setting (OEM) The Write Setting command provides the ability to write a value to a general-purpose input/output (GPIO) pin on the Zircon PM. By toggling certain GPIO pins, software can reset or power-down the board. Table 11-11 shows the request/response data parameters for the Write Setting command. Table 11-11: Write Setting Parameters Type: Byte: Data Field: Request Data 1 Bits[7:1], Device Slave Address Bit[0], Reserved. Write as zero.
IPMI Controller: IPMI Message Protocol Read Setting (OEM) The Read Setting command provides the ability to read the value of a general-purpose input/output (GPIO) pin on the Zircon PM. Software can read certain GPIO pins to determine if the board is in reset or powered-down. Table 11-12 shows the request/response data parameters for the Read Setting command. Table 11-12: Read Setting Parameters Type: Byte: Data Field: Request Data 1 Bits[7:1], Device Slave Address Bit[0], Reserved. Write as zero.
IPMI Controller: IPMI Message Protocol Set Heartbeat (OEM) The Set Heartbeat command configures the Zircon PM to send a heartbeat message to a receiver on the IPMB or private I2C bus at a specific interval. The interval can range between 100 milliseconds and 25.6 seconds. The heartbeat message data may be a string of bytes or a command that gets processed at each interval. Table 11-13 shows the request/response data parameters for the Set Heartbeat command.
IPMI Controller: IPMI Message Protocol Get Heartbeat (OEM) The Get Heartbeat command returns the current configuration of the heartbeat function for a specified interface. The response data has the same definition as the Set Heartbeat request data (see Section ). Table 11-14 shows the request/response data parameters for the Get Heartbeat command.
IPMI Controller: IPMI Message Protocol IPMI FRU Information The Zircon PM stores Field Replaceable Unit (FRU) information in its boot memory (SROM). The data structure contains information such as the product name, part number, serial number, and manufacturing date. Please refer to the IPMI specification for complete details on the FRU data structure. Table 11-15 lists the general contents of the Katana®752i’s FRU information.
IPMI Controller: IPMI Message Protocol IPMI Device SDR Repository The Zircon PM implements a Device SDR Repository that contains Sensor Data Records for the Zircon PM, the FRU device, and each sensor. A system management controller may use the Get Device SDR command to read the repository and dynamically discover the capabilities of the board. Please refer to the IPMI specification (listed in Table 1-2) for more information on using Sensor Data Records and the Device SDR Repository.
IPMI Controller: IPMI Message Protocol Byte:1 Field: Description: (continued) 7 Sensor Type Indicates event class or type of sensor that generated the message 8 Sensor Number A unique number indicating the sensor that generated the message 9 Event Dir / Event Type Upper bit indicates direction (0 = Assert, 1 = Deassert); Lower 7 bits indicate type of threshold crossing or state transition 10 Event Data 0 Data for sensor and event type 11 Event Data 1 (Optional) Data for sensor and event t
IPMI Controller: IPMI Message Protocol The Event Data 0 byte has three fields: Bits 7:6 describe the contents of Event Data 1 (set to 102 when an OEM code is present in Event Data 1). Bits 5:4 describe the contents of Event Data 2 (also set to 102 when an OEM code is present). Bits 3:0 store the Sensor-specific Offset value for the System Firmware Progress sensor (zero indicates a POST Error). Please see the IPMI specification for further information on these fields.
Section 12 Hot Swap The Katana®752i baseboard incorporates a Linear Technologies LTC1643L Hot Swap™ controller device and is fully compliant with the CompactPCI (cPCI) Hot Swap Specification (see references in Table 1-2). Katana®752i circuit boards allow for High Availability Hot Swap systems, including cPCI/PSB systems (without a cPCI interface).
Hot Swap: cPCI Functionality CPCI FUNCTIONALITY The Katana®752i implements an optional jumper, JP1 (see Fig. 2-4), which can enable or disable the board’s cPCI functionality. By default, cPCI is enabled (jumpers placed on JP1, pins 1—2 and pins 7—8). The jumper settings also can prevent the cPCI_RST signal from resetting the board. This allows system designers the flexibility to choose whether or not the Katana®752i uses the cPCI reset signal (from the backplane).
Hot Swap: Hot Swap LED and Ejector Switch Control The Hot Swap logic functions as follows when a board is removed from a slot: 1 The operator opens the board’s ejector handles and the PCI0_HS signals goes low to indicate that the board is about to be extracted. 2 The REM bit is set, and the PCI0_ENUMn pin is asserted, if not masked by the EIM bit. 3 System Hot Swap software detects PCI0_ENUMn assertion and checks the REM bits in all Hot Swap-compliant boards.
Hot Swap: Hot Swap LED and Ejector Switch Control Non-cPCI Hot Swap When the cPCI functionality is disabled, the LED/ejector switch control mechanism works in conjunction with the Power Good indication from the Hot Swap controller circuit, as shown in Fig. 12-1. Figure 12-1: Hot Swap Controller Circuit 3.3_EARLY 3.
Hot Swap: Timing Considerations low (active). This occurs when power supply voltages are not within the proper tolerance or when the BDSEL* signal is not driven low (active) to the Hot Swap controller. The LED remains illuminated until software clears bit 0 at address F821,000616 in the HSL PLD. 2 When the operator locks the ejector handle, the MV64460 bridge chip senses the event and notifies the software that a board has been inserted.
Hot Swap: HEALTHY* Signal HEALTHY* SIGNAL The Katana®752i logic asserts the HEALTHY* signal whenever the Hot Swap controller indicates that all power supplies provided by the backplane are within the appropriate range. This signal passes through the Hot Swap Logic (HSL) programmable logic device (PLD) and goes to the backplane. Other logic, including board reset signals, does not affect the HEALTHY* signal, except for the front panel reset switch, which deasserts HEALTHY* when pressed.
Section 13 CT Bus Interface The Katana®752i supports an optional computer telephony (CT) bus interface that routes various signals from the CompactPCI J4 backplane connector to the PCI Telecom Mezzanine Card (PTMC) expansion sites. The Katana®752i complies with Configuration 2 of the PCI Telecom Mezzanine/Carrier Card Specification, PICMG 2.15. Note: The standard Katana®752i configuration does not support any of the CT bus interface options. PICMG 2.
CT Bus Interface: • Katana®752i CT Bus Options User Managed Combination (UMC) UMC indicates combinations that are not to be made casually, since they may not be compatible. Potential device destruction must be assumed for these combinations. For example, a PMC64 combined with a PT3CC is subject to damage from incompatible signal mapping on Pn3/Jn3. Caution: Do not install 64-bit PMC cards on the Katana®752i since this is an invalid configuration and would cause possible damage.
CT Bus Interface: Signal Control Figure 13-1: Typical System Clocking Model CT_C8_A/CT_FRAME_A CT_C8_B/CT_FRAME_B CT_NETREF_1 CT_NETREF_2 Primary Master Bits Derived Source Secondary Master Slave Digital Trunk Card Slave Digital Trunk Card SIGNAL CONTROL The Katana®752i supports control signals that allow a PTMC site to master the CT clocks and/or data. The control registers are located in the Hot Swap Logic (HSL) programmable logic device (PLD) at hex address F821,000316.
CT Bus Interface: CT Bus Routing Without the T8110 (option 1) CT BUS ROUTING WITHOUT THE T8110 (OPTION 1) The Katana®752i option 1 routes the NETREF1 and NETREF2 clock signals; as well as the FA, C8A, FB, and C8B data signals between the J4 backplane connector and the two PTMC site connectors (see Fig. 13-2). Note: There is no data path between J4 and the PTMC sites. See Table 13-1 for buffer control settings. For the J4 connector pinouts, please refer to Table 14-1.
CT Bus Interface: CT Bus Routing Without the T8110 (option 1) Figure 13-2: CT Signal Routing Diagram —T8110 Not Installed (option 1) PM/3Gv PM/3Gv MPC8264 MPC8264 T8105 T8105 Termination Logic Termination Logic J13 J23 P13 P23 CT Data (8) Katana750i CT_NETREF1 CT_NETREF2 CT_C8A CT_C8B CT_FRAMEA CT_FRAMEB NETREF1_DIR NETREF2_DIR C8_FRAME_A_DIR C8_FRAME_B_DIR Local CT Bus 10006024-04 C8_B FRAME_B FRAME_A C8_A NETREF2 NETREF1 J4/P4 Katana®752i User’s Manual 13-5
CT Bus Interface: CT Bus Routing With the T8110 Installed (option 2) CT BUS ROUTING WITH THE T8110 INSTALLED (OPTION 2) The T8110 Time Slot Interchanger (TSI) is a PCI device that serves as a bridge between the H.110 and local CT bus on the Katana®752i. It must be properly configured before local and H.110 CT traffic can occur. There are several architectural restrictions with the local CT bus implementation on the Katana®752i as noted below.
CT Bus Interface: CT Bus Routing With the T8110 Installed (option 2) T8110: PTMC Site 1: PTMC Site 2: LCT_D0 CT_D0 — Local CT Bus Operation On the Katana®752i, option 2, the local CT clock master must always be the T8110. The two PTMC sites cannot be local CT bus masters (primary or secondary). They can only be CT slaves. • PTMCx local CT clocks CT_C8A/B must be sourced from the T8110 L_SCx pins, see Fig. 13-3. • PTMCx local CT frames CT_FA/B must be sourced from T8110 FGx pins.
CT Bus Interface: CT Bus Routing With the T8110 Installed (option 2) Figure 13-3: CT Signal Routing Diagram —T8110 Installed (option 2) From HSL PLD (bits 2:3) EN* C8A C8B QuickSwitch C8A L_SC0 C8A C8B L_SC1 C8B FA FA FG0 FA FB FB FG1 FB PTMC 1 NETREF1 NETREF1 LREF0 NETREF1 NETREF2 NETREF2 LREF1 NETREF2 CT_D31:0 LCT_D19:0 CT_D19:0 D31:0 T8110 J4 (H.110) Data lines swapped here L_SC2 C8A L_SC3 C8B FG2 FA FG3 FB LREF2 NETREF1 LREF3 NETREF2 LCT_D20:31 H.
Section 14 Backplane Signals This chapter describes the Katana®752i board’s backplane signals. It lists the pinouts for connectors J1, J2, J3, J4, and J5 on the CompactPCI backplane. OVERVIEW The Katana®752i backplane connectors provide the following connections: • Connector J1 carries power supply source signals, various CompactPCI (cPCI) utility signals and Intelligent Platform Management Interface (IPMI) control signals to/from the cPCI backplane.
Backplane Signals: Pinouts PINOUTS J1 is a 110-pin female connector (Emerson #01899062-00) that routes power supply source signals from the CompactPCI backplane, and cPCI and IPMI signals to the CompactPCI backplane, as listed in the following table.
Backplane Signals: Pinouts J2 is a 110-pin female connector (Emerson #01899063-00) that routes cPCI, Geographical Address, and power signals from the CompactPCI backplane, as listed in the table below.
Backplane Signals: Pinouts J3 is a 95-pin female connector (Emerson #01899064-00) that routes cPSB Ethernet differential signals and PTMC site #1 user I/O signals to the cPCI backplane, as listed in the table below.
Backplane Signals: Pinouts J4 is an optional 90-pin female connector (Emerson #01899070-00) that routes CT signals between the PTMC sites and the cPCI backplane, as listed in the table below.
Backplane Signals: Pinouts J5 is a 110-pin female connector (Emerson #01899063-00) that routes PTMC site user I/O and Ethernet signals to the cPCI backplane, as listed in the table below. Figure 14-1: cPCI Connector Pin Assignments, J5 Pin: 14-6 Row A: Row B: 22 PMC1_ENET_TXP 3.3V (fused) 21 PMC1_ENET_TXN 20 PMC2_ENET_TXP 19 PMC2_ENET_TXN Row C: Row D: Row E: —12V (fused) PMC1_ENET_RXP 5V (2.5A fused) 3.3V (fused) no connection PMC1_ENET_RXN 5V (2.
Section 15 Monitor The Katana®752i monitor is based on the Embedded PowerPC Linux Boot Project (PPCBoot) boot program, available under the GNU General Public License (GPL). For instructions on how to obtain the source code for this GPL program, please visit http://www.emersonembeddedcomputing.com, send an e-mail to support@artesyncp.com, or call Emerson at 1-800-327-1251. This chapter describes the monitor’s basic features, operation, and configuration sequences.
Monitor: Command-Line Features Figure 15-1: Example Monitor Start-up Display Hardware Initialization PPCBoot 1.2.0 (Oct 31 2007 - 12:52:52)1.7s CPU: Board: BusHz: I2C: DRAM: 750GX v1.2 @ 900 MHz Katana752i 200000000 ready 512MB DDR SDRAM in slot 0 VM485L6523C-CC Early setup ECC (Clearing..) 512 MB Reserving 32MB for EDNR at 0x1e000000 FLASH: [512kB@f8000000] [32MB@e8000000] [32MB@ea000000] 64.
Monitor: Basic Operation BASIC OPERATION The Katana®752i monitor performs various configuration tasks upon power-up or reset. This section describes the monitor operation during initialization of the Katana®752i board. The flowchart (see Fig. 15-2) illustrates the power-up and reset sequence (bold text indicates environment variables).
Monitor: Basic Operation Figure 15-2: Power-up/Reset Sequence Flowchart RESET Initialize HID0 Initialize MSR Initialize flash Enable icache Initialize malloc area Relocate the base of the MV64460 internal registers Is cPCI enabled? Yes Early I2C Init. LED 0010 Early mem. Init.
Monitor: Basic Operation Power-Up Timing Upon power-up, the Katana®752i initially retries cPCI cycles for a specific period of time (see “cPCI/PCI Stop Retries, Memory Read Access Only” monitor state in the tables below). After that time, it stops retrying cycles on the cPCI bus. Caution: Any read access between the “cPCI/PCI Stop Retries, Memory Read Access Only” and “Final Memory Initialization” monitor states (see Table 15-1 and Table 15-2) may result in an ECC ! exception on the Katana®752i.
Monitor: Basic Operation Time (sec): Debug LED State (bits): Monitor State: 5.344 1000 Monitor code relocated to top of memory 5.978 1001 PCI/cPCI Final Setup. Enumeration. Memory Read/Write Access 6.265 0000 Monitor Prompt POST Diagnostic Results The Katana®752i stores Power-On Self-Test (POST) diagnostic results in I2C nonvolatile random-access memory (NVRAM). This memory is located in the EEPROM at hex address 0x53 on the I2C bus.
Monitor: Monitor Recovery and Updates MONITOR RECOVERY AND UPDATES Note: The monitor provides VxWorks 6.0 support for Error Data and Reporting (EDNR). This feature allocates a persistent area of memory that retains its contents after a systerm soft reset. Any information stored in the 32megabyte window starting at 0x1E000000 should stil be available after a soft resset.
Monitor: Monitor Command Reference 3 Update the monitor: [Katana 752i (1.0)] => moninit serial# 100000 4 Reset the monitor: [Katana 752i (1.0)] => reset 5 Reset the environment parameters: [Katana 752i (1.0)] => envinit serial# If moninit( ) fails, burn the new monitor to a ROM and follow the recovery steps in “Recovering the Monitor” on page 15-7.
Monitor: Boot Commands However, commands cannot be abbreviated when accessing on-line help. You must type help and the full command name. Command Help Access the monitor online help for each command by typing help . The full command name must be entered to access the online help. Typographic Conventions In the following command descriptions, Courier New font is used to show the command format.
Monitor: Boot Commands 3 The host board finally writes 0x596F4F6B (character string “YoOk”) to MagicLoc to show that the application is ready for the target. 4 The target writes value 0x42796521 (character string “Bye!”) to MagicLoc to show that the application was found. If necessary, the target then updates its memory-resident loadaddr environment parameter with the contents of CallAddress, and the bootbus command is complete.
Monitor: Boot Commands Definition: bootp [loadAddress] [bootfilename] bootv The bootv command checks the checksum on the primary image (in Flash) and boots it, if valid. If it is not valid, it checks the checksum on the secondary image (in Flash) and boots it, if valid. If neither checksum is valid, the command returns back to the monitor prompt. Definition: Verify bootup. bootv Write image to Flash and update NVRAM.
Monitor: JFFS2 File Systems JFFS2 FILE SYSTEMS This section describes the commands for the read-only JFFS2 file systems. These commands assume a valid JFFS2 file system in Flash with support provided for two partitions: • Base of partition 0 is 0xE8180000 • Base of partition 1 is 0xE8000000 + (Total_Flash_Size/2) + 0x180000 ls The ls command lists the files in the directory. Definition: ls [directory] fsinfo The fsinfo command prints information about file systems.
Monitor: Memory Commands cmp The cmp command compares count objects between addr1 and addr2. Any differences are displayed on the console display. Definition: cmp [.b, .w, .l] addr1 addr2 count cp The cp command copies count objects located at the source address to the target address. Note: If the target address is located in the range of the Flash device, it will program the Flash with count objects from the source address. The cp command does not erase the Flash region prior to copying the data.
Monitor: Memory Commands 00080020: ffff ffff ffff ffff ffff ffff ffff ffff 00080030: ffff ffff ffff ffff ffff ffff ffff ffff ................ ................ mm The mm command modifies memory one object at a time. Once started, the command line prompts for a new value at the starting address. After a new value is entered, pressing ENTER auto-increments the address to the next location. Pressing ENTER without entering a new value leaves the original value for that address unchanged.
Monitor: Flash Commands 00080020: 00080030: 00080040: 00080050: 00080060: 00080070: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ................ ................ ................ ................ ................ ................ FLASH COMMANDS The Flash commands affect the StrataFlash devices on the Katana®752i circuit board.
Monitor: EEPROM / I2C Commands protect The protect command enables or disables the Flash sector protection for the specified Flash sector. Protection is implemented using software only. The protection mechanism inside the physical Flash part is not being used. Definition: Protect all of the Flash sectors in the address range from start to end. protect on start end Protect all of the sectors SF (first sector) to SL (last sector) in FLASH bank # N.
Monitor: EEPROM / I2C Commands icrc32 The icrc32 computes a CRC32 checksum. Definition: icrc32 chip_address[.0, .1, .2] count iloop The iloop command reads in an infinite loop on the specified address range. Definition: iloop chip_address[.0, .1, .2] [# of objects] imd The imd command displays I2C memory. For example: imd 53 1800.2 100 displays 100 bytes from offset 0x1800 of I2C device 0x53 (right-shifted 7-bit address). The .
Monitor: Ethernet Controller EEPROM Commands iprobe The iprobe command probes to discover valid I2C chip addresses. Definition: iprobe ETHERNET CONTROLLER EEPROM COMMANDS This section describes the commands that provide access to the EEPROM for the Intel 82544EI Ethernet Controller. initeth4rom The initeth4rom command sets the 82544EI controller’s EEPROM to the default values. These values include the ETH4 port Ethernet address, port settings, and ROM checksum.
Monitor: Environment Parameter Commands envinit The envinit command resets the NVRAM and serial number. Optional parameters allow you to: • specify the processor number • specify the serial number • retrieve the serial number from the FRU device • specify parameters not in the default list Definition: envinit [p1, p2, p3] [serial#, ‘fru’, ‘old’] [env: ...] printenv The printenv command displays all of the environment variables and their current values to the display.
Monitor: Test Commands TEST COMMANDS The commands described in this section perform diagnostic and memory tests. diags The diags command runs the power-on self test (POST). Definition: diags mtest The mtest command performs a simple SDRAM read/write test. Definition: mtest [start [end [pattern]]] um The um command is a destructive memory test. Definition: um [.b, .w, .l] base_addr [top_addr] OTHER COMMANDS This section describes all the remaining commands supported by the Katana®752i monitor.
Monitor: Other Commands coninfo The coninfo command displays the information for all available console devices. Definition: coninfo crc16 The crc16 command computes a CRC16 checksum on size bytes starting at buff. Optionally, it stores the result at addr. Definition: crc16 address count crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address. Definition: crc32 address count echo The echo command echoes args to console. Definition: echo [args..
Monitor: Other Commands frusetuser The frusetuser command writes count bytes to offset in the FRU user area and copies the bytes to storage. Definition: frusetuser offset count storage gethvr The gethvr command returns the contents of the Hardware Version Register (see Register Map 6-7 on page 6-4). Definition: gethvr getmonver The getmonver command prints the monitor version string of the currently running monitor (default).
Monitor: Other Commands getpcimode The getpcimode command shows how many Configuration Space Headers the Katana®752i is reporting on PCI/cPCI. Single Function means only Function 0 is available. Multi Function indicates that multiple functions (i.e. Function 0, Function 1, etc.) are available.
Monitor: Other Commands isdram The isdram command displays the SDRAM configuration information (valid chip values range from 50 to 57). Definition: isdram loop The loop command executes an infinite loop on address range. Definition: loop [.b, .w, .l] address number_of_objects memmap The memmap command displays the board’s memory map layout.
Monitor: Other Commands Modify, read, and keep the CFG address. pci next[.b, .w, .l] b.d.f address Modify automatically increment the CFG address. pci modify[.b, .w, .l] b.d.f address Write to the CFG address. pci write[.b, .w, .l] b.d.f address value reset The reset command performs a hard reset of the CPU by writing to the reset register on the board. Definition: reset run The run command runs the commands in an environment variable var.
Monitor: Other Commands Setting PCI Mode to Multi ... Complete => setspr The setspr command sets the contents of the SPR register specified by SPR_ID to SDR_Value. Definition: setspr SPR_ID SPR_Value script The script command runs a list of monitor commands out of memory. The list is an ASCII string of commands separated by the ; character and terminated with the ;; character sequence.
