Technical data

ManualsBrandsEmerson ManualsComputer equipmentMVME4100

Embedded Computing for

Business-Critical Continuity

MVME4100 Single Board Computer

Programmer’s Reference

P/N: 6806800H19B

April 2009

Summary of content (92 pages)

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Embedded Computing for Business-Critical ContinuityTM MVME4100 Single Board Computer Programmer’s Reference P/N: 6806800H19B April 2009
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© 2009 Emerson All rights reserved. Trademarks Emerson, Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co. © 2008 Emerson Electric Co. All other product or service names are the property of their respective owners. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
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Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1 1.2 1.3 1.4 1.5 2 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents Contents 3.1.17 3.1.18 3.1.19 3.1.20 3.1.21 3.1.22 3.1.23 3.1.24 3.1.25 Watch Dog Timer Load Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Watch Dog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Watch Dog Timer Resolution Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Watch Dog Timer Count Register . . . . . . . .
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Contents 4.13 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.13.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.13.2 Real Time Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.13.3 Local Bus Controller Clock Divisor . . .
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Contents Contents 6 MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
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List of Tables Table 1-1 Table 1-2 Table 2-1 Table 2-2 Table 2-3 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 3-20 Table 3-21 Table 3-22 Table 3-23 Table 3-24 Table 3-25 Table 3-26 Table 3-27 Table 3-28 Table 3-29 Table 3-30 Table 3-31 Board Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 4-11 Table 4-12 Table 4-13 Table A-1 Table A-2 Table A-3 Table A-4 Table B-1 Table B-2 Table B-3 8 MPC8548E POR Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MPC8548E Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LBC Chip Select Assignments . . . . . . .
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List of Figures Figure 1-1 Figure 3-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Boot Flash Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 10 MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
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About this Manual Overview of Contents This manual is divided into the following chapters and appendices: Chapter 1, Introduction, provides a brief product description and a block diagram showing the architecture of the MVME4100 Single Board Computer. Chapter 2, Memory Maps, provides information on the board’s memory maps. Chapter 3, Register Descriptions, contains status registers for the system resources. Chapter 4, Programming Details, includes additional programming information for the board.
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About this Manual About this Manual Acronym Description MB Megabyte Mfg Manufacturing SPD Serial Presence Detect VPD Vital Product Data Conventions The following table describes the conventions used throughout this manual.
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About this Manual Notation Description | Logical OR Indicates a hazardous situation which, if not avoided, could result in death or serious injury Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered.
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About this Manual About this Manual Comments and Suggestions We welcome and appreciate your comments on our documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to us by filling out the following online form: http://www.emersonnetworkpowerembeddedcomputing.com/ > Contact Us > Online Form In "Area of Interest" select "Technical Documentation". Be sure to include the title, part number, and revision of the manual and tell us how you used it.
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Chapter 1 Introduction 1.1 Overview This chapter briefly describes the board level hardware features of the MVME4100 Single Board Computer. Refer to the MPC8548E Reference Manual listed in Appendix B, Related Documentation, for more detail and programming information. At the time of publication of this manual, the MVME4100 is available in the configurations shown below. Table 1-1 Board Variants 1.2 Marketing Number Processor MVME4100-0171 1.
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Introduction Table 1-2 Features List (continued) Function Features System Memory One DDR2 SO-CDIMM for SDRAM with ECC 2 GBytes Up to DDR533 I2 C One 8 KB VPD serial EEPROM Two 64 KB user configuration serial EEPROMs One Real Time Clock (RTC) with removable battery Dual temperature sensor One SPD for memory on SO-CDIMM Connection to XMCspan and rear transition module Flash 128 MB soldered NOR flash with two alternate 1 MB boot sectors selectable via hardware switch H/W switch or S/W bit write protec
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Introduction Table 1-2 Features List (continued) Function Features Watchdog Timer One watchdog timer in PLD VME Interface VME64 (ANSI/VITA 1-1994) compliant (3 row backplane 96-pin VME connector) VME64 Extensions (ANSI/VITA 1.1-1997) compliant (5 row backplane 160-pin VME connector) 2eSST (ANSI/VITA 1.5-2003) compliant ANSI/VITA 1.7-2003 compliant (Increased Current Level for 96 pin & 160 pin DIN/IEC Connector Standard) VITA 41.0, version 0.
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Introduction 1.3 Block Diagram The following figure is a block diagram of the MVME4100 architecture.
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Introduction 1.4 Functional Description The MVME4100 VMEbus board is based on the MPC8548E system-on-chip (SoC) processor. The MVME4100 provides front panel access to one serial port with a micro DB-9 connector, two 10/100/1000 Ethernet ports with two RJ-45 connectors, and one USB port with one type A connector. The front panel includes a fail indicator LED, user-defined indicator LED, and a reset/abort switch.
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Introduction 20 MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
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Chapter 2 Memory Maps 2.1 Overview The following sections describe the memory maps for the MVME4100. Refer to the MPC8548E Reference Manual for additional details and/or programming information. 2.1.1 Default Processor Memory Map The following table describes a default memory map from the point of view of the processor after a processor reset.
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Memory Maps Table 2-2 Suggested Processor Address Map (continued) Processor Address 2.1.
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Memory Maps 2.1.4 VME Memory Map The MVME4100 is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2 GB.
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Memory Maps 24 MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
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Chapter 3 Register Descriptions 3.1 Overview System resources including system control and status registers, external timers, and the QUART are mapped into a 16 MB address range accessible from the MVME4100 local bus via the MPC8548E LBC. The memory map is defined in the following table including the LBC bank chip select used to decode the register. Any address that is not listed in the table blelow is unused and reserved for future use.
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Register Descriptions Table 3-1 System I/O Memory Map (continued) 26 Address Definition LBC Bank/Chip Select Notes F200 0016 Reserved 4 1 F200 0017 Reserved 4 1 F200 0018 NAND Flash Chip 2 Control Register 4 3 F200 0019 NAND Flash Chip 2 Select Register 4 3 F200 001A Reserved 4 1 F200 001B Reserved 4 1 F200 001C NAND Flash Chip 2 Presence Register 4 3 F200 001D NAND Flash Chip 2 Status Register 4 3 F200 001E Reserved 4 1 F200 001F Reserved 4 1 F200 0020 Watch
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Register Descriptions Table 3-1 System I/O Memory Map (continued) Address Definition F200 0018 - Reserved LBC Bank/Chip Select Notes 1 F200 0FFF F201 1000 - COM 2 (QUART channel 1) 5 COM 3 (QUART channel 2) 5 COM 4 (QUART channel 3) 5 COM 5 (QUART channel 4) 5 F201 1FFF F201 2000 F201 2FFF F201 3000 F201 3FFF F201 4000 F201 4FFF F201 5000 - Reserved 1 F201 FFFF F202 0000 External PLD Tick Timer Prescaler Register 6 2 F202 0010 External PLD Tick Timer 1 Control Register 6 2 F202 00
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Register Descriptions Table 3-1 System I/O Memory Map (continued) Address Definition LBC Bank/Chip Select Notes F202 0048 External PLD Tick Timer 4 Counter Register 6 2 F202 004C - Reserved 6 1 F203 0000 NAND Chip 1 Data Register 2 3 F203 0001 - Reserved 2 1 F203 1000 NAND Chip 2 Data Register 2 3 F203 1001 - Reserved 2 1 F2FF FFFF F203 0FFF F203 FFFF 1. Reserved for future implementation. 2. 32-bit write only. 3. Byte read/write capable. 3.1.
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Register Descriptions BD_TYPE Board Type. These bits indicate the board type. 00: VME SBC 01: PrPMC 10-11: reserved 3.1.2 SAFE_START ENV Safe Start. This bit reflects the current state of the ENV safe start select switch. A cleared condition indicates that the ENV settings programmed in NVRAM should be used by the firmware. A set condition indicates that firmware should use the safe ENV settings. PCI MODE PCI mode. This bit reflects the current state of the PCI Mode switch.
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Register Descriptions 3.1.3 EEPROM_WP EEPROM Write Protect. This bit is to provide protection against inadvertent writes to the on-board EEPROM devices. Clearing this bit will enable writes to the EEPROM devices. Setting this bit write protects the devices. The devices are write protected following a reset. BRD_RST Board Reset. These bits are used to force a hard reset of the board.
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Register Descriptions 3.1.4 USR2_LED User LED 2. This bit is used to control the planar USR2 LED. A set condition illuminates the LED and a cleared condition extinguishes the LED. USR3_LED User LED 3. This bit is used to control the planar USR3 LED. A set condition illuminates the LED and a cleared condition extinguishes the LED.
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Register Descriptions F_WP_SW Software Flash Bank Write Protect. This bit provides software-controlled protection against inadvertent writes to the flash memory devices. A set condition indicates that the entire flash is write-protected. A cleared condition indicates that the flash bank is not write-protected, only when the HW write-protect bit is not set. This bit is set during reset and must be cleared by the system software to enable writing of the flash devices. MAP_SEL Memory Map Select.
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Register Descriptions 3.1.5 Interrupt Register 1 The MVME4100 provides an Interrupt Register that may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt Table 3-6 Interrupt Register 1 REG Interrupt Register 1 - 0xF200 0004 BIT 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD PHY4 PHY3 PHY2 PHY1 OPER R RESET 0 0 0 0 0 0 0 0 PHY1 TSEC1 PHY Interrupt. If cleared, the TSEC1 interrupt is not asserted.
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Register Descriptions 3.1.6 Interrupt Register 2 The RTC, TEMP sensor and Abort switch interrupts are OR'd together. The MVME4100 provides an Interrupt Register that may be read by the system software to determine which device originated the interrupt. This register also includes bits that allow the interrupt sources to be mask.
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Register Descriptions 3.1.7 Presence Detect Register The MVME4100 provides a Presence Detect Register that may be read by the system software to determine the presence of optional devices. Table 3-8 Presence Detect Register REG Presence Detect Register - 0xF200 0006 BIT 7 6 5 4 3 2 1 0 Field RSVD RSVD ERDY2 ERDY1 RSVD XEP PMC2P PMC1P OPER R RESET 0 0 0 0 0 X X X PMC1P PMC Module 1 Present. If cleared, there is no PMC module installed in site 1.
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Register Descriptions 3.1.8 PCI Bus Status Registers The MVME4100 Status Registers provide PCI bus configuration information for each of the PCI busses. Table 3-9 PCI Bus 1 Status Register REG PCI Bus 1 Status Register - 0xF200 0008 BIT 7 6 5 4 3 2 1 Field RSVD RSVD RSVD RSVD PCI_1_64B PCIX_1 PCI_1_SPD OPER R R R R R R R R RESET 0 0 0 0 1 X 1 0 0 PCI_1_SPD PCI Bus 1 Speed. Indicates the frequency of PCI bus 1.
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Register Descriptions PCI_2_SPD PCI Bus 2 Speed. Indicates the frequency of PCI bus 2. 00: 33 MHz 01: 66 MHz 10: 100 MHz 11: 133 MHz PCIX_2 PCI-X Bus 2. A set condition indicates that bus 2 is operating in PCI-X mode. Cleared indicates PCI mode. PCI_2_64B PCI Bus 2 64-bit. A set condition indicates that bus 2 is enabled to operate in 64-bit mode. Cleared indicates 32-bit mode. 5.0V_VIO 5.0V VIO Enabled. This bit set indicates that the PMC bus (PCI Bus 2) is configured for 5.0V VIO. 3.3V_VIO 3.
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Register Descriptions 3.1.9 NAND Flash Chip 1 Control Register The MVME4100 provides a Control Register for the NAND Flash device. Table 3-12 NAND Flash Chip 1 Control Register REG NAND Flash Chip 1 Control Register - 0xF200 0010 BIT 7 6 5 4 3 2 1 0 Field CLE ALE WP RSVD RSVD RSVD RSVD RSVD OPER R/W RESET 0 0 0 0 0 R 0 1 0 WP Write Protect. If cleared, WP is not asserted when the device is accessed. If set, WP is asserted when the device is accessed.
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Register Descriptions CE4 Chip Enable 4. If cleared, CE4 is not asserted when the device is accessed. If set, CE4 is asserted when the device is accessed. CE3 Chip Enable 3. If cleared, CE3 is not asserted when the device is accessed. If set, CE3 is asserted when the device is accessed. CE2 Chip Enable 2. If cleared, CE2 is not asserted when the device is accessed. If set, CE2 is asserted when the device is accessed. CE1 Chip Enable 1. If cleared, CE1 is not asserted when the device is accessed.
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Register Descriptions 3.1.12 NAND Flash Chip 1 Status Register The MVME4100 provides a Status Register for the NAND Flash device. Table 3-15 NAND Flash Chip 1 Status Register REG NAND Flash Chip 1 Status Register - 0xF200 0015 BIT 7 6 5 4 3 2 1 0 Field RB1 RB2 RB3 RB4 RSVD RSVD RSVD RSVD OPER R RESET 1 1 1 1 0 0 0 0 RB4 Ready/Busy 4. If cleared, Device 4 is busy. If set, device 4 is ready. RB3 Ready/Busy 3. If cleared, Device 3 is busy. If set, device 3 is ready.
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Register Descriptions WP Write Protect. If cleared, WP is not asserted when the device is accessed. If set, WP is asserted when the device is accessed. ALE Address Latch Enable. If cleared, ALE is not asserted when the device is accessed. If set, ALE is asserted when the device is accessed. CLE Command Latch Enable. If cleared, CLE is not asserted when the device is accessed. If set, CLE is asserted when the device is accessed. RSVD Reserved for future implementation. 3.1.
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Register Descriptions 3.1.15 NAND Flash Chip 2 Presence Register The MVME4100 provides a Presence Register for the NAND Flash device. Table 3-18 NAND Flash Chip 2 Presence Register REG NAND Flash Chip 2 Presence Register - 0xF200 001C BIT 7 6 5 4 3 2 1 0 Field C2P RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPER R RESET X 0 0 0 0 0 0 0 C2P Chip 2 Present. If cleared, chip 1 is not installed on the board. If set, chip 2 is installed on the board.
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Register Descriptions RB1 Ready/Busy 1. If cleared, Device 1 is busy. If set, device 1 is ready. RSVD Reserved for future implementation. 3.1.17 Watch Dog Timer Load Register The MVME4100 provides a watch dog timer load register. Table 3-20 Watch Dog Timer Load Register REG Watch Dog Timer Control Register - 0xF200 0020 BIT 7 Field Load OPER R/W RESET 0 LOAD 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Counter Load.
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Register Descriptions SYSRST System Reset. If cleared a board-level reset is generated when a time-out occurs. If set, a VMEbus SYSRST is generated when a time-out occurs. If MVME4100 is SYSCON then a local reset will also result in a VMEbus SYSRST. EN Enable. If cleared the watch dog timer is disabled. If set the watch dog timer is enabled. RSVD Reserved for future implementation. 3.1.19 Watch Dog Timer Resolution Register The MVME4100 provides a watch dog timer resolution register.
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Register Descriptions 10: 2 ms 11: 4 ms 12: 8 ms 13: 16 ms 14: 32 ms 15: 64 ms RSVD Reserved for future implementation. 3.1.20 Watch Dog Timer Count Register The MVME4100 provides a watch dog timer count register. Table 3-23 Watch Dog Timer Count Register REG Watch Dog Timer Counter Register - 0xF200 0026 BIT 15:0 Field Count OPER R/W RESET 03FF COUNT Count. These bits define the watch dog timer count value.
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Register Descriptions 3.1.21 PLD Revision Register The MVME4100 provides a PLD revision register that can be read by the system software to determine the current revision of the timers/registers PLD. Table 3-24 PLD Revision Register REG PLD Revision Register - 0xF200 0030 BIT 7 Field PLD_REV OPER R RESET 01 PLD_REV 6 5 4 3 2 1 0 8-bit field containing the current timer/register PLD revision. The revision number starts with 01. 3.1.
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Register Descriptions dd Day vv Version of the day 3.1.23 Test Register 1 The MVME4100 provides a 32-bit general purpose read/write register which can be used by software for PLD test or general status bit storage. Table 3-26 Test Register 1 REG Test Register 1 - 0xF200 0038 BIT 31:0 Field TEST1 OPER R/W RESET 0000 TEST1 General purpose 32-bit R/W field. 3.1.24 Test Register 2 The MVME4100 provides a second 32-bit test register that reads back the complement of the data in Test Register 1.
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Register Descriptions TEST2 A read from this address will return the complement of the data pattern in Test Register 1. A write to this address will write the uncomplemented data to register TEST1. 3.1.25 External Timer Registers The MVME4100 provides a set of tick timer registers for access to the four external timers implemented in the timers/registers PLD. Note that these registers are 32-bit registers and are not byte writable.
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Register Descriptions 3.1.25.
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Register Descriptions 3.1.25.3 Compare Registers The tick timer counter is compared to the Compare Register. When they are equal, the tick timer interrupt is asserted and the overflow counter is incremented. If the clear-on-compare mode is enabled the counter is also cleared.
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Register Descriptions 3.1.25.4 Counter Register When enabled the tick timer counter register increments every microsecond. software may read or write the counter at any time. Table 3-31 Tick Timer Counter Register Tick Timer 1 Counter Register - 0xF202 0018 (32 bits) Tick Timer 2 Counter Register - 0xF202 0028 (32 bits) Tick Timer 3 Counter Register - 0xF202 0038 (32 bits) REG Tick Timer 4 Counter Register - 0xF202 0048 (32 bits) BIT 31 Field Tick Timer Counter Value OPER R/W RESET 0 … 0 3.1.
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Register Descriptions 52 MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
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Chapter 4 Programming Details 4.1 Overview This chapter includes additional programming information for the MVME4100. Items discussed include: 4.
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Programming Details Bill of Materials. Each option and the corresponding default setting are described in the following table. Refer to the MPC8548E reference manual, listed in Appendix B, Related Documentation, Manufacturers’ Documents on page 85 for additional details and/or programming information.
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Programming Details Table 4-1 MPC8548E POR Configuration Settings (continued) MPC8548E Signal Select Option Default POR Setting TSEC1_TXD[0], TSEC1_TXD[7] Fixed 10 TSEC1_TCD[6:4] Fixed 111 Description State of Bit vs.
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Programming Details Table 4-1 MPC8548E POR Configuration Settings (continued) MPC8548E Signal Select Option Default POR Setting TSEC1_TCD[3:1] Fixed 111 TSEC2_TXD[0], TSEC2_TXD[7] TSEC2_TXD[1, TSEC2_RX_ER] 56 Fixed Fixed 10 11 Description State of Bit vs. Function I/O port selection 000 Reserved 001 Reserved 010 Reserved 011 Serial Rapid IO x4 (2.5 Gbps); PCI Express x4 100 Serial Rapid IO x4 (1.25 Gbps); PCI Express x4 101 Serial Rapid IO x4 (3.
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Programming Details Table 4-1 MPC8548E POR Configuration Settings (continued) MPC8548E Signal Select Option Default POR Setting TSEC3_TXD[0], TSEC3_TXD[1] Fixed 10 TSEC3_TXD[2] TSEC4_TXD[0], TSEC4_TXD[7] TSEC4_TXD[2] LA[27] Fixed Fixed Fixed Fixed 0 10 1 1 Description State of Bit vs.
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Programming Details Table 4-1 MPC8548E POR Configuration Settings (continued) MPC8548E Signal Select Option Default POR Setting LA[28:31] Resistors 1000 533 MHz LWE[0] LWE[1:3]_L 58 PLD PLD 1 111 Description State of Bit vs.
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Programming Details Table 4-1 MPC8548E POR Configuration Settings (continued) MPC8548E Signal Select Option Default POR Setting LBCTL, LALE, LGPL2 Resistors 101 LGPL3, LGPL5 MSRCID0 MSRCID1 Fixed Fixed Fixed 11 1 1 Description State of Bit vs. Function e500 core clock PLL ratio (e500 core:CCB clock) 000 4:1 001 9:2 (4.5:1) 010 1:1 011 3:2 (1.5:1) 100 2:1 101 5:2 (2.5:1) 110 3:1 111 7:2 (3.
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Programming Details 4.3 MPC8548E Interrupt Controller The MVME4100 uses the MPC8548E integrated programmable interrupt controller (PIC) to manage locally generated interrupts. Currently defined external interrupting devices and interrupt assignments, along with corresponding edge/levels and polarities, are shown in the following table.
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Programming Details 4.4 Local Bus Controller Chip Select Assignments The following table shows local bus controller (LBC) bank and chip select assignments for the MVME4100 board.
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Programming Details 4.5 I2C Device Addresses A two-wire serial interface is provided by an I2C compatible serial controller integrated into the MPC8548E. The MPC8548E I2C controller is used by the system software to read the contents of the various I2C devices located on the MVME4100. The following table contains the I2C devices used for the MVME4100 and their assigned device addresses.
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Programming Details 4.7 VPD EEPROM The MVME4100 board provides an 8 KB dual address serial EEPROM containing Vital Product Data (VPD) configuration information specific to the MVME4100. Typical information that may be present in the EEPROM may include: manufacturer, board revision, build version, date of assembly, memory present, options present, L2 cache information, etc. The VPD EEPROM is hardwired to have a device ID as shown in Table 4-4 on page 62.
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Programming Details 4.10 Flash Memory The MVME4100 is designed to provide 128 MB of soldered-on NOR flash memory. Two +3.0 V devices are configured to operate in 16-bit mode to form a 32-bit flash bank. This flash bank is also the boot bank and is connected to LBC Chip Select 0 and 1. The NOR flash is accessed via the MPC8548E local bus. The next table shows memory size and device IDs.
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Programming Details 4.11.1 PCI IDSEL and Interrupt Definition Each PCI device has an associated address line connected via a resistor to its IDSEL pin for Configuration Space accesses. The following table shows the IDSEL assignments for the PCI devices and slots on each of the PCI busses on the board along with the corresponding interrupt assignment to the PIC external interrupt pins.
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Programming Details The following table shows the Vendor ID and the Device ID for each of the planar PCI devices on the MVME4100. Table 4-9 Planar PCI Device Identification Function Device Vendor ID Device ID System Controller MPC8548E 0x1957 0x0012 PCI-X to PCI-X Bridge PCI6520 0x10B5 0x6520 VME Controller TSi148 0x10E3 0x0148 USB Controller μPD720101 0x1033 0x0035 4.11.
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Programming Details 4.12.1 MRAM The MVME4100 provides 512 K bytes of fast non-volatile storage in the form of MRAM (Magnetoresistive Random Access Memory). The MRAM is directly accessible by software in the same manner as the DRAM (that means using processor load and store instructions). The only difference is that the MRAM retains its contents even if the board is power cycled. The MRAM is accessed through the LBC. The MRAM may be write protected by hardware switches and/or hardware registers.
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Programming Details 4.12.4 LBC Timing Parameters The following table defines the timing parameters for the devices on the local bus. Table 4-11 LBC Timing Parameters 0 1 4 5 6 NOR Flash 2 NAND Flash 3 NOR Flash MRAM CSR UART Timers LBCTLD 0 0 0 0 0 0 0 CSNT 1 1 1 1 0 1 0 ACS 0 0 0 0 0 0 0 XACS 0 0 0 0 0 0 0 SCY 4 4 2 1 5 3 5 SETA 0 0 0 0 0 0 0 TRLX 0 0 1 1 0 0 0 EHTR 0 0 0 0 0 0 0 EAD 0 0 0 0 0 0 0 4.12.
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Programming Details 4.13 Clock Distribution The clock function generates and distributes all of the clocks required for system operation. The PCI-E clocks are generated using a four output differential clock driver. The PCI/PCI-X bus clocks are generated using a MPC9855 clock generator. Additional clocks required by individual devices are generated near the devices using individual oscillators. The following table lists the clocks required on the MVME4100 along with their frequency and source.
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Programming Details 4.13.1 System Clock The system clock is driven by an oscillator. The following table defines the clock frequency. Table 4-13 Clock Frequencies SYSCLK Core MXP (Platform) DDR2 LB 66.67 MHz 1.3 GHz 533 MHz 266 MHz 33 MHz 4.13.2 Real Time Clock Input The RTC clock input is driven by 1 MHz clock generated by the Control and Timers PLD. This provides a fixed clock reference for the MPC8548E PIC timers which software can use as a known timing reference. 4.13.
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Appendix A A Programmable Configuration Data A.1 Overview This appendix provides data and specifications pertaining to programmable parts used on the MVME4100. The board is shipped after the programmable parts have been programmed through ATE or boundary scan according to the In-Circuit Test specifications. Table A-1 Programmable Devices A.
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Programmable Configuration Data A.3 Vital Product Data (VPD) Introduction The data listed in the following tables are for general reference information. The VPD identifies board information that may be useful during board initialization, configuration and verification. This section includes information on how to perform various tasks to read, modify and correct Vital Product Data, as well as specific format and content information for this product. Information that is contained in the VPD includes: A.
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Programmable Configuration Data A.6 How to Fix Corrupted VPD Information If you encounter corrupted VPD information, use the following method to fix the corrupted data: A.7 z The firmware is designed to reach the prompt with bad VPD. z Use the vpdEdit command to fix the VPD. What if Your Board Has the Wrong VPD? If your board has the wrong VPD information, the following occurs: A.8 z No warning message is displayed. z Incorrect VPD information is seen as correct by the firmware.
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Programmable Configuration Data * This function's purpose is to generate the CRC for the * passed VPD SROM buffer.
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Programmable Configuration Data crcValue <<= 1; if (msbDataBitValue ^ (dataByte & 1)) { crcValue ^= 0x04c11db6; crcValue |= 1; } dataByte >>= 1; } } crcValueFlipped = 0; for (index = 0; index < 32; index++) { crcValueFlipped <<= 1; dataBitValue = crcValue & 1; crcValue >>= 1; crcValueFlipped += dataBitValue; } crcValue = crcValueFlipped ^ 0xffffffff; return (crcValue); } MVME4100 Single Board Computer Programmer’s Reference (6806800H19B) 75
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Programmable Configuration Data A.10 VPD Contents for MVME4100 Boards The following tables describe the VPD data to be programmed into U49. Table A-3 contains only the static VPD data and Table A-4 on page 83 contains only the variable VPD data. This information is subject to change (under authority of an engineering change order). If a difference is noted between either or these tables and your board, please contact your support representative to determine which is accurate.
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Programmable Configuration Data Table A-3 Static VPD Contents (continued) Offset (HEX) Data (HEX) Field Type Description 12 xx ASCII Product Identifier. 13 xx 14 xx 15 xx 16 xx 17 xx 18 xx 19 xx 1A xx 1B xx 1C xx 1D xx 1E xx 1F xx 20 xx 21 xx 22 xx 23 xx 24 xx 25 xx 26 02 Refer to Table A-4. BINARY Factory Assembly Number. Refer to Notes 1 and 2.
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Programmable Configuration Data Table A-3 Static VPD Contents (continued) Offset (HEX) Data (HEX) Field Type Description 28 xx ASCII Factory Assembly Number. 29 xx 2A xx 2B xx 2C xx 2D xx 2E xx 2F xx 30 xx 31 xx 32 xx 33 xx 34 xx 35 03 Refer to Table A-4. BINARY **Serial number to be filled in. Refer to Notes 2 and 3.
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Programmable Configuration Data Table A-3 Static VPD Contents (continued) Offset (HEX) Data (HEX) Field Type Description 40 03 BINARY Four bytes containing the SYSCLK frequency. 41 F9 42 40 43 AA 44 01 BINARY First Processor 45 08 BINARY Ethernet MAC Address Packet 46 07 BINARY # of bytes 47 xx BINARY Six bytes containing the lowest Ethernet address.
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Programmable Configuration Data Table A-3 Static VPD Contents (continued) 80 Offset (HEX) Data (HEX) Field Type Description 59 xx BINARY Six bytes containing the next Ethernet address. 5A xx 5B xx 5C xx 5D xx 5E xx 5F 02 BINARY Ethernet Controller 2 60 08 BINARY Ethernet MAC Address Packet 61 07 BINARY # of bytes 62 xx BINARY Six bytes containing the highest Ethernet address.
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Programmable Configuration Data Table A-3 Static VPD Contents (continued) Offset (HEX) Data (HEX) Field Type Description 70 0A BINARY EPROM CRC When computing the CRC this field (4 bytes) is set to zero. This CRC only covers the range as Integer (4byte). Refer to Vital Product Data CRC Calculation on page 73.
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Programmable Configuration Data Table A-3 Static VPD Contents (continued) Offset (HEX) Data (HEX) Field Type Description 86 00 BINARY Vendor Identifier 87 EC 88 D5 BINARY Device Identifier 89 51 8A 08 BINARY Single device width in bits 8B 01 BINARY Number of devices or sockets present 8C 01 BINARY Number of interleave columns 8D 08 BINARY Column width in bits 8E 08 BINARY Minimum write/erase data width in bits 8F 02 BINARY Flash bank number 90 2D BINARY Flash acce
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Programmable Configuration Data The "xx" in Table A-4 at address 0x32 represents the assembly revision letter (A=41, B=42, etc.).
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Programmable Configuration Data Table A-4 Variable VPD Contents (continued) Offset (Hex) 84 MVME4100-0171 MVME4100-0173 0106855E03x 0106855E04x 2A 30 30 2B 36 36 2C 38 38 2D 35 35 2E 35 35 2F 45 45 30 30 30 31 33 34 32 XX XX 33 00 00 34 00 00 - - - 40 03 03 41 F9 F9 42 40 40 43 AA AA - - - 91 0F 0F MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
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Appendix B B Related Documentation B.1 Emerson Network Power - Embedded Computing Documents The Emerson Network Power - Embedded Computing publications listed below are referenced in this manual. You can obtain electronic copies of Emerson Network Power - Embedded Computing publications by contacting your local Emerson sales office. For documentation of final released (GA) products, you can also visit the following website: www.emersonnetworkpower.
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Related Documentation Table B-2 Manufacturer’s Publications (continued) Document Title and Source Publication Number Atmel Corporation 2-Wire Serial EEPROM 5174B-SEEPR-12/06 32K (4096 x 8), 64K (8192 x 8) AT24C32C, AT24C64C 2-Wire Serial EEPROM Rev. 1116K-SEEPR-1/04 512K (65,536 x 8) AT24C512 NEC Corporation Data Sheet S16265EJ3V0DS00 μPD720101 April 2003 USB2.0 Host Controller Freescale Corporation MPC8548E Integrated Host Processor Reference Manual MPC8548ERM Rev.
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Related Documentation Table B-2 Manufacturer’s Publications (continued) Document Title and Source Publication Number Maxim Integrated Products DS1375 Serial Real-Time Clock REV: 121203 MAX3221E/MAX3223E/MAX3243E ±15kV ESD-Protected, 1μA, 3.0V to 5.
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Related Documentation Table B-2 Manufacturer’s Publications (continued) Document Title and Source Publication Number Broadcom Corporation BCM5482S 5482S-DS06-R 10/100/1000BASE-T Gigabit Ethernet Transceiver 2/15/07 PLX Technology PCI6520 Version 2.0 PCI-X to PCI-X Bridge Databook B.3 Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided.
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Related Documentation Table B-3 Related Specifications (continued) Organization and Standard Document Title PCI Special Interest Group PCI Local Bus Specification, Revision 2.2 PCI Rev 2.2 December 18, 1998 PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a PCI-X EM 2.0a PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0a PCI-X PT 2.0a August 22, 2003 July 22, 2003 Institute for Electrical and Electronics Engineers, Inc.
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Related Documentation 90 MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
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HOW TO REACH LITERATURE AND TECHNICAL SUPPORT: Tempe, Arizona, USA 1 800 759 1107 1 602 438 5720 Munich, Germany +49 89 9608 0 For literature, training, and technical assistance and support programs, visit www.emersonnetworkpowerembeddedcomputing.com Emerson Network Power. The global leader in enabling Business-Critical Continuity™ AC Power Systems Connectivity DC Power Systems Embedded Computing Embedded Power Integrated Cabinet Solutions www.emersonnetworkpowerembeddedcomputing.