Technical data

Register Descriptions
MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
49
3.1.25.2 Control Registers
Table 3-29 Tick Timer Control Registers
REG
Tick Timer 1 Control Register - 0xF202 0010 (32 bits)
Tick Timer 2 Control Register - 0xF202 0020 (32 bits)
Tick Timer 3 Control Register - 0xF202 0030 (32 bits)
Tick Timer 4 Control Register - 0xF202 0040 (32 bits)
BIT 31 … 11 10 9 8 7 6 5 4 3 2 1 0
Field R
S
V
D
…R
S
V
D
I
N
T
S
C
I
N
T
E
N
I
N
T
OVF R
S
V
D
C
O
V
F
C
O
C
E
N
C
OPER R/W
RESET 0 … 0 0 0 0 00000000
ENC Enable counter. When the bit is set the counter increments
When the bit is cleared the counter does not increment.
COC Clear Counter on Compare. When the bit is set the counter is reset to 0 when it compares
with the compare register.
When the bit is cleared the counter is not reset.
COVF Clear Overflow Bits. The overflow counter is cleared when a 1 is written to this bit.
OVF Overflow Bits. These bits are the output of the overflow counter. The overflow counter is
incremented each time the tick timer sends an interrupt to the local bus interrupter. The
overflow counter can be cleared by writing a 1 to the COVF bit.
ENINT Enable Interrupt. When the bit is set the interrupt is enabled.
When the bit is cleared the interrupt is not enabled.
CINT Clear Interrupt.
INTS Interrupt Status.
RSVD Reserved for future implementation.