Endura KP915GV Product Manual www.radisys.
KP915GV Product Manual Copyright © 2005 by RadiSys Technology (Ireland) Ltd. All rights reserved. EPC and RadiSys are registered trademarks of RadiSys Corporation. ASM, Brahma, DAI, DAQ, MultiPro, SAIB, Spirit, and ValuePro are trademarks of RadiSys Corporation. DAVID, MAUI, OS-9, OS-9000, and SoftStax are registered trademarks of RadiSys Microware Communications Software Division, Inc. FasTrak, Hawk, and UpLink are trademarks of RadiSys Microware Communications Software Division, Inc.
KP915GV Product Manual Preface Revision History Revision history No. Date Description 1.0 September 2005 • 2.0 December 2005 • First Release Updates to clarify jumper default positioning, non-support for S/PDIF In and Out on board, BIOS update to P28 version, and editorial changes to some tables. Added details to OEM Features section. No functional changes. Notational Conventions This manual uses the following conventions: • Screen text and syntax strings appear in this font.
KP915GV Product Manual Safety and Approval Notices Safety and approval notices Item Battery LAN (Local Area Network) Connector Description This product contains a lithium cell. • When removing or replacing the lithium cell, do not use a conductive instrument as a short-circuit may cause the cell to explode. Always replace the cell with one of the same type. This product uses a CR2032 cell. Dispose of a spent cell promptly – do not recharge, disassemble or incinerate. Keep cells away from children.
KP915GV Product Manual Contents 1 OVERVIEW ................................................................................................................ 10 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.5 Accessories ………………………………………………………………………………………….. 11 Motherboard Layout ................................................................................................................12 Block Diagram....................................................................................................
KP915GV Product Manual 4 MOTHERBOARD BIOS ............................................................................................. 51 4.1 BIOS Features ........................................................................................................................51 4.2 Post and Boot ………………………………………………………………………………………..51 4.2.1 Hotkeys ...................................................................................................................................52 4.
KP915GV Product Manual B CONTROL REGISTERS .......................................................................................... 111 B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 B.10 Index Register ....................................................................................................................... 111 Watchdog Control ................................................................................................................. 111 Watchdog Kick .........................................
KP915GV Product Manual Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. KP915GV Board Layout.............................................................................................12 KP915GV Block diagram ...........................................................................................14 Jumpers .....................................................................................................................
KP915GV Product Manual Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Complex Programmable Logic Device (CPLD) JTAG Header ....................................124 Serial Port 2 Header ...................................................................................................124 4 X Internal USB Headers ...........................................................................................124 Remote Thermal Sensor.................................................
KP915GV Product Manual 1 Overview Target applications are transaction terminals, medical, test & measurement, gaming, industrial automation applications and other enterprise systems. This motherboard is part of the RadiSys Endura product line, which is specifically targeted at embedded applications with a lifetime of 5 years. Products are fully revision controlled and any change to form, fit or function will be notified to customers in advance via a Product Change Notification procedure.
KP915GV Product Manual Product Specification Overview Item Description Network Intel 82573V (or ‘L) PCI-E Gbit Ethernet controller, co-lay with Intel 82562GZ 10/100 PHY (using the integrated MAC) Available with second Intel 82573V (or ‘L) Gbit Ethernet controller Disks Four SATA ports with locking headers Single Ultra ATA/100 interface supporting hard disks and ATAPI drives One FDD interface Super I/O & H/W Monitor Nat Semiconductor PC8374K Super I/O and Nat Semiconductor LM9600 hardware monitoring
KP915GV Product Manual 1.2 Motherboard Layout Figure 1 shows the layout of the KP915GV motherboard with the major components identified. Figure 1.
KP915GV Product Manual Component Identification Description 1 Super IO 21 Description Ethernet port 1 (option) Description 2 Memory sockets 22 I/O panel USB port 7 42 USB port 3 header 3 Serial port 2 header 23 I/O panel USB port 8 43 USB port 4 header 4 Remote thermal sensor 24 Microphone input jack 44 SMBus header 5 CPU FAN power connector 25 Audio line output jack 45 BIOS ROM writeprotect jumper 6 Chipset GMCH 26 Ethernet controller 1 (option) 46 Clear CMOS Jumper 7 7
KP915GV Product Manual 1.3 Block Diagram Figure 2 shows the block diagram of the KP915GV motherboard. Figure 2. KP915GV Block diagram Prescott, Tejas Pentium 4 EE LGA775 processor Socket T VRD 10.1 4 Phase PWM CK-410 Clock 800/533 FSB CRT 400/533MHz Channel A DDR-2 DIMM1 400/533MHz Channel A DDR-2 DIMM2 Channel B DDR-2 DIMM3 VGA PCIEx16 Port Intel SDVO Card GMCH Grantsdale I/O Panel USB2.0 Port5 USB2.0 Port6 USB2.0 Port7 USB2.
KP915GV Product Manual 1.4 Configuration The majority of the configuration of the motherboard is done through the Setup utility built into the BIOS – discussed later in this document. There are, however, a number of jumpers that control the operation of the motherboard as described below. Some jumpers are not fitted to certain products. Figure 3.
KP915GV Product Manual Recover Mode (No jumper) With no jumper installed on pins 1, 3, and 5 recovery mode is entered. The motherboard does not boot and waits until a valid recovery diskette is detected and then copies new BIOS into the ROM. The motherboard must be powered down and then re-powered with the jumper in the normal position before normal operation can resume. CPLD Write Enabled (Jumper between pins 2 & 4) In this position the contents of the CPLD can be reprogrammed.
KP915GV Product Manual Tamper Switch To make use of the tamper detection logic of the motherboard, connect a momentary switch between pins 18 and 20. The switch should be open when the chassis is closed. 1.4.5 Alternate Power LED The power LED function on the front panel connector is duplicated on the Alternate Power LED connector for use with LEDs cabled to a 3-pin connector. Do not use both the primary (front panel) and alternate connectors simultaneously. 1.5 Installation of CPU 1.5.
KP915GV Product Manual 3. Use thumb & forefinger to hold the hook of the load lever and pull the lever sideways to unlock it. Correct Wrong Warning: DO NOT use finger to lift the locking lever, as injury could occur to the finger and the SKT could be damaged. 4. 5. 18 Lift up the lever. Use thumb to open the load plate. Be careful not to touch the contacts.
KP915GV Product Manual Alignment key Pin 1 indicator 19
KP915GV Product Manual 6. Close the load plate, and slightly push down the tongue side. Slightly push down the tongue side 7. Lower the lever and lock it to the load plate, then the CPU is locked in place. CAUTION Excessive temperatures will severely damage the CPU and system. Therefore, you should install CPU cooling fan and make sure that the cooling fan works normally at all times in order to prevent overheating and damaging to the CPU. Please refer to your CPU fan user guide to install it properly.
KP915GV Product Manual DDR2 Memory bank 128 Pins 112 Pins 3. The plastic clips at both sides of the DIMM slot will lock automatically. CAUTION Be sure to unplug the AC power supply before adding or removing expansion cards or other system peripherals, especially the memory devices, otherwise the motherboard or the system memory might be seriously damaged.
KP915GV Product Manual 1.5.3 Power Supply In order to avoid damaging any devices, make sure that they have been installed properly prior to connecting the power supply. It is recommended that the board be used with a power supply that supports a minimum current load of 0.3A or less on the 5V supply rail and 2A or less on the 3.3V supply rail. This board with CPU and memory may draw as little as 400mA of 5V and 2A of 3.3V during start-up (increases depend on installed devices).
KP915GV Product Manual KP915GV 20-pin ATX power connector: Below is the ATX power supply connector. Make sure that the power supply cable and pins are properly aligned with the connector on the motherboard. Firmly plug the power supply cable into the connector and make sure it is secure. GND PS-ON 5V -5V 5V GND GND GND 5V 12V 5VSB Pw-OK 3.3V -12V +5V GND 3.3V GND 3.
KP915GV Product Manual 2 Motherboard Description 2.1 Processor Support • • • • • • • 2.2 Single processor support Intel® Pentium® 4 Processor 550/551 (3.4GHz 800MHz FSB 1MB L2) Intel® Celeron™ D Processor 340/341 (2.93GHz 533MHz FSB 256Kb L2) Follow the Design Guide in the Intel(R) Pentium(R) 4 Processor in the 775-land Package on 90 nm Process EMTS REV. NO. 1.1 and Grantsdale Chipset (915-GV) Platform Design Guide REV NO. 1.
KP915GV Product Manual 2.3 On board Clocking Block Diagram 14.318MHz CPU CPU 133/200 MHz Diff Pair MCH 133/200 MHz Diff Pair DDR 4 Slots 12 Diff Pair CLKs PCI Express 100 MHz Diff Pair PCI Express x16 SDVO DOT 96 MHz Diff Pair Channel A DDR2 DIMM1 GMCH PCI Express/DMI 100 MHz Diff Pair DIMM2 Grantsdale Channel B DDR2 DIMM1 PCI Express/DMI 100 MHz Diff Pair DIMM2 USB/SIO 48 MHz CK-410 ICH 33 MHz REF 14 MHz FWH 33 MHz FWH Azalia ICH6 24.
KP915GV Product Manual Table 1. KP915GV Motherboard 2.6 Chipset Form Factor PCI-E x16 or ADD2 PCI-E x1 PCI PCI Riser Extension 915GV ATX 1 2 3 N/A • See Figure 5 for slot configurations • ADD2 will be a green connector 915GV Chipset Feature The 915GV is a Memory Controller Hub (MCH) designed for use with the Prescott processors in desktop platforms.
KP915GV Product Manual • • • • • • • • • • • • • • • Support for non-ECC memory, unbuffered DIMMs only, in 256MB, 512MB, 1GB, and 2GB sizes, which may be installed as single DIMMs if desired. If a total of 4GB of DIMMs is installed, the maximum available memory will be approximately 3.24GB, with the balance of the address space being consumed by other resources in the system. I/O Voltage of 1.8V for DDR2. Directly support only two channels of non-ECC DDR2 DIMMs. Supports maximum memory bandwidth of 4.
KP915GV Product Manual Processor ADD2 Figure 5. 2.8 2.
KP915GV Product Manual External Internal Optional* Line in ATAPI 1 Line out ATAPI 3 Line out MIC in ATAPI 2 MIC in Figure 6.
KP915GV Product Manual 2.11 2.12 I/O • Four USB 2.0 ports on I/O panel via two dual stacked USB over RJ45 connectors • Four USB 2.0 ports on internal locking headers • Available with IEEE 1394b controller with support for 1394a • Single port via a header connector • Based on Texas Instruments TSB82AA2 controller and TSB81BA3 transceiver Power Management • Supports ACPI 2.
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KP915GV Product Manual 2.19 2.20 • All configuration is automatic - no stopping on configuration change • Resources freed when unused Operating Systems Support • Windows XP Professional SP2 • Embedded Windows XP Server SP2 • Red Hat Enterprise Linux 4.0 AS • Knoppix Linux 3.7 (selected drivers only) • Windows 2000 Server SP4 • SUSE Linux Enterprise Server 9.
KP915GV Product Manual 2.21 Reliability and Environmental Table 5. Environmental Specifications Characteristic State Value Temperature (ambient) Operating 0oC to +55oC Relative humidity Vibration Operation above +30° C reduces the maximum operational relative humidity. Operating gradient ±5°C per minute Storage -40oC to +85oC, 5°C per minute maximum excursion gradient. Operating 10% to 85% RH non-condensing at +30oC, linearly o decreasing to 5% to 15.5% RH non-condensing at +65 C.
KP915GV Product Manual 2.22 Regulatory Compliance Table 6.
KP915GV Product Manual 3 Specifications 3.1 Product Basis This product based on the Intel® 915GV Express chipset, designed for the Intel® Pentium® 4 processor with Hyper-Threading (HT) Technology in the LGA775 package, and is flexible for specific customer needs. 3.2 Non-Core Integrated Sub-systems 3.2.
KP915GV Product Manual • • • • 36 • PCI Express endpoint • Independent Bus Master logic for eight general purpose streams: Four input and four output • Support three external Codecs • Supports variable length stream slots • Supports multimedia channel, 32-bit sample depth, 192kHz sample rate output • Provides Mic array support • Supports memory-based command/response transport • Allows for non-48kHz sampling output • Support for ACPI Devices States AC-Link for Audio and Telephony cod
KP915GV Product Manual • • • • • External Glue Integration • Integrated Pull-op, Pull down and Series Termination resistors on IDE, processor I/F • Integrated Pull-down and Series resistors on USB Enhanced DMA Controller • Two cascaded 8237 DMA controller • Supports LPC DMA SMBus • Flexible SMBus/SMLink architecture to optimize for ASF • Provides independent manageability bus through SMLink interface • Supports SMBus 2.
KP915GV Product Manual • 3.2.2 5V tolerant buffers on IDE, PCI, and Legacy signals • Integrated 1.
KP915GV Product Manual • • • • • • • Greater than 100 years Data Retention Low Power Consumption • Active Read Current: 6 mA (typical) • Standby Current: 10 µA (typical) Fast Sector-Erase/Byte-Program Operation • Sector-Erase Time: 18 ms (typical) • Block-Erase Time: 18 ms (typical) • Chip-Erase Time: 70 ms (typical) • Byte-Program Time: 14 µs (typical) • Chip Rewrite Time: SST49LF004B: 8 seconds (typical) • Single-pulse Program or Erase • Internal timing generation Two Operation
KP915GV Product Manual STAC9200 Block Diagram SPDIF INPin47 SPDIF Receiver BIT_CLKPin6 SDI Pin8 SYNCPin10 Reset#Pin11 Stream/ Channel Select Stream/ Channel Select Stream/ Channel Select -6dB Digital PC Beep SPDIF Pin48 W SD0 Pin5 AZALIA LINK LOGIC Stream/ Channel Select PCM to SPDIF OUT MUX Stream/ Channel Select Single Bit Loopback (Loop 3) Stream/ Channel Select Stream/ Channel Select DAC BYPASS MODE Stream/ Channel Select MUX Digital Analog vol mute Loop 1 W STEREO ADC Figure 8.
KP915GV Product Manual • 3.3.2 Package 48-pin Lead Free LQFP Hardware Management Interface The LM96000, hardware monitor, has a two wire digital interface compatible with SMBus 2.0. Using an 8-bit Σ∆ ADC, the LM96000 measures: • The temperature of two remote diode connected transistors as well as its own die • The VCCP, 2.5V, 3.3VSBY, 5.0V, and 12V supply (internal scaling resistors). VID[4:0] REGISTER SERIAL BUS INTERFACE VOLTAGE. FAN SPEED. TEMPREATURE.
KP915GV Product Manual 3.3.3 • XOR-tree test mode • Package 24-pin Lead TSSOP Ethernet Interface Either one or two IEEE 802.3 compatible Ethernet ports are available as build options that are based around Intel controllers (82562GZ and 82573V or ‘L) to provide 10/100Mbps and/or 10/100/1000Mbps configuration. Connection to the network is achieved through two RJ45 connectors, available on the I/O (Input/Output) panel, which have integral LED’s to provide Link status information.
KP915GV Product Manual 3.3.4 • Support ASF1.0 and 2.0 alerting • Support Wake On LAN (WOL) and ACPI • Programmable LED functionality • On-chip power control circuitry • Loop-back capabilities • IEEE 802.3ab Auto-Negotiation support and PHY compliance with compatibility • Package 15x15 mm 196 pin TF-BGA Super I/O Interface The motherboard is designed to support the NS PC8374K controller.
KP915GV Product Manual • Heceta6-compatible register set accessible via the LPC interface and SMBus • • • 3.3.4.
KP915GV Product Manual 3.3.4.4 • Lock option for the configuration and data of each output pin • 15 GPIO ports generate IRQ/SMI/SIOPME# for wake-up events; each GPIO has separate: • Enable control of event status routing to IRQ • Enable control of event status routing to SMI • Enable control of event status routing to SIOPME# (via SWC) • Polarity and edge/level selection • Programmable de-bouncing Power Management • Supports ACPI Specification Revision 2.
KP915GV Product Manual 3.3.4.5 • Supports programmable 8-byte sequence “Password” or “Special Keys” for Power Management • Simultaneous recognition of three programmable keys (sequences): “Power”, “Sleep” and “Resume” • Wake-up on mouse movement and/or button click Bus Interface • • LPC Bus Interface • Based on Intel’s LPC Interface Specification Revision 1.
KP915GV Product Manual • • • Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80 IEEE 1284-compliant Parallel Port • ECP, with Level 2 (14 mA sink and source output buffers) • Software or hardware control • Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.
KP915GV Product Manual • • • 3.4 Generates 48 MHz clock • Generates 32.768 KHz internal clock • VSB3 powered • Based on the 14.
KP915GV Product Manual KP915GV Item Description Power Supply FSP350-60PLN/350W Current Meter PROVA CM-01 AC/DC Clamp Meter Drives Powered independently Hard Drive Disk WD Caviar SE 1200/120GB Serial ATA Disk Network On-board (single LAN, not operating) Configuration 1 : Heavy Load Item Description Memory Apacer ELPIDA chip DDR2-400 1GB X4 (P/N: 78.01066.420) Video On-board (8MB shared Memory) Network On-board (single 10/100 LAN, not operating) Intel Pentium 4 at 3.
KP915GV Product Manual Configuration 2 : Light Load Item Description Memory Micron MT8HF3264AY-40EB3 256MB DDR2-400 CL3 X1 Video On-board (8MB shared Memory) Network On-board (single LAN, not operating) Intel Celeron 4 at 2.93GHz with 533MHz Processor Bus Motherboard Current (A) Mode +3.3V +5V +12V -12V +5Vsby Total (W) MS-DOS Prompt without power management 2.96 0.74 0.32 4.14 0.02 0.05 67.48 Windows XP desktop idle 3.06 0.75 0.35 4.08 0.02 0.05 67.
KP915GV Product Manual 4 Motherboard BIOS 4.1 BIOS Features • • • • • • • • • • • • • • • • • • • • • 4.
KP915GV Product Manual and test progress messages are visible. Pressing the 'TAB' key on the keyboard during a Quietboot switches the display to text mode - providing the progress messages. The BIOS will then search for boot devices in the order configured by the BIOS Setup and load an operating system from the first boot device found. Control is then passed to the operating system and the motherboard BIOS plays no further part in the boot except to provide run-time services. 4.2.
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KP915GV Product Manual Note: The Main BIOS level in the figure above is an example only and doesn’t necessarily reflect the latest BIOS on delivered products or available for downloading. 4.3.4.
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KP915GV Product Manual 4.4 Power Management Supports APM and ACPI 2.0 with power states S0, S3, S4 (not S4BIOS), S5 and C0, C1, C2, C3. 4.4.1 ACPI Wake-up Support The next table indicates which events can cause an ACPI wake-up and from which sleep states. Event Power Switch RTC alarm PS2 Mouse/Keyboard USB Device PME WOL 4.
KP915GV Product Manual LED 4.7 CPLD 4.7.1 POST Code Display State Blinking yellow Indicates The motherboard is in sleep state S1 with a message waiting (as determined by ACPI TAPI). Support for character-based LCD panel to display BIOS POST messages and other information. Displays have an 8-bit parallel interface. Text for display is the BIOS Port 80 codes in the format: "BIOS Code xx". This section describes how the LCD character display support is implemented.
KP915GV Product Manual 4.9.1 Normal Mode This is the factory default position the jumper should be in for normal operation of the motherboard. 4.9.2 Configure Mode The Configure mode forces the BIOS into Setup with the manufacturer defaults loaded. The mode should be returned to normal before re-starting. 4.9.3 Recovery Mode The Recovery mode expects a recovery disk in floppy disk drive A and will wait until one is found before performing the recovery operation. 4.10 Update and Recovery Diskette 4.
KP915GV Product Manual NOTE The full-screen logo file must be 640X464 pixels with 16 colors BMP format. 4.12.2 CMOS Default Change The MODBIN6.EXE is the utility that runs at a DOS prompt for binary code manipulation. It allows selection of customized default CMOS (BIOS setup) settings.The process is described below: Execute the MODBIN6.exe • • • 4.13 Load the BIOS bin file by the ‘File’ option. Change the ‘Edit Setup Screen’ to change the default settings.
KP915GV Product Manual 4.14 BIOS Flash Usage Map 4.15 Processor Microcode Support IA32 processors have the capability of correcting specific errata through the loading of an Intelsupplied data block (i.e. microcode update). Below table list the microcode that BIOS store in flash, and will load it into each processor during POST. Name M9DF4304 M9DF4112 M0DF3702 M1DF3414 M0DF320A M10F252C 4.
KP915GV Product Manual Item 1 2 3 4 5 6 98 SMBIOS Data Type 00: BIOS Information BIOS Vendor Phoenix Technologies, LTD BIOS Version 4C7R2BXX Starting Addr Seg E000h BIOS Release Date MM/DD/YYYY BIOS ROM Size 512K Manufacturer ‘RadiSys‘ Product Name ‘Endura KP915GV‘ Type 01: System Version Information Serial Number Type 02: Baseboard Information Type 07: Cache Information ‘‘ ‘‘ UUID FFFFFFFF-FFFFFFFF FFFFFFFF-FFFFFFFF Manufacturer ‘Foxconn‘ Product ‘Endura KP915GV‘ Version
KP915GV Product Manual Item 7 8 9 10 11 SMBIOS Data Type 07: Cache Information Expected Result System Cache Type Data Associativity Depend on CPU Socket Designation L2-Cache Cache Configuration Depend on CPU Maximum Cache Size Depend on CPU Installed Size Depend on CPU Supported SRAM Type Current SRAM Type Depend on CPU Depend on CPU Cache Speed Depend on CPU Error Correction Type 03h(None) System Cache Type Unified Associativity Depend on CPU Slot Designation PCI0 Slot Typ
KP915GV Product Manual Item 12 13 14 15 100 SMBIOS Data Expected Result Slot Length: Other Slot ID: 0004 Slot Characteristics: Provides 3.
KP915GV Product Manual Item 16 17 18 19 20 SMBIOS Data Bank Locator Bank 4/5 Memory Type 0Fh(SDRAM) Type Detail 0080h(Synchronous) Memory Error Information Handle Unknown Total Width Depend on MEM Data Width Depend on MEM Size Depend on MEM Type 17 Memory Form Factor Device Device Set 22 09h(DIMM) 00 Device Locator B1 Bank Locator Bank 6/7 Memory Type 0Fh(SDRAM) Type Detail 0080h(Synchronous) Starting Address Type 19 Memory Array Mapped Ending Address Address Partition Width
KP915GV Product Manual Item 23 4.17 SMBIOS Data Type 127: End-ofTable Post Code Technical Description POST Code CFh Description Test CMOS R/W functionality. C0h Early chipset initialization: -Disable shadow RAM -Disable L2 cache (socket 7 or below) -Program basic chipset registers C1h Detect memory -Auto-detection of DRAM size, type and ECC.
KP915GV Product Manual POST Code 23h 27h 29h 2Dh Description Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead. Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration of the ESCD’s legacy information. Onboard clock generator initialization. Disable respective clock resource to empty PCI & DIMM slots.
KP915GV Product Manual POST Code 75h 77h 7Ah 4.18 • 104 7Fh Switch back to text mode if full screen logo is supported. 82h Call chipset power management hook. If password is set, ask for password. 83h 84h Save all data in stack back to CMOS Initialize ISA PnP boot devices 85h USB final Initialization. 93h Read HDD boot sector information for Trend Anti-Virus code 94h Enable L2 cache Program boot up speed Chipset final initialization.
KP915GV Product Manual 5 Customer Support RadiSys Online Support can be found at www.radisys.com and includes device drivers, BIOS updates, support software and documentation. See the Manuals, Drivers & BIOS section. The next table displays online specifications and reference material: Table 7. References Specification Description Location ACPI Advanced Configuration and Power Interface specification www.acpi.info AGP Advanced Graphics Port Interface Specification www.agpforum.
KP915GV Product Manual A Technical Reference A.1 I/O Map Table 8.
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KP915GV Product Manual A.3 PCI Device Assignments Table 10.
KP915GV Product Manual A.5 ISA Interrupt Allocation While the motherboard does not include an ISA bus, it includes an ISA-compatible interrupt controller (PIC) in order to be compatible with AT standard architecture. The interrupts are allocated as described in the next table. Table 12. ISA Interrupt Allocation A.
KP915GV Product Manual A.7 BIOS Organization The BIOS ROM is a 4or 8Mbit device containing eight or sixteen symmetrical 64KB blocks. The next figure shows how the ROM stores code and control information. The addresses shown refer to the ROM image at the top of the 4GB-address space. Note that the system BIOS segment is compressed in this image. When the BIOS runs, the code is uncompressed in real-time and the resulting code and data image is found at physical address 0E0000h through 0FFFFFh. Figure 11.
KP915GV Product Manual B Control Registers Notes • The following abbreviations are used in register descriptions: R=Read • B.1 RO=Read only R/W=Read/Write W=Write only The MSB (Most Significant Bit) is listed first. Index Register 7 6 5 4 3 2 Version RO B.2 RO 1 0 R/W R/W Index RO RO R/W R/W I/O location: Default: 062h vvvv1010b Version A read-only field containing the software version number for the logic. 0001 Version 1 0010 Version 2 Index Value description.
KP915GV Product Manual Prescale 4-bit value to set the watchdog counter period 0..15 16..
KP915GV Product Manual 1 B.5 Timer is enabled and counting Watchdog Timeout Period 7 6 5 4 3 2 1 0 R/W R/W R/W Watchdog timeout period R/W I/O location: Index Default: R/W R/W R/W R/W 066h 1 11111111b Timeout period B.
KP915GV Product Manual These bits are input only. Writes to these bits have no effect; reads reflect the state of the GPIO port 2 bits 4 and 3 respectively. D104, GPIO Port 1 bits 0 – 4 direction control: GPIO bits 10 – 14 are inputs GPIO bits 10 – 14 are outputs D157, GPIO Port 1 bits 5 – 7 direction control: GPIO bits 15 – 17 are inputs GPIO bits 15 – 17 are outputs D201, GPIO Port 2 bits 0 – 1 direction control: GPIO bits 20 – 21 are inputs GPIO bits 20 – 21 are outputs B.
KP915GV Product Manual B.10 Controller Part Number The controller part number format is 97-xxyy-0v where v is version number (top 4 bits of index register), xx is the byte 2 value and yy is the byte 1 value. BCD encoding is used for all digits. Byte 1 is 36h Byte 2 is 42h. The programmed part number is 97-4236-0v for production motherboards.
KP915GV Product Manual C Connector Descriptions Note 1: Connector views in the following sections are shown from the motherboard side. Note 2: In all tables below the # sign indicates “active low.” C.1 Connector Part Numbers The various motherboard connectors are listed in the next table along with the part number of one of the approved vendors. The list is intended to assist in the selection of mating connectors. Table 14.
KP915GV Product Manual Table 14. Connector part numbers C.
KP915GV Product Manual Table 15. ADD2 Expansion Slot C.3 Pin Signal Pin Signal Pin A27 DVOCD11 B27 DVOCD10 A60 DVOBD5 Signal B60 Pin DVOBD4 Signal A28 +3.3V B28 +3.3V A61 GND B61 GND A29 DVOCD9 B29 DVOCD8 A62 DVOBD3 B62 DVOBD2 A30 DVOCD7 B30 DVOCD6 A63 DVOBD1 B63 DVOBD0 A31 GND B31 GND A64 VDDQ1.5 B64 VDDQ1.5 A32 DVOCCLK# B32 DVOCCLK A65 DVOBHSYNC B65 DVOBVSYNC A33 DVOCD5 B33 DVOCD4 A66 VREFGC B66 VREFGC PCI Expansion Slot12 Table 16.
KP915GV Product Manual 13 Not used but pulled low Not used but pulled high to +5V 15 Not connected 14 C.4 PCI Express x1 Slot Table 17. PCI Express x1 Slot (PCI-E x1) Pin Signal A1 PRSNT1# 16 A2 12V A3 12V A4 GND A5 JTAG2 16 A6 JTAG3 16 A7 JTAG4 16 A8 JTAG5 16 A9 3.3V 16 Not connected Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 Signal 12V 12V RSVD GND SMCLK SMDAT GND 3.3V JTAG1 16 Pin Signal Pin A10 A11 A12 A13 A14 A15 A16 A17 A18 3.
KP915GV Product Manual Table 20. Serial Port Pin SIGNAL 1 2 3 4 DCD SIN SOUT DTR 5 GND Pin 6 7 8 9 SIGNAL DSR RTS CTS RI Table 21. VGA Port Pin 1 2 3 4 5 6 7 8 SIGNAL RED GREEN BLUE NC GND GND GND GND Pin 9 10 11 12 13 14 15 SIGNAL +5V GND NC SDA Horizontal Sync Vertical Sync SCL Table 22. 2 x Dual Stack USB Ports Pin SIGNAL Pin SIGNAL 1 VCC 5 VCC 2 DATA0- 6 DATA1- 3 DATA0+ 7 DATA1+ 4 GND 8 GND Table 23.
KP915GV Product Manual Table 24. 3 x Audio Jack Pin SIGNAL Tip Left Audio Ring Right Audio Sleeve GND Remark L- Line (Line In, Line Out) Table 25. 1394 Header Pin SIGNAL Pin SIGNAL 1 TA1+ 6 TB1- 2 TA1- 7 Power 3 GND 8 Power 4 GND 9 KEY 5 TB1+ 10 GND Table 26.
KP915GV Product Manual Table 27. General Purpose I/O Headers Pin 1 3 SIGNAL GND PWM Pin 2 4 SIGNAL +5V (fused) GPIO20 5 GPIO21 6 GPIO22 7 GPIO10 8 GPIO11 9 GPIO12 10 GPIO13 11 GPIO14 12 GPIO15 13 GPIO16 14 GPIO17 15 17 19 Reserved GND GND 16 18 20 KEY (no pin fitted) GPI23 GPI24 Table 28. Power Supply Connector Pin 11 12 13 14 15 16 17 18 19 20 SIGNAL +3.3V -12V GND PSON# GND GND GND Not Used +5V +5V Pin 1 2 3 4 5 6 7 8 9 10 SIGNAL +3.3V +3.
KP915GV Product Manual Table 30.
KP915GV Product Manual Table 33. Pin 1 3 5 7 9 11 13 15 17 19 Table 34. TPM Header SIGNAL LCLK LFRAME# LRESET# LAD3 VDD LAD0 NC1 NC2 GND LPCPDn Pin 2 4 6 8 10 12 14 16 18 20 Complex Programmable Logic Device (CPLD) JTAG Header Pin 1 2 3 4 5 6 7 8 SIGNAL VCC_STBY CPLD_TDO CPLD_TDI NC KEY PIN CPLD_TMS GND CPLD_TCK Table 35. Serial Port 2 Header Pin 1 DCD SIGNAL 2 Pin SIGNAL DSR 3 RxD 4 RTS 5 TxD 6 CTS 7 9 DTR GND 8 10 RING KEY Table 36.
KP915GV Product Manual Table 37. Remote Thermal Sensor Pin SIGNAL 1 DIODE+ 2 DIODE- Table 38. 3 X Fan Connector Pin SIGNAL 1 2 GND +12V 3 4 TACHO PWM Table 39. SMBus Connector Pin SIGNAL 1 2 3 4 +3.3V DATA CLOCK GND Table 40. PS/2 Keyboard Header Pin 1 2 3 4 SIGNAL +5V (fused) DATA GND CLOCK Table 41.
