Specifications

Computer Architecture and Maintenance (G-Scheme-2014)

clock signal changes twice per transfer, while the data lines change at most once per

transfer. When operating at a high bandwidth, signal integrity limitations constrain the

clock frequency. By using both edges of the clock, the data signals operate with the

same limiting frequency, thereby doubling the data transmission rate.

This technique has been used for microprocessor front side busses, Ultra-3 SCSI,

graphics RAM (the AGP bus and GDDR), main memory (both RDRAM and DDR1

through DDR4), and the HyperTransport bus on AMD's Athlon 64 processors. It is

more recently being used for other systems with high data transfer speed

requirements – as an example, for the output of analog-to-digital converters (ADCs).

DDR should not be confused

with dual channel, in which

each memory channel accesses

two RAM modules

simultaneously. The two

technologies are independent

of each other and many

motherboards use both, by

using DDR memory in a dual

channel configuration.

The 184-pin DDR RAM dual in-line memory modules (DIMMS) only work properly in

a motherboard designed for their use. While this RAM comes in various speeds,

installing a version faster than a motherboard can support is a waste of money, since it

will only run as fast as the motherboard permits. It is visually differentiated from

SDRAM in that SDRAM is a 168-pin DIMM with a double notch at the bottom along

the pins — one notch just off-center, the other offside. The 184-pin DDR SDRAM has a

single off-center notch.

DDR RAM is generally made for processors 1GHz and faster. Designations like PC1600

DDR SDRAM and PC2100 DDR SDRAM coincide with particular FSB and CPU speeds.

RAM manufacturers use different schemes to designate processor speed, and the

various technicalities in RAM designations and standards can be confusing. Computer

users should check their motherboard manual to see what RAM type is compatible

with their system before purchasing memory.

SDR SDRAM (Single Data Rate synchronous DRAM)

Prepared By – Prof. Manoj.kavedia (9860174297 – 9324258878 ) (www.kavediasir.yolasite.com)