Specifications

BIOSEP-MVP4G
Page 4-15
Disabled: Normal Setting.
Enabled: If you have plugged in some Legacy cards to the system and they
were recorded into ESCD (Extended System Configuration Data), you can
set this field to Enabled in order to clear ESCD.
CPU to PCI Write Buffer: When enabled, up to four D words of data can be
written to the PCI bus without interruting the CPU. When disabled, a write buffer is
not used and the CPU read cycle will not be completed until the PCI bus signals that
it is ready to receive the data.
The Choice: Enabled, Disabled.
PCI Dynamic Bursting: When Enabled, data transfers on the PCI bus, where
possible, make use of the high-performance PCI bust protocol, in which graeater
amounts of data are transferred at a single command.
The Choice: Enabled, Disabled.
PCI Master 0 WS Write: When Enabled, writes to the PCI bus are command with
zero wait states.
The Choice: Enabled, Disabled.
PCI Delay Transaction: The chipset has an embedded 32-bit posted write buffer to
support delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
The Choice: Enabled, Disabled.
PCI #2 Access #1 Retry: This item allows you enabled/disable the PCI #2 Access
#1 Retry.
The Choice: Enabled, Disabled.
Assign IRQ For USB: This item allows BIOS to assign whether IRQ is with USB
or not. If you have not connect the USB device. Can release the IRQ for other
device.
The default is Enabled.
Enalbed: Provides IRQ for USB device.
Disabled: Release IRQ for other device.