User`s guide

Cache Internal cache in the 586-class processor;
256KB, 512KB, or 1MB of external cache
installed on 32K x 8, 64K x 8, or 128K x 8,
3.3 volt, 15ns cache SRAM DIP chips and
two 32K x 8,28-pin, 5 volt, 15ns tag chips
(one for the tag and one for the ALT bit);
internal and external cache controllable
through SETUP
Math
Math coprocessor built into the 586-class
coprocessor processor
Clock/
calendar
Real-time clock, calendar, and CMOS
RAM socketed on main system board with
integrated backup battery
Controllers
PCI chipset Provides PCI caching, memory, and
control for the PCI bus and the
two-channel PCI IDE interface (described
under “Hard disk and other IDE devices”
below); integrated PCI bridge translates
CPU bus cycles to PCI bus cycles and
CPU-to-PCI memory write cycles to PCI
burst cycles
Video
S3™ Trio64™ PCI VGA controller with
integrated 24-bit RAMDAC, 64-bit DRAM
interface; includes power-saving and
multimedia features; supports resolutions
up to 1280 x 1024 in 16 colors with 1MB of
video RAM, increasing to 256 colors with
2MB of video RAM; True Color support in
the 640 x 480 resolution
Specifications A-3