ETM26E-03 Application Manual Real Time Clock Module RX-8801SA/JE
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RX - 8801 SA / JE Contents 1. Overview.......................................................................................................................... 1 2. Block Diagram ................................................................................................................. 1 3. Terminal description ........................................................................................................ 2 3.1. Terminal connections...........................................................
RX − 8801 SA / JE I2C-Bus Interface Real-time Clock Module RX − 8801 SA / JE • • • • • • • • • • Features built-in 32.768 kHz DTCXO, High Stability. 2 Supports I C-Bus's high speed mode (400 kHz) Alarm interrupt function for day, date, hour, and minute settings Fixed-cycle timer interrupt function (Seconds, minutes) Time update interrupt function (FOE and FOUT pins) 32.768 kHz output with OE function (from 2000 to 2099) Auto correction of leap years Wide interface voltage range: 2.2 V to 5.
RX − 8801 SA / JE 3. Terminal description 3.1. Terminal connections RX − 8801 SA RX − 8801 JE 1. T1 (CE) 14. N.C. 2. SCL 13. SDA 3. FOUT 12. T2 (VPP) 4. N.C. 11. GND 5. TEST 10. / INT 6. VDD 9. N.C. 7. FOE 8. N.C. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. /INT GND T2 (VPP ) SDA N.C. T1 (CE) SCL FOUT N.C. FOE #1 # 20 # 10 # 11 20. 19. 18. 17. 16. 15. 14. 13. 12. 11. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD VSOJ − 20pin SOP − 14pin 3.2.
RX − 8801 SA / JE 4. Absolute Maximum Ratings GND = 0 V Item Symbol Condition Supply voltage Input voltage (1) Input voltage (2) Output voltage (1) Output voltage (2) VDD VIN1 VIN2 VOUT1 VOUT2 Storage temperature TSTG Between VDD and GND FOE pin SCL and SDA pins FOUT pin SDA and /INT pins When stored separately, without packaging Rating −0.3 GND−0.3 GND−0.3 GND−0.3 GND−0.3 to to to to to Unit +6.5 VDD+0.3 +6.5 VDD+0.3 +6.5 V V V V V −55 to +125 °C 5.
RX − 8801 SA / JE 7. Electrical Characteristics 7.1.
RX − 8801 SA / JE * Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C 7.2. AC Characteristics Item Symbol SCL clock frequency Start condition setup time Start condition hold time Data setup time Data hold time Stop condition setup time Bus idle time between start condition and stop condition Time when SCL = "L" Time when SCL = "H" Rise time for SCL and SDA Fall time for SCL and SDA Allowable spike time on bus FOUT duty Condition Min. Typ. fSCL Max.
RX − 8801 SA / JE 8. Use Methods 8.1. Overview of Functions 1) Clock functions This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. 2) Fixed-cycle interrupt generation function The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.
RX − 8801 SA / JE 8.2. Description of Registers 8.2.1.
RX − 8801 SA / JE 8.2.2. Control register (Reg F) Address Function F bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Control Register CSEL1 CSEL0 UIE TIE AIE { { RESET (Default) (0) (1) (−) (−) (−) (0) (0) (−) ∗1) The default value is the value that is read (or is set internally) after powering up from 0 V. ∗2) "o" indicates write-protected bits. A zero is always read from these bits. ∗3) "−" indicates no default value has been defined.
RX − 8801 SA / JE 3) AIE ( Alarm Interrupt Enable ) bit When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated.
RX − 8801 SA / JE 8.2.3. Flag register (Reg-E) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 E Flag register { { UF TF AF { VLF VDET (Default) (0) (0) (−) (−) (−) (0) (1) (1) ∗1) The default value is the value that is read (or is set internally) after powering up from 0 V. ∗2) "o" indicates write-protected bits. A zero is always read from these bits. ∗3) "−" indicates a default value is undefined.
RX − 8801 SA / JE 8.2.4. Extension register (Reg-D) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 (Default) (0) (−) (−) (−) (0) (0) (−) (−) ∗1) ∗2) ∗3) The default value is the value that is read (or is set internally) after powering up from 0 V. "o" indicates write-protected bits. A zero is always read from these bits. "−" indicates a default value is undefined.
RX − 8801 SA / JE 8.2.5. RAM register (Reg - 7) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7 RAM • • • • • • • • • This RAM register is read/write accessible for any data in the range from 00 h to FF h. 8.2.6. Clock counter (Reg - 0 ∼ 2) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 2 SEC MIN HOUR { { 40 40 { { 20 20 20 10 10 10 8 8 8 4 4 4 2 2 2 1 1 1 ∗) "o" indicates write-protected bits.
RX − 8801 SA / JE 8.2.8. Calendar counter (Reg 4 to 6) ∗) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 5 6 DAY MONTH YEAR { { 20 { { { 80 40 20 10 10 10 8 8 8 4 4 4 2 2 2 1 1 1 "o" indicates write-protected bits. A zero is always read from these bits. • The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099. • The data format is BCD format.
RX − 8801 SA / JE 8.3. Fixed-cycle Timer Interrupt Function The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14 μs and 4095 minutes. When an interrupt event is generated, the /INT pin goes to low level and "1" is set to the TF bit to report that an event has occurred.
RX − 8801 SA / JE 8.3.2. Related registers for function of time update interrupts. Address Function bit 7 bit 6 B C D E F ∗1) ∗2) Timer Counter 0 Timer Counter 1 Extension Register Flag Register Control Register bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 • TE TF TIE 8 2048 4 1024 FSEL1 FSEL0 2 512 TSEL1 1 256 TSEL0 AF { VLF VDET AIE { { RESET 128 • 64 • 32 • TEST WADA USEL { { UF CSEL1 CSEL0 UIE "o" indicates write-protected bits. A zero is always read from these bits.
RX − 8801 SA / JE 5) TIE (Timer Interrupt Enable) bit When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). Data Description TIE 1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status remains Hi-Z).
RX − 8801 SA / JE 8.4. Time Update Interrupt Function The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's UIE bit is "1".
RX − 8801 SA / JE 8.4.2. Related registers for time update interrupt functions. ∗) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D E F Extension Register Flag Register Control Register TEST WADA USEL UF UIE TE FSEL1 FSEL0 TSEL1 TSEL0 TF AF { VLF VDET TIE AIE { { RESET { { CSEL1 CSEL0 "o" indicates write-protected bits. A zero is always read from these bits.
RX − 8801 SA / JE 8.5. Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred. ∗ Example of /INT operation AIE = " 1 " ( AF = " 0 " → " 1 " ) AF = " 1 " → " 0 " or AIE = " 1 " → " 0 " 8.4.1.
RX − 8801 SA / JE 8.5.2.
RX − 8801 SA / JE 3) AF (Alarm Flag) bit When this flag bit value is already set to "0", occurrence of an alarm interrupt event changes it to "1". When this flag bit value is "1", its value is retained until a "0" is written to it. Data Description AF 0 Write The AF bit is cleared to zero to prepare for the next status detection ∗ Clearing this bit to zero enables /INT low output to be canceled (/INT remains Hi-Z) when an alarm interrupt event has occurred.
RX − 8801 SA / JE 8.6. Reading/Writing Data via the I2C Bus Interface 8.6.1. Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data transfer signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed.
RX − 8801 SA / JE 8.6.3. Starting and stopping I2C bus communications START Repeated START(RESTART) condition condition STOP condition SCL [S] [ Sr ] [P] SDA 0.95 s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1) START condition • The SDA level changes from high to low while SCL is at high level. (2) STOP condition • This condition regulates how communications on the I2C-BUS are terminated. The SDA level changes from low to high while SCL is at high level.
RX − 8801 SA / JE 8.6.4. Data transfers and acknowledge responses during I2C-BUS communications 1) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no longer than 0.95 seconds.) The address auto increment function operates during both write and read operations.
RX − 8801 SA / JE 8.6.6. I2C bus protocol In the following sequence descriptions, it is assumed that the CPU is the master and the RX-8801 is the slave. a. Address specification write sequence Since the RX-8801 includes an address auto increment function, once the initial address has been specified, the RX-8801 increments (by one byte) the receive address each time data is transferred. (1) CPU transfers start condition [S]. (2) CPU transmits the RX-8801's slave address with the R/W bit set to write mode.
RX − 8801 SA / JE 8.7. Backup and Recovery VDD VDET VCLK 0V t R1 tF t R2 Back up Item Max. Unit. − 2.2 V VLOW − 1.6 V tF − Initial power-up time t R1 − Clock maintenance power-up time t R2 Power supply detection voltage ( 1 ) Power supply detection voltage ( 2 ) Power supply drop time Symbol Condition VDET Min. Typ. μs /V 2 10 ms /V 1.6V → VDD ≤ 3.6V 5 μs /V 1.6V → VDD > 3.
RX − 8801 SA / JE 8.8. Connection with Typical Microcontroller VDD D1: Schottky Barrier Diode SCL Note 2 I C-BUS Master SDA VDD SCL RX-8801 SLAVE ADRS = 0110 010* VDD SDA GND Pull up Registor R= tr C BUS SCL SDA ( I2C Bus ) Note : It uses the secondary battery or a lithium battery. When using the seconding battery, the diode is not required. When using the lithium battery, the diode is required. For detailed value on the resistance, please consult a battery maker. 8.9.
RX − 8801 SA / JE 9. External Dimensions / Marking Layout 9.1. RX − 8801 SA ( SOP − 14pin ) 9.1.1. External dimensions RX − 8801 SA ( SOP − 14pin ) • External dimensions • Recommended soldering pattern 10.1 ± 0.2 #14 0° - 10° #8 1.4 5.0 5.4 7.4 ± 0.2 0.6 #1 #7 0.15 0.05 Min. 0.35 ∗ 1.27 1.4 1.27 0.7 1.27 × 6 = 7.62 3.2 ± 0.1 1.2 Unit : mm The cylinder of the crystal oscillator can be seen in this area ( front ), but it has no affect on the performance of the device. 9.1.2.
RX − 8801 SA / JE 9.2. RX − 8801 JE ( VSOJ − 20pin ) 9.2.1. External dimensions RX − 8801 JE ( VSOJ − 20pin ) • External dimensions • Recommended soldering pattern 7.0 ± 0.3 #20 (0.75) #11 1.5 #1 3.8 6.0 ± 0.2 5.4 0.65 0.35 0.3 1.5 #10 (0.75) 0.65 × 9 = 5.85 1.3 1.5 Max. 0.22 0.65 0.12 ∗ 0 Min. Unit : mm 0.1 The cylinder of the liquid crystal oscillator can be seen in this area ( back and front ), but it has no affect on the performance of the device. 9.2.2.
RX − 8801 SA / JE 10. Application notes 1) Notes on handling This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling. (1) Static electricity While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials.
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