CMOS 4-Nit Single Chip Microcomputer Core CPU Manual

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MF297-07

Core CPU Manual

CMOS 4

BIT SINGLE CHIP MICROCOMPUTER

S1C6200/6200A

Summary of content (98 pages)

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MF297-07 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C6200/6200A Core CPU Manual
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
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The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
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CONTENTS S1C6200/6200A Core CPU Manual CONTENTS 1 DESCRIPTION ____________________________________________________ 1 1.1 1.2 1.3 System Features ........................................................................................................ 1 Instruction Set Features ........................................................................................... 1 Differences between S1C6200 and S1C6200A .........................................................
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1 DESCRIPTION 1 DESCRIPTION The S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomputers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include RAM, ROM, I/O ports, interrupt controllers, timers and LCD drivers, depending upon the application. The memory address space is divided into program and data memory, each with data and address lines. Program memory consists of on-chip ROM, containing instructions to be executed by the CPU.
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1 DESCRIPTION 4-bit address bus XP (4) 4-bit data bus 8-bit address bus Data Memory RAM, Peripheral I/O (4,096 4-bit words max.) RP (4) YHL (8) XHL (8) YP (4) Oscillator Interrupt Controller Timing Generator A (4) B (4) TEMPB (5) TEMPA (5) Stack Pointer (8) 13-bit address bus Program Counter Block ALU Micro-Instructions I D Z C Instruction Decorder Instruction Register (12) S1C6200 CORE CPU 12-bit data bus Program Memory ROM (8,192 12-bit words max.) Fig. 1.
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2 MEMORY AND OPERATIONS 2 MEMORY AND OPERATIONS A single-chip microcomputer using the S1C6200/6200A Core CPU has four major blocks: the program memory (ROM), the data memory (RAM and I/O), the arithmetic logic unit (ALU) and the timing generator circuit. This section describes each of these blocks in detail. 2.1 Program Memory (ROM) Program memory contains the instructions that the CPU executes. Figure 2.1.1 shows the configuration of the program memory. Each instruction is a 12-bit word.
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2 MEMORY AND OPERATIONS 2.1.1 Program counter block The program counter is used to point to the next instruction step to be executed by the CPU. See Figure 2.1.1.1. The program counter has the following registers. Table 2.1.1.1 Program counter registers Register PCB (Program Counter-Bank) PCP (Program Counter-Page) PCS (Program Counter-Step) NBP (New Bank Pointer) NPP (New Page Pointer) Size 1-bit register 4-bit counter 8-bit counter 1-bit register 4-bit register Program memory (8,192 12-bit words max.
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2 MEMORY AND OPERATIONS 2.1.3 Jump instructions A jump can be made using the instructions in Table 2.1.3.1. Table 2.1.3.1 Jump instructions Type of jump Instruction JP Unconditional Conditional JP C, JP NC, JP Z, JP NZ CALL, CALZ Subroutine call Return RET, RETS, RETD PSET Page set Indirect JPBA The differences between jumps within the same page and jumps from one page to another is as follows.
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2 MEMORY AND OPERATIONS 2.1.6 PSET instruction Jump or call instructions must follow PSET immediately in order for PSET to affect the destination address. When a jump or call is not immediately preceded by PSET, the destination address is within the current page. Some examples using PSET are shown in Table 2.1.6.1. Table 2.1.6.
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2 MEMORY AND OPERATIONS The difference between CALL and CALZ is shown in Figure 2.1.7.2.
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2 MEMORY AND OPERATIONS 2.2 Data Memory The data memory area comprises 4,096 4-bit words. The RAM, timer, I/O and other peripheral circuits are mapped into this memory according to the designer's specifications. Figure 2.2.1 shows the data memory configuration.
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2 MEMORY AND OPERATIONS • Index register IY Index register IY is like the index register IX: it has a 4-bit page part (YP), an 8-bit register (YHL), and can address any location in the data memory. See Figure 2.2.1.2. MSB LSB 4 4 4 YP YH YL YHL YHL is divided into two 4-bit groups: the four highIY order bits (YH) and the four low-order bits (YL), and can address any location within a page. Fig. 2.2.1.
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2 MEMORY AND OPERATIONS 2.3 ALU (Arithmetic Logic Unit) and Registers Table 2.3.1 shows ALU operations between the 4-bit registers, TEMPA and TEMPB. Table 2.3.
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2 MEMORY AND OPERATIONS Hexadecimal operations will not always produce the correct result if performed in decimal mode. Note that: • An add instruction with carry (for example, ADC XH,i) which uses index registers XH, XL, YH and YL, does not involve decimal correction even if it is performed in the decimal mode. This is because it uses an 8-bit field for 4-bit data. • The results of the compare instruction (CP) is not decimal-corrected, because the carry flag is ignored.
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2 MEMORY AND OPERATIONS 2.5 Interrupts The S1C6200/6200A can have up to 15 interrupt vectors. When used with peripheral circuits, these allow internal and external interrupts to be processed easily. See Figure 2.5.3.1 through 2.5.3.4. 2.5.1 Interrupt vectors The interrupt vectors are assigned to steps 1 to 15 in page 1 of each bank of the program memory. When an interrupt occurs, the program jumps to the appropriate interrupt vector in the current bank.
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2 MEMORY AND OPERATIONS S1C6200 Clock Status Instruction 5-clock Instrruction 12-clock Instrruction INT1 (*1) INT2 (*1) JP (*2) Interrupt Interrupt processing: 12-clock instruction ... 13 to 25 clock cycles 7-clock instruction ... 13 to 20 clock cycles 5-clock instruction ... 13 to 18 clock cycles S1C6200A Clock Status Instruction 5-clock Instrruction 12-clock Instrruction INT1 (*1) INT2 (*1) JP (*2) Interrupt Interrupt processing: 12-clock instruction ... 12.5 to 24.
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2 MEMORY AND OPERATIONS S1C6200/6200A System clock CPU clock Status Instruction 5-clock Instrruction INT1 (*1) SLEEP INT2 (*1) JP (*2) Interrupt Interrupt processing: 14 to 15 clock cycles Status: Fetch Execute Note: (*1) INT1 and INT2 are dummy instructions (*2) Branches to the top of the interrupt service routine Fig. 2.5.3.3 Interrupt timing in SLEEP mode S1C6200 Clock Status Instruction PSET CALL INT1 (*1) INT2 (*1) JP (*2) Interrupt Interrupt processing: PSET + CALL ...
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2 MEMORY AND OPERATIONS 2.5.4 Initial reset On reset, the registers and flags are set as shown in Table 2.5.4.1. Table 2.5.4.
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3 INSTRUCTION SET 3 INSTRUCTION SET This chapter describes the entire instruction set of the S1C6200/6200A Core CPU. A subset is allocated to each device within the S1C62 Family according to the configuration of the device. Therefore not all instructions are available in every device. The relevant information is in the technical manual for each device. The source format and a description of the assembler is in the series-specific cross assembler manuals. The instruction set contains 109 instructions.
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3 INSTRUCTION SET 3.1.
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3 INSTRUCTION SET Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation XH, i 1 0 1 0 0 1 0 0 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 XH-i3~i0 operation XL, i 1 0 1 0 0 1 0 1 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 XL-i3~i0 instructions YH, i 1 0 1 0 0 1 1 0 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 YH-i3~i0 YL, i 1 0 1 0 0 1 1 1 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 YL-i3~i0 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r ← i3~i0 transfer r, q 1 1 1 0 1 1 0 0 r1 r0 q1 q0 5 r←q instructions A, Mn 1 1 1
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3 INSTRUCTION SET Classification Stack Mnemonic POP operation instructions LD Arithmetic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation YH 1 1 1 1 1 1 0 1 1 0 0 0 5 YH ← M(SP), SP ← SP+1 YL 1 1 1 1 1 1 0 1 1 0 0 1 5 YL ← M(SP), SP ← SP+1 F 1 1 1 1 1 1 0 1 1 0 1 0 ↓ ↑ ↑ ↓ ↑ ↓ ↑ ↓ 5 F ← M(SP), SP ← SP+1 SPH, r 1 1 1 1 1 1 1 0 0 0 r1 r0 5 SPH ← r SPL, r 1 1 1 1 1 1 1 1 0 0 r1 r0 5 SPL ← r r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r ← SPH r, SPL 1 1 1 1 1 1
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3 INSTRUCTION SET 3.1.
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3 INSTRUCTION SET Page Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation A, Mn 1 1 1 1 1 0 1 0 n3 n2 n1 n0 5 A ← M(n3~n0) 47 B, Mn 1 1 1 1 1 0 1 1 n3 n2 n1 n0 5 B ← M(n3~n0) 48 Mn, A 1 1 1 1 1 0 0 0 n3 n2 n1 n0 5 M(n3~n0) ← A 48 Mn, B 1 1 1 1 1 0 0 1 n3 n2 n1 n0 5 M(n3~n0) ← B 51 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r ← i3~i0 51 r, q 1 1 1 0 1 1 0 0 r1 r0 q1 q0 5 r←q 52 r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r ← SPH 52 r, SPL 1 1 1 1 1 1 1
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3 INSTRUCTION SET Operation Code Flag Page Mnemonic 67 PSET p 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP ← p4, NPP ← p3~p0 68 PUSH F 1 1 1 1 1 1 0 0 1 0 1 0 5 SP ← SP-1, M(SP) ← F 68 r 1 1 1 1 1 1 0 0 0 0 r1 r0 5 SP ← SP-1, M(SP) ← r 69 XH 1 1 1 1 1 1 0 0 0 1 0 1 5 SP ← SP-1, M(SP) ← XH 69 XL 1 1 1 1 1 1 0 0 0 1 1 0 5 SP ← SP-1, M(SP) ← XL 70 XP 1 1 1 1 1 1 0 0 0 1 0 0 5 SP ← SP-1, M(SP) ← XP 70 YH 1 1 1 1 1 1 0 0 1 0 0 0 5 SP ← SP-1, M(SP) ← YH 71 YL 1 1 1 1 1 1 0 0 1 0 0
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3 INSTRUCTION SET 3.1.
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3 INSTRUCTION SET Operation Code (HEX) Mnemonic Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP ← p4, NPP ← p3~p0 E60 to E6F LDPX MX, i 1 1 1 0 0 1 1 0 i3 i2 i1 i0 5 M(X) ← i3~i0, X ← X+1 E70 to E7F LDPY MY, i 1 1 1 0 0 1 1 1 i3 i2 i1 i0 5 M(Y) ← i3~i0, Y ← Y+1 E80 to E83 LD XP, r 1 1 1 0 1 0 0 0 0 0 r1 r0 5 XP ← r E84 to E87 LD XH, r 1 1 1 0 1 0 0 0 0 1 r1 r0 5 XH ← r E88 to E8B LD XL, r 1 1 1 0 1 0 0 0 1 0 r1 r0 5 XL ← r E8C to E8F RRC
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3 INSTRUCTION SET Operation Code (HEX) Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation F90 to F9F LD Mn, B 1 1 1 1 1 0 0 1 n3 n2 n1 n0 5 M(n3~n0) ← B FA0 to FAF LD A, Mn 1 1 1 1 1 0 1 0 n3 n2 n1 n0 5 A ← M(n3~n0) FB0 to FBF LD B, Mn 1 1 1 1 1 0 1 1 n3 n2 n1 n0 5 B ← M(n3~n0) FC0 to FC3 PUSH r 1 1 1 1 1 1 0 0 0 0 r1 r0 5 SP ← SP-1, M(SP) ← r FC4 PUSH XP 1 1 1 1 1 1 0 0 0 1 0 0 5 SP ← SP-1, M(SP) ← XP FC5 PUSH XH 1 1 1 1 1 1 0 0 0 1 0 1 5 S
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3 INSTRUCTION SET 3.2 Operands This section describes the operands used in the instructions. p s e i r q 5-bit immediate data or labels 00H to 1FH. Used to specify a destination address. 8-bit immediate data or labels 00H to FFH. Used to specify a destination address. 8-bit immediate data 00H to FFH. 4-bit immediate data 00H to 0FH. 2-bit immediate data. See Table 3.2.1. 2-bit immediate data. See Table 3.2.1. The contents of A, B, MX, MY are referenced using r and q as shown in the following table.
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3 INSTRUCTION SET 3.4 Instruction Types Instructions are divided into six types according to the size of the operand. (I) MSB LSB Op-code ex: 8-bit operand JP CALL LBPX s s MX,e etc. (II) MSB LSB Op-code ex: 6-bit operand ADD LD FAN r, i r, i r, i etc. (III) MSB LSB Op-code 5-bit operand (IV) MSB ex: PSET p ex: SET LD INC F, i r, q Mn LSB Op-code 4-bit operand etc. (V) MSB LSB 2-bit operand Op-code ex: ACPX LD PUSH MX, r XH, r r etc.
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3 INSTRUCTION SET ACPX MX,r Source Format: Operation: OP-Code: Add with carry r-register to M(X), increment X by 1 ACPX MX,r M(X) ← M(X) + r + C, X ← X + 1 1 1 1 1 0 0 1 0 1 MSB Type: V Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a carry is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Adds the carry bit and the contents of the r-register to the data memory location addressed by IX. X is incremented by one.
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3 INSTRUCTION SET ADC r,i Add with carry immediate data i to r-register Source Format: Operation: OP-Code: ADC r,i r ← r + i3 to i0 + C 1 1 0 0 0 1 r1 r0 i3 i2 i1 i0 MSB Type: II Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a carry is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Adds the carry bit and immediate data i to the r-register.
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3 INSTRUCTION SET ADC XH,i Source Format: Operation: OP-Code: Add with carry immediate data i to XH ADC XH,i XH ← XH + i3 to i0 + C 1 0 1 0 0 0 0 0 i3 i2 i1 i0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a carry is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Adds the carry bit and immediate data i to XH, the four high-order bits of XHL.
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3 INSTRUCTION SET ADC YH,i Source Format: Operation: OP-Code: Add with carry immediate data i to YH ADC YH,i YH ← YH + i3 to i0 + C 1 0 1 0 0 0 1 0 i3 i2 i1 i0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a carry is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Adds the carry bit and immediate data i to YH, the four high-order bits of YHL.
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3 INSTRUCTION SET ADD r,i Add immediate data i to r-register Source Format: Operation: OP-Code: ADD r,i r ← r + i3 to i0 1 1 0 0 0 0 r1 r0 i3 i2 i1 i0 MSB Type: II Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a carry is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Adds immediate data i to the contents of the r-register.
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3 INSTRUCTION SET AND r,i Logical AND immediate data i with r-register Source Format: Operation: OP-Code: AND r,i r ← r ∧ i3 to i0 1 1 0 0 1 0 r1 r0 i3 i2 i1 i0 MSB Type: II Clock Cycles: 7 Flag: C Z D I Description: – – – – Not affected Set if the result is zero; otherwise, reset. Not affected Not affected Performs a logical AND operation between immediate data i and the contents of the r-register. The result is stored in the r-register.
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3 INSTRUCTION SET CALL s Source Format: Operation: OP-Code: OP-Code: Type: Type: Clock Cycles: Clock Cycles: Flag: Flag: Description: Description: Call subroutine CALL s M(SP-1) ← PCP, M(SP-2) ← PCSH, M(SP-3) ← PCSL + 1, SP ← SP - 3, PCP ← NPP, PCS ← s7 to s0 MSB 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 LSB s0 MSB I 7 C C Z Z D DI I – – – – – Not affected Not affected Not affected Not affected Pushes the program counter (PCP, PCS) onto the stack as the return address, then calls the subroutine addressed by N
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3 INSTRUCTION SET CP r,i Compare immediate data i with r-register Source Format: Operation: OP-Code: CP r,i r - i3 to i0 1 1 0 1 1 1 r1 r0 i3 i2 i1 i0 MSB Type: II Clock Cycles: 7 Flag: C Z D I Description: Example: – – – – Set if r < i3 to i0; otherwise, reset. Set if r = i3 to i0; otherwise, reset. Not affected Not affected Compares immediate data i to the r-register by subtracting i from the contents of r. The r-register remains unchanged. 1. When Z = 0 and C = 0 then i < r 2.
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3 INSTRUCTION SET CP XH,i Compare immediate data i with XH Source Format: Operation: OP-Code: CP XH,i XH - i3 to i0 1 0 1 0 0 1 0 0 i3 i2 i1 i0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: Example: – – – – Set if XH < i3 to i0; otherwise, reset. Set if XH = i3 to i0; otherwise, reset. Not affected Not affected Compares immediate data i to XH by subtracting i from the contents of XH. XH remains unchanged. 1. When Z = 0 and C = 0 then i < XH 2.
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3 INSTRUCTION SET CP YH,i Compare immediate data i with YH Source Format: Operation: OP-Code: CP YH,i YH - i3 to i0 1 0 1 0 0 1 1 0 i3 i2 i1 i0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: Example: – – – – Set if YH < i3 to i0; otherwise, reset. Set if YH = i3 to i0; otherwise, reset. Not affected Not affected Compares immediate data i to YH by subtracting i from the contents of YH. YH remains unchanged. 1. When Z = 0 and C = 0 then i < YH 2.
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3 INSTRUCTION SET DEC Mn Decrement memory Source Format: Operation: OP-Code: DEC Mn M(n3 to n0) ← M(n3 to n0) - 1 1 1 1 1 0 1 1 1 n3 n2 n1 n0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a borrow is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Decrements the contents of the data memory location addressed by Mn by 1.
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3 INSTRUCTION SET DI Disable interrupts Source Format: Operation: OP-Code: DI I←0 1 1 1 1 0 1 0 1 0 1 1 MSB Type: 7 Flag: C Z D I – – – – Not affected Not affected Not affected Reset Disables all interrupts.
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3 INSTRUCTION SET FAN r,i Logical AND immediate data i with r-register for flag check Source Format: Operation: OP-Code: FAN r,i r ∧ i3 to i0 1 1 0 1 1 0 r1 r0 i3 i2 i1 i0 MSB Type: II Clock Cycles: 7 Flag: C Z D I Description: – – – – Not affected Set if the result is zero; otherwise, reset. Not affected Not affected Performs a logical AND operation between immediate data i and the contents of the r-register. Only the Z flag is affected. The r-register remains unchanged.
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3 INSTRUCTION SET HALT Halt Source Format: Operation: OP-Code: HALT Stops CPU 1 1 1 1 1 1 1 1 1 0 0 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Stops the CPU. When an interrupt occurs, PCP and PCS are pushed onto the stack as the return address and the interrupt service routine is executed.
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3 INSTRUCTION SET INC SP Increment stack pointer by 1 Source Format: Operation: OP-Code: INC SP SP ← SP + 1 1 1 1 1 1 1 0 1 1 0 1 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Increments the contents of the stack pointer by 1. This operation does not affect the flags.
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3 INSTRUCTION SET INC Y Increment Y-register by 1 Source Format: Operation: OP-Code: INC Y Y←Y+1 1 1 1 0 1 1 1 1 0 0 0 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Increments the contents of register Y by 1. This operation does not affect the flags.
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3 INSTRUCTION SET JP C,s Jump if carry flag is set Source Format: Operation: JP C,s PCB ← NBP, PCP ← NPP, PCS ← s7 to s0 if C = 1 0 OP-Code: 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 MSB Type: I Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Jumps to the destination address specified by the 8-bit operand when the carry flag is set.
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3 INSTRUCTION SET JP NZ,s Jump if not zero Source Format: Operation: JP NZ,s PCB ← NBP, PCP ← NPP, PCS ← s7 to s0 if Z = 0 0 OP-Code: 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0 MSB Type: I Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Jumps to the destination address specified by the 8-bit operand when the zero flag is not set.
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3 INSTRUCTION SET JP Z,s Jump if zero Source Format: Operation: JP Z,s PCB ← NBP, PCP ← NPP, PCS ← s7 to s0 if Z = 1 0 OP-Code: 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0 MSB Type: I Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Jumps to the destination address specified by the 8-bit operand when the zero flag is set.
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3 INSTRUCTION SET LD A,Mn Load memory into A-register Source Format: Operation: OP-Code: LD A,Mn A ← M(n3 to n0) 1 1 1 1 1 0 1 0 n3 n2 n1 n0 MSB Type: IV Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the contents of the data memory location addressed by Mn into the Aregister.
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3 INSTRUCTION SET LD Mn,A Load A-register into memory Source Format: Operation: OP-Code: LD Mn,A M(n3 to n0) ← A 1 1 1 1 1 0 0 0 n3 n2 n1 n0 MSB Type: IV Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the contents of the A-register into the location addressed by Mn.
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3 INSTRUCTION SET LDPX MX,i Source Format: Operation: OP-Code: Load immediate data i into MX, increment X by 1 LDPX MX,i M(X) ← i3 to i0, X ← X + 1 1 1 1 0 0 1 1 0 i3 i2 i1 i0 MSB Type: IV Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads immediate data i into the data memory location addressed by IX. X is incremented by 1. Incrementing X does not affect the flags.
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3 INSTRUCTION SET LDPY MY,i Source Format: Operation: OP-Code: Load immediate data i into MY, increment Y by 1 LDPY MY,i M(Y) ← i3 to i0, Y ← Y + 1 1 1 1 0 0 1 1 1 i3 i2 i1 i0 MSB Type: IV Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads immediate data i into the data memory location addressed by IY. Y is incremented by 1. Incrementing Y does not affect the flags.
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3 INSTRUCTION SET LD r,i Load immediate data i into r-register Source Format: Operation: OP-Code: LD r,i r ← i3 to i0 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 MSB Type: II Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads immediate data i into the r-register.
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3 INSTRUCTION SET LD r,SPH Source Format: Operation: OP-Code: Load SPH into r-register LD r,SPH r ← SPH 1 1 1 1 1 1 1 0 0 1 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the four high-order bits of the stack pointer into the r-register.
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3 INSTRUCTION SET LD r,XH Load XH into r-register Source Format: Operation: OP-Code: LD r,XH r ← XH 1 1 1 0 1 0 1 0 0 1 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the four high-order bits of register X into the r-register.
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3 INSTRUCTION SET LD r,XP Load XP into r-register Source Format: Operation: OP-Code: LD r,XP r ← XP 1 1 1 0 1 0 1 0 0 0 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the 4-bit page part of index register IX into the r-register.
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3 INSTRUCTION SET LD r,YL Load YL into r-register Source Format: Operation: OP-Code: LD r,YL r ← YL 1 1 1 0 1 0 1 1 1 0 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the four low-order bits of register Y into the r-register.
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3 INSTRUCTION SET LD SPH,r Source Format: Operation: OP-Code: Load r-register into SPH LD SPH,r SPH ← r 1 1 1 1 1 1 1 0 0 0 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the contents of the r-register into the four high-order bits of the stack pointer.
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3 INSTRUCTION SET LD X,e Load immediate data e into X-register Source Format: Operation: LD X,e XH ← e7 to e4, XL ← e3 to e0 1 OP-Code: 0 1 1 e7 e6 e5 e4 e3 e2 e1 e0 MSB Type: I Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads 8-bit immediate data e into register X.
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3 INSTRUCTION SET LD XL,r Load r-register into XL Source Format: Operation: OP-Code: LD XL,r XL ← r 1 1 1 0 1 0 0 0 1 0 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the contents of the r-register into the four low-order bits of register X.
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3 INSTRUCTION SET LD Y,e Load immediate data e into Y-register Source Format: Operation: LD Y,e YH ← e7 to e4, YL ← e3 to e0 1 OP-Code: 0 0 0 e7 e6 e5 e4 e3 e2 e1 e0 MSB Type: I Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads 8-bit immediate data e into register Y.
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3 INSTRUCTION SET LD YL,r Load r-register into YL Source Format: Operation: OP-Code: LD YL,r YL ← r 1 1 1 0 1 0 0 1 1 0 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the contents of the r-register into the four low-order bits of register Y.
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3 INSTRUCTION SET NOP5 No operation for 5 clock cycles Source Format: Operation: OP-Code: NOP5 No operation (5 clock cycles) 1 1 1 1 1 1 1 1 1 0 1 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Increments the program counter by 1. Has no other effect for 5 clock cycles.
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3 INSTRUCTION SET NOT r NOT r-register (one's complement) Source Format: Operation: OP-Code: NOT r r←r 1 1 0 1 0 0 r 1 r0 1 1 1 MSB Type: II Clock Cycles: 7 Flag: C Z D I Description: – – – – Performs a one's complement operation on the contents of the r-register.
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3 INSTRUCTION SET OR r,q Logical OR q-register with r-register Source Format: Operation: OP-Code: OR r,q r←r∨q 1 0 1 0 1 1 0 1 r1 r0 q1 q0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: – – – – Not affected Set if the result is zero; otherwise, reset. Not affected Not affected Performs a logical OR operation between the contents of the q-register and the contents of the r-register. The result is stored in the r-register.
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3 INSTRUCTION SET POP r Pop stack data into r-register Source Format: Operation: OP-Code: POP r r ← M(SP), SP ← SP + 1 1 1 1 1 1 1 0 1 0 0 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Not affected Not affected Not affected Not affected Loads the contents of the data memory location addressed by the stack pointer into the r-register. SP is incremented by 1.
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3 INSTRUCTION SET POP XL Pop stack data into XL Source Format: Operation: OP-Code: POP XL XL ← M(SP), SP ← SP + 1 1 1 1 1 1 1 0 1 0 1 1 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Loads the contents of the data memory location addressed by the stack pointer into XL, the four low-order bits of X. SP is incremented by 1.
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3 INSTRUCTION SET POP YH Pop stack data into YH Source Format: Operation: OP-Code: POP YH YH ← M(SP), SP ← SP + 1 1 1 1 1 1 1 0 1 1 0 0 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Loads the contents of the data memory location addressed by the stack pointer into YH, the four high-order bits of Y. SP is incremented by 1.
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3 INSTRUCTION SET POP YP Pop stack data into YP Source Format: Operation: OP-Code: POP YP YP ← M(SP), SP ← SP + 1 1 1 1 1 1 1 0 1 0 1 1 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Loads the contents of the data memory location addressed by the stack pointer into YP, the 4-bit page part of IY. SP is incremented by 1.
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3 INSTRUCTION SET PUSH F Push flag onto stack Source Format: Operation: OP-Code: PUSH F SP' ← SP - 1, M(SP') ← F 1 1 1 1 1 1 0 0 1 0 1 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Decrements the stack pointer by 1 and loads the flags (F) into the data memory location addressed by SP.
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3 INSTRUCTION SET PUSH XH Source Format: Operation: OP-Code: Push XH onto stack PUSH XH SP' ← SP - 1, M(SP') ← XH 1 1 1 1 1 1 0 0 0 1 0 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Decrements the stack pointer by 1 and loads the contents of XH, the four highorder bits of XHL, into the data memory location addressed by SP.
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3 INSTRUCTION SET PUSH XP Source Format: Operation: OP-Code: Push XP onto stack PUSH XP SP' ← SP - 1, M(SP') ← XP 1 1 1 1 1 1 0 0 0 1 0 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Decrements the stack pointer by 1 and loads the contents of XP, the page part of IX, into the data memory location addressed by SP.
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3 INSTRUCTION SET PUSH YL Push YL onto stack Source Format: Operation: OP-Code: PUSH YL SP' ← SP - 1, M(SP') ← YL 1 1 1 1 1 1 0 0 1 0 0 MSB Type: 5 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Decrements the stack pointer by 1 and loads the contents of YL, the four low-order bits of YHL, into the data memory location addressed by SP.
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3 INSTRUCTION SET RCF Reset carry flag Source Format: Operation: OP-Code: RCF C←0 1 1 1 1 0 1 0 1 1 1 1 MSB Type: 7 Flag: C Z D I – – – – Reset Not affected Not affected Not affected Resets the C (carry) flag.
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3 INSTRUCTION SET RET Return from subroutine Source Format: Operation: RET PCSL ← M(SP), PCSH ← M(SP+1), PCP ← M(SP+2), SP ← SP + 3 1 OP-Code: 1 1 1 1 1 0 1 1 1 1 MSB Type: 7 Flag: C Z D I – – – – Not affected Not affected Not affected Not affected Jumps to the return address that was pushed onto the stack when the subroutine was called.
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3 INSTRUCTION SET RETS Return then skip an instruction Source Format: Operation: OP-Code: RETS PCSL ← M(SP), PCSH ← M(SP+1), PCP ← M(SP+2), SP ← SP + 3, PC ← PC + 1 1 1 1 1 1 1 0 1 1 1 1 MSB Type: VI Clock Cycles: 12 Flag: C Z D I Description: – – – – Jumps to the return address that was pushed onto the stack when the subroutine was called and then skips one instruction.
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3 INSTRUCTION SET RRC r Rotate r-register right with carry Source Format: Operation: OP-Code: RRC r d3 ← C, d2 ← d3, d1 ← d2, d0 ← d1, C ← d0 1 1 1 0 1 0 0 0 1 1 r 1 r0 MSB Type: V Clock Cycles: 5 Flag: C Z D I Description: – – – – Set when the low-order bit of the r-register is 1; otherwise, reset. Not affected Not affected Not affected Shifts the contents of the r-register one bit to the right.
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3 INSTRUCTION SET RZF Reset zero flag Source Format: Operation: OP-Code: RZF Z←0 1 1 1 1 0 1 0 1 1 1 0 MSB Type: 7 Flag: C Z D I – – – – Not affected Reset Not affected Not affected Resets the Z (zero) flag.
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3 INSTRUCTION SET SBC r,q Subtract with carry q-register from r-register Source Format: Operation: OP-Code: SBC r,q r←r-q-C 1 0 1 0 1 0 1 1 r1 r0 q1 q0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a borrow is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Subtracts the carry flag and the contents of the q-register from the r-register.
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3 INSTRUCTION SET SCPX MX,r Source Format: Operation: OP-Code: Subtract with carry r-register from M(X) and increment X by 1 SCPX MX,r M(X) ← M(X) - r - C, X ← X + 1 1 1 1 1 0 0 1 1 1 0 r 1 r0 MSB Type: V Clock Cycles: 7 Flag: C Z D I Description: – – – – Set if a borrow is generated; otherwise, reset. Set if the result is zero; otherwise, reset. Not affected Not affected Subtracts the carry flag and the contents of the r-register from the data memory location addressed by IX.
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3 INSTRUCTION SET SDF Set decimal flag Source Format: Operation: OP-Code: SDF D←1 1 1 1 1 0 1 0 0 0 1 0 MSB Type: 7 Flag: C Z D I – – – – Not affected Not affected Set Not affected Sets the D (decimal) flag.
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3 INSTRUCTION SET SLP Sleep Source Format: Operation: OP-Code: SLP Stop CPU and peripheral oscillator 1 1 1 1 1 1 1 1 1 0 0 MSB Type: FF9H VI Clock Cycles: 5 Flag: C Z D I Description: 1 LSB – – – – Not affected Not affected Not affected Not affected Stops the CPU and the peripheral oscillator. When an interrupt occurs PCP and PCS are pushed onto the stack as the return address and the interrupt service routine is executed.
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3 INSTRUCTION SET SZF Set zero flag Source Format: Operation: OP-Code: SZF Z←1 1 1 1 1 0 1 0 0 0 0 1 MSB Type: 7 Flag: C Z D I – – – – Not affected Set Not affected Not affected Sets the Z (zero) flag.
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3 INSTRUCTION SET XOR r,q Exclusive-OR q-register with r-register Source Format: XOR r,q Operation: r←r∀q OP-Code: 1 0 1 0 1 1 1 0 r1 r0 q 1 q 0 MSB Type: IV Clock Cycles: 7 Flag: C Z D I Description: AE0H to AEFH LSB – – – – Not affected Set if the result is zero; otherwise, reset. Not affected Not affected Performs an exclusive-OR operation between the contents of the q-register and the contents of the r-register. The result is stored in the r-register.
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3 INSTRUCTION SET ABBREVIATIONS Source Format:(4 bits) A ............. A register B ............. BOperation: register (4 bits) M(SP) ..... Contents of the data memory location whose address is specified by stack pointer SP (4 bits) OP-Code:of the data memory location whose address is specified by IX (4 bits) M(X) ....... Contents MSB LSB M(Y) ....... Contents of the data memory location whose address is specified by IY (4 bits) Type: M(n3-0) ....
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APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU S1C6200A is an improved version of the S1C6200. In this section, S1C6200A is described only in terms of its differences with S1C6200. It is recommended that users of S1C6200A read this section. S1C6200A is a Core CPU which has been made easier to integrate software by improving the parts of the S1C6200 CPU which are difficult to use.
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APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU Clock Status Instruction 5-clock Instrruction 12-clock Instrruction INT1 (*1) INT2 (*1) JP (*2) Interrupt Interrupt processing: 12-clock instruction ... 12.5 to 24.5 clock cycles 7-clock instruction ... 12.5 to 19.5 clock cycles 5-clock instruction ... 12.5 to 17.
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APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU Writing on the interrupt mask register during EI This section describes the operation for writing on the interrupt mask register during EI (enable interrupt flag) in the regular 1-chip micro controller which uses S1C6200 Core CPU and in the regular 1-chip micro controller which uses S1C6200A Core CPU. For information on accurate operation, see the respective hardware manuals of the S1C62 Family. Table A2.2.
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APPENDIX B. INSTRUCTION INDEX APPENDIX B. INSTRUCTION INDEX A ACPX MX,r Add with carry r-register to M(X), increment X by 1 ........................... 28 ACPY MY,r Add with carry r-register to M(Y), increment Y by 1 ........................... 28 ADC r,i ADC r,q Add with carry immediate data i to r-register ...................................... 29 Add with carry q-register to r-register ................................................. 29 ADC XH,i ADC XL,i Add with carry immediate data i to XH .....
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APPENDIX B. INSTRUCTION INDEX L 88 LBPX MX,e Load immediate data e to memory, and increment X by 2 ................... 46 LD A,Mn LD B,Mn Load memory into A-register ............................................................... 47 Load memory into B-register ............................................................... 47 LD Mn,A LD Mn,B Load A-register into memory ............................................................... 48 Load B-register into memory .......................................
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APPENDIX B. INSTRUCTION INDEX P R S X PUSH r Push r-register onto stack .................................................................... 68 PUSH XH PUSH XL Push XH onto stack .............................................................................. 69 Push XL onto stack ............................................................................... 69 PUSH XP PUSH YH Push XP onto stack ............................................................................... 70 Push YH onto stack ..
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S1C6200/6200A Core CPU Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.