MF1112-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N04 Technical Manual S1C60N04 Technical Hardware
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CONTENTS CONTENTS CHAPTER 1 INTRODUCTION ____________________________________________ 1 1.1 1.2 1.3 1.4 CHAPTER Features ........................................................................................................ 1 Block Diagram .............................................................................................. 2 Pin Layout ..................................................................................................... 3 Pin Description .....................................
CONTENTS 4.7 Clock Timer .................................................................................................. 25 4.7.1 Configuration of clock timer ..................................................................... 25 4.7.2 Interrupt function ...................................................................................... 25 4.7.3 I/O memory of clock timer ........................................................................ 26 4.7.4 Programming notes ............................
CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION The S1C60N04 is a single-chip microcomputer which uses an S1C6200B CMOS 4-bit CPU as the core. It contains a 1,536 (words) × 12 (bits) ROM, 144 (words) × 4 (bits) RAM, LCD driver, 4-bit input port (K00– K03), 4-bit output port (R00–R03), 4-bit I/O port (P00–P03) and a timer. 1.1 Features Core CPU ........................................... S1C6200B Built-in oscillation circuit ............. CR oscillation circuit, 2 MHz (Typ.) (VSS = -5 V) Instruction set .
CHAPTER 1: INTRODUCTION 1.2 Block Diagram ROM System Reset Control 1,536 words × 12 bits RESET Core CPU S1C6200B OSC1 OSC2 OSC / SLEEP Interrupt Generator RAM Input Port K00–K03 144 words × 4 bits COM0–3 SEG0–25 VDD VSS TEST LCD Driver I/O Port 26 SEG × 4 COM Power Divider P00–P03 VL1 VL2 R00 (FOUT, BUZZER)∗1 R01 (BUZZER)∗1 R02, R03 Output Port Clock Timer FOUT & Buzzer ∗1: Terminal specifications can be selected by mask option. Fig. 1.2.
CHAPTER 1: INTRODUCTION 1.3 Pin Layout QFP12-48pin 36 25 37 No. Pin name No. Pin name No. Pin name No.
CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (∗) supplied to VDD through VSS, the S1C60N04 generates the necessary internal voltages with the power divider. ∗ Supply voltage: 2.7 to 3.6 V or 4.5 V to 5.5 V The power divider generates the LCD drive voltages by dividing the supply voltage as shown in Figure 2.1.1.
CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2.1 Power-on reset circuit The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts oscillating. Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The following two initial reset method are recommended to generate the initial reset signal. 2.2.2 Reset pin (RESET) An initial reset can be invoked externally by making the reset pin high.
CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N04 employs the S1C6200B core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200/6200A/6200B. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B, which is compatible with the S1C6200A.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N04 are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2 Oscillation Circuit The S1C60N04 has a CR oscillation circuit. The CR oscillation circuit generates the operating clock for the CPU and the peripheral circuits. The oscillation frequency is 2 MHz (Typ.). Figure 4.2.1 is the circuit diagram of the CR oscillation circuit. OSC1 RCR CPU and peripheral circuits CCR OSC2 Fig. 4.2.1 CR oscillation circuit As shown in Figure 4.2.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3 Input Ports (K00–K03) 4.3.1 Configuration of input port The S1C60N04 has a 4-bit general-purpose input port. Each of the input port pins (K00–K03) has an internal pull-down resistor. The pull-down resistor can be selected for each bit with the mask option. Figure 4.3.1.1 shows the configuration of input port. VDD Data bus Interrupt request K0x Address VSS Mask option Fig. 4.3.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Input interrupt programming related precautions Port K input Active status Mask register ➀ Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at ➀. Fig. 4.3.2.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3.4 I/O memory of input port Table 4.3.4.1 list the input port control bits and their addresses. Table 4.3.4.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4 Output Ports (R00–R03) 4.4.1 Configuration of output port The S1C60N04 has a 4-bit general output port (R00–R03). Output specification of the output port can be selected in a bit units with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Also, the mask option enables the output ports R00 and R01 to be used as special output ports. Figure 4.4.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) FOUT (R00) When output port R00 is set for FOUT output, this port will generate fosc (CPU operating clock frequency) clock. BUZZER, BUZZER (R01, R00) Output ports R01 and R00 may be set to BUZZER output and BUZZER output (BUZZER reverse output), respectively, allowing for direct driving of the piezo-electric buzzer. BUZZER output (R00) may only be set if R01 is set to BUZZER output.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00 register 0 1 FOUT output waveform Fig. 4.4.3.1 FOUT output waveform Note: A hazard may occur when the FOUT signal is turned ON or OFF. R00, R01 (when buzzer output is selected): Special output port data (0F3H•D0, D1) Controls the buzzer output. When 1 is written: Buzzer output When 0 is written: Low level (DC) output Reading: Valid BUZZER and BUZZER output can be controlled by writing data to R00 and R01.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.5 I/O Ports (P00–P03) 4.5.1 Configuration of I/O port Data bus The S1C60N04 has a 4-bit general-purpose I/O port. Figure 4.5.1.1 shows the configuration of the I/O port. The four bits of the I/O port P00–P03 can be set to either input mode or output mode. The mode can be set by writing data to the I/O control register (IOC). Input control Register P0x Address I/O control register (IOC) Address Vss Fig. 4.5.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) P00–P03: I/O port data (0F6H) I/O port data can be read and output data can be written through the port. When writing data When 1 is written: High level When 0 is written: Low level When an I/O port is set to the output mode, the written data is output from the I/O port pin unchanged. When 1 is written as the port data, the port pin goes high (VDD), and when 0 is written, the level goes low (VSS). Port data can also be written in the input mode.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6 LCD Driver (COM0–COM3, SEG0–SEG25) 4.6.1 Configuration of LCD driver The S1C60N04 has four common pins and 26 (SEG0–SEG25) segment pins, so that an LCD with a maximum of 104 (26 × 4) segments can be driven. The power for driving the LCD is generated by the CPU internal circuit, so there is no need to supply power externally.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 COM2 SEG0–25 COM3 Off On VDD VL1 VL2 VSS SEG0 –SEG25 Frame frequency Fig. 4.6.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0–25 COM2 Off On COM3 VDD VL1 VL2 VSS SEG0 –SEG25 Frame frequency Fig. 4.6.1.2 Drive waveform for 1/3 duty (1/3 bias) VDD VL1 VL2 VSS COM0 COM1 LCD lighting status COM0 COM1 SEG0–25 COM2 COM3 VDD VL1 VL2 VSS Off On SEG0 –SEG25 Frame frequency Fig. 4.6.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0–25 COM2 Off On COM3 -VDD -VL1, L2 -VSS SEG 0–25 Frame frequency Fig. 4.6.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0–25 COM2 Off On COM3 -VDD -VL1, L2 -VSS SEG 0–25 Frame frequency Fig. 4.6.1.5 Drive waveform for 1/3 duty (1/2 bias) -VDD -VL1, L2 -VSS COM0 COM1 LCD lighting status COM0 COM1 SEG0–25 COM2 Off On COM3 -VDD -VL1, L2 -VSS SEG 0–25 Frame frequency Fig. 4.6.1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6.2 Mask option (1) Segment allocation As shown in Figure 4.l.1, the S1C60N04 display data is decided by the data written to the display memory (write-only) at address 090H–0AFH. The address and bits of the display memory can be made to correspond to the segment pins (SEG0– SEG25) in any combination through mask option. This simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.6.2.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6.3 I/O memory of LCD driver Table 4.6.3.1 shows the control bits of the LCD driver and their addresses. Figure 4.6.3.1 shows the display memory map. Table 4.6.3.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7 Clock Timer 4.7.1 Configuration of clock timer The S1C60N04 has a built-in clock timer that uses the oscillation circuit as the clock source. The clock timer is configured as a 7-bit binary counter that counts with a 256 Hz source clock from the divider. The high-order 4 bits of the counter (16 Hz–2 Hz) can be read by the software. Figure 4.7.1.1 is the block diagram of the clock timer.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7.3 I/O memory of clock timer Table 4.7.3.1 shows the clock timer control bits and their addresses. Table 4.7.3.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TMRST: Clock timer reset (0F9H•D2) This bit resets the clock timer. When 1 is written: Clock timer reset When 0 is written: No operation Reading: Always 0 The clock timer is reset by writing 1 to TMRST. The clock timer starts immediately after this. No operation results when 0 is written to TMRST. This bit is write-only, and so is always 0 when read. 4.7.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8 Interrupt and HALT/SLEEP Interrupt types The S1C60N04 provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input port interrupt (one) Timer interrupt (one) To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask registers must be set to 1 (enable).
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) HALT and SLEEP modes When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits the HALT mode and resumes operating. Executing the SLP instruction set the IC in the SLEEP mode that stops operations of the CPU and oscillation circuit.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8.1 Interrupt factors Table 4.8.1.1 shows the factors that generate interrupt requests. The interrupt factor flags are set to 1 depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to 1.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8.3 Interrupt vectors When an interrupt request is input to the CPU, the CPU starts interrupt processing. After the program being executed is suspended, interrupt processing is executed in the following order: ➀ The address data (value of the program counter) of the program step to be executed next is saved on the stack (RAM).
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP) 4.8.5 Programming notes (1) Restart from the HALT mode is performed by an interrupt. The return address after completion of the interrupt processing will be the address following the HALT instruction. (2) Restart from the SLEEP mode is performed by an input interrupt from the input port (K00–K03). The return address after completion of the interrupt processing will be the address following the SLP instruction.
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM Piezo Buzzer Single Terminal Driving I COM3 K00 COM0 SEG0 SEG25 LCD PANEL K03 VDD OSC1 RCR P00 I/O P03 OSC2 S1C60N04 [The potential of the substrate RESET (back of the chip) is VDD.
CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating (VDD=0V) Item Rated value Unit Symbol Supply voltage -7.0 to 0.5 V VSS Input voltage (1) VI VSS - 0.3 to 0.5 V Input voltage (2) VIOSC VS1 - 0.3 to 0.
CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics Unless otherwise specified: VDD=0V, VSS=-5.
CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Current Consumption Unless otherwise specified: VDD=0V, fosc=2MHz, Ta=25°C Item Symbol Current consumption ISLP2 IHALT2 IHALT4 IEXE2 IEXE4 ISLP1 IHALT1 IHALT3 IEXE1 IEXE3 Condition During SLEEP, LCD off During HALT, LCD off During HALT, LCD on During operation, LCD off During operation, LCD on During SLEEP, LCD off During HALT, LCD off During HALT, LCD on During operation, LCD off During operation, LCD on Min. Vss=-3.0V no panel load RCR=39kΩ Typ.
CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package QFP12-48pin (Unit: mm) 9±0.4 7±0.1 36 25 7±0.1 9±0.4 24 37 INDEX 13 48 1 12 +0.1 0.18 –0.05 0.1 1.4±0.1 1.7max 0.5 0.125±0.05 0° 10° 0.5±0.
CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples (Unit: mm) 81.3 PIN NO. 1 2 23.1 34 33 22.8 64 63 31 32 INDEX MARK 2.54 78.7 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 38 Pin name SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 N.C. N.C. N.C. N.C. N.C. COM0 COM1 COM2 COM3 TEST No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name RESET VDD OSC1 OSC2 VSS K03 N.C. N.C. N.C. N.C. N.C. K02 K01 K00 P03 P02 No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin name No.
CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Diagram of Pad Layout Die No. 10 5 1 48 15 45 20 (0, 0) 2.44 mm Y X 40 25 30 35 2.79 mm 8.2 Pad Coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pad name SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 X 885 755 625 495 365 211 82 -48 -178 -308 -438 -568 -698 -828 -1226 -1226 S1C60N04 TECHNICAL MANUAL Y 1053 1053 1053 1053 1053 1053 1053 1053 1053 1053 1053 1053 1053 1053 670 540 No.
CHAPTER 9: PRECAUTIONS ON MOUNTING CHAPTER 9 PRECAUTIONS ON MOUNTING ● Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer’s recommended values for constants such as capacitance and resistance. ● Disturbances of the oscillation clock due to noise may cause a malfunction.
CHAPTER 9: PRECAUTIONS ON MOUNTING ● In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. ● When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction.
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