Specifications

I-12 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 3: CPU, ROM, RAM
CPU, ROM, RAM
CPU
The S1C62N82 Series employs the S1C6200A core CPU, so
that register configuration, instructions, and so forth are
virtually identical to those in other processors in the family
using the S1C6200A. Refer to the "S1C6200/6200A Core
CPU Manual" for details of the S1C6200A.
Note the following points with regard to the S1C62N82
Series:
(1)The SLEEP operation is not provided, so the SLP instruc-
tion cannot be used.
(2)Because the ROM capacity is 2,048 words, 12 bits per
word, bank bits are unnecessary, and PCB and NBP are
not used.
(3)The RAM page is set to 0 only, so the page part (XP, YP)
of the index register that specifies addresses is invalid.
PUSH XP PUSH YP
POP XP POP YP
LD XP,r LD YP,r
LD r,XP LD r,YP
CHAPTER 3
3.1