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MF1110

Technical Manual

CMOS 4

BIT SINGLE CHIP MICROCOMPUTER

S1C63466 Technical Hardware

S1C63466

Summary of content (144 pages)

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MF1110-03 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C63466 Technical Manual S1C63466 Technical Hardware
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
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Revisions and Additions for this manual Chapter 7 Appendix S1C63466 Technical Manual Section 7.5 Page 113 125 Item OSC1 crystal oscillation circuit Appendix Contents The table was revised. The Appendix was added.
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The information of the product number change Starting April 1, 2001, the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative.
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CONTENTS CONTENTS CHAPTER 1 OUTLINE ________________________________________________ 1 1.1 1.2 1.3 1.4 1.5 CHAPTER Features ......................................................................................................... 1 Block Diagram .............................................................................................. 2 Pin Layout Diagram ..................................................................................... 3 Pin Description .........................................
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CONTENTS 4.5 Output Ports (R00–R03, R10–R13 and R20–R23) ...................................... 34 4.5.1 Configuration of output ports ................................................................... 34 4.5.2 Mask option ............................................................................................... 34 4.5.3 High impedance control ............................................................................ 35 4.5.4 Special output .........................................................
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CONTENTS 4.12.3 Control of buzzer output .......................................................................... 87 4.12.4 Setting of buzzer frequency and sound level ........................................... 87 4.12.5 Digital envelope ...................................................................................... 88 4.12.6 One-shot output ....................................................................................... 89 4.12.7 I/O memory of sound generator .............................
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CHAPTER 1: OUTLINE CHAPTER 1 OUTLINE The S1C63466 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU, ROM (16,384 words × 13 bits), RAM (1,792 words × 4 bits), serial interface, watchdog timer, programmable timer, time base counters (2 systems), SVD circuit, a dot-matrix LCD driver that can drive a maximum 60 segments × 17 commons and sound generator built-in. The S1C63466 features high speed operation and low current consumption in a wide operating voltage range (2.
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CHAPTER 1: OUTLINE Current consumption (Typ.) ................ Single clock (OSC1: Crystal oscillation): During HALT (32 kHz) 3.0 V (LCD power OFF) 1 µA 3.0 V (LCD power ON, VC1 standard) 6 µA 3.0 V (LCD power ON, VC2 standard) 4 µA During operation (32 kHz) 3.0 V (LCD power ON, VC1 standard) 10 µA Twin clock: During operation (4 MHz) 3.0 V (LCD power ON, VC1 standard) 1,200 µA Package ..............................................
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CHAPTER 1: OUTLINE 1.3 Pin Layout Diagram QFP8-144pin QFP17-144pin 108 108 73 72 109 72 109 S1C63466 S1C63466 INDEX INDEX 37 144 1 37 144 1 36 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 73 Name SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 COM5 COM4 N.C. COM3 COM2 COM1 COM0 BZ VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD RESET TEST VREF N.C. N.C. No.
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CHAPTER 1: OUTLINE QFP5-128pin 102 65 64 103 S1C63466 INDEX 39 128 1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 38 No.
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CHAPTER 1: OUTLINE 1.4 Pin Description Table 1.4.1 Pin description VC1–VC5 Pin No.
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CHAPTER 1: OUTLINE 1.5 Mask Option Mask options shown below are provided for the S1C63466. Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. The function option generator winfog, that has been prepared as the development software tool of S1C63466, is used for this selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the "S5U1C63000A Manual" for the winfog.
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CHAPTER 1: OUTLINE (7) Synchronous clock polarity in the serial interface The polarity of the synchronous clock SCLK and the SRDY signal in slave mode of the serial interface is selected by the mask option. Either positive polarity or negative polarity can be selected. Refer to Section 4.11.2, "Mask option", for details. (8) Buzzer output specification of the sound generator It is possible to select the polarity of the buzzer signal output from the BZ terminal.
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CHAPTER 1: OUTLINE 6. OUTPUT PORT OUTPUT SPECIFICATION • R1x ...... ■ 1. Complementary • R2x ...... ■ 1. Complementary ■ 2. Nch-OpenDrain ■ 2. Nch-OpenDrain 7. I/O PORT OUTPUT SPECIFICATION • P1x ....... • P20 ....... • P21 ....... • P22 ....... • P23 ....... ■ ■ ■ ■ ■ 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary ■ ■ ■ ■ ■ 2. Nch-OpenDrain 2. Nch-OpenDrain 2. Nch-OpenDrain 2. Nch-OpenDrain 2. Nch-OpenDrain ■ ■ ■ ■ ■ 2. Gate Direct 2. Gate Direct 2.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply The S1C63466 operating power voltage is as follows: Table 2.1.1 Operating power voltage OSC1 oscillation circuit Crystal oscillation OSC3 oscillation circuit Not use Operating power voltage 1.8 V–6.4 V Crystal oscillation CR oscillation Use – 2.2 V–6.4 V 2.2 V–6.4 V The S1C63466 operates by applying a single power supply within the above range between VDD and VSS.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.1.1 Voltage for oscillation circuit and internal circuits VD1 is a voltage for the oscillation circuit and the internal logic circuits, and is generated by the oscillation system voltage regulator for stabilizing the oscillation. The S1C63466 is designed with twin clock specification; it has two types of oscillation circuits OSC1 and OSC3 built-in.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C63466 circuits, initial reset must be executed. There are two ways of doing this. (1) External initial reset by the RESET terminal (2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting) The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the reset function.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2.2 Simultaneous low input to terminals K00–K03 Another way of executing initial reset externally is to input a low signal simultaneously to the input ports (K00–K03) selected with the mask option. Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at low level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal operation.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET Table 2.2.3.
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CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C63466 has a 4-bit core CPU S1C63000 built-in as its CPU part. Refer to the "S1C63000 Core CPU Manual" for the S1C63000. Note: The SLP instruction cannot be used because the SLEEP operation is not assumed in the S1C63466. 3.2 Code ROM The built-in code ROM is a mask ROM for loading programs, and has a capacity of 16,384 steps × 13 bits.
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CHAPTER 3: CPU, ROM, RAM (3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data. 0000H 4-bit access area (SP2 stack area) 00FFH 0100H 4/16-bit access area (SP1 stack area) 01FFH 0200H 4-bit access area (Data area) 06FFH 4 bits Fig. 3.3.1 Configuration of data RAM 3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION The peripheral circuits of S1C63466 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit. 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 4.2 Watchdog Timer 4.2.1 Configuration of watchdog timer The S1C63466 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software. The watchdog timer must be reset cyclically by the software while it operates.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 4.2.3 I/O memory of watchdog timer Table 4.2.3.1 shows the I/O address and control bits for the watchdog timer. Table 4.2.3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3 Oscillation Circuit 4.3.1 Configuration of oscillation circuit The S1C63466 has two oscillation circuits (OSC1 and OSC3). OSC1 is either a crystal or a CR oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscillation circuit. When processing with the S1C63466 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3 by the software.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) As shown in Figure 4.3.2.1, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer capacitor (CGX) between the OSC1 and VSS terminals when crystal oscillation is selected. The CR oscillation circuit can be configured simply by connecting the resistor RCR1 between the OSC1 and OSC2 terminals when CR oscillation is selected.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.4 Switching of operating voltage (1) When OSC1 crystal oscillation circuit is used The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). In this case, to obtain stable operation, the operating voltage VD1 for the internal circuits must be switched by the software (VDC register). OSC1 (crystal oscillation) operation: OSC3 operation: VD1 = 1.3 V VD1 = 2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.6 I/O memory of oscillation circuit Table 4.3.6.1 shows the I/O address and the control bits for the oscillation circuit. Table 4.3.6.1 Control bits of oscillation circuit Address Register D3 D2 D1 D0 CLKCHG OSCC 0 VDC R/W R R/W FF00H Name Init ∗1 CLKCHG 0 OSCC 0 0 ∗3 – ∗2 VDC 0 1 OSC3 On 2.2 V Comment 0 OSC1 CPU clock switch OSC3 oscillation On/Off Off Unused 1.3 V CPU operating voltage switch (1.3 V: OSC1, 2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.7 Programming notes (1) When switching the CPU system clock from OSC1 to OSC3, first set VD1. After that maintain 2.5 msec or more, and then turn the OSC3 oscillation ON. When switching from OSC3 to OSC1, set VD1 after switching to OSC1 and turning the OSC3 oscillation OFF. However, when the CR oscillation circuit has been selected as the OSC1 oscillation circuit, it is not necessary to set VD1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00–K03 and K10–K13) 4.4.1 Configuration of input ports The S1C63466 has eight bits general-purpose input ports. Each of the input port terminals (K00–K03, K10–K13) provides internal pull-up resistor. Pull-up resistor can be selected for each bit with the mask option. Figure 4.4.1.1 shows the configuration of input port. Interrupt request Kxx Data bus VDD Address VSS Mask option Fig. 4.4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the input ports K00–K03 and K10–K13, and can specify the terminals for generating interrupt and interrupt timing. The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13 to use for the interrupt.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.4 I/O memory of input ports Table 4.4.4.1 shows the I/O addresses and the control bits for the input ports. Table 4.4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) SIK00–SIK03: K0 port interrupt selection register (FF20H) SIK10–SIK13: K1 port interrupt selection register (FF24H) Selects the ports to be used for the K00–K03 and K10–K13 input interrupts. When "1" is written: Enable When "0" is written: Disable Reading: Valid Enables the interrupt for the input ports (K00–K03, K10–K13) for which "1" has been written into the interrupt selection registers (SIK00–SIK03, SIK10–SIK13).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.5 Programming notes (1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate waiting time. Particular care needs to be taken of the key scan during key matrix configuration.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00–R03, R10–R13 and R20–R23) 4.5.1 Configuration of output ports The S1C63466 has 12 bits general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and N-channel open drain output. Figure 4.5.1.1 shows the configuration of the output port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.3 High impedance control The terminal output status of the output ports can be set to a high impedance status. This control is done using the high impedance control registers. The high impedance control registers are provided to correspond with the output ports as shown below.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) • TOUT (R02) The R02 terminal can output a TOUT signal. The TOUT signal is the clock that is output from the programmable timer, and can be used to provide a clock signal to an external device. To output the TOUT signal, fix the R02 register at "1" and the R02HIZ register at "0", and turn the signal ON and OFF using the PTOUT register. It is, however, necessary to control the programmable timer. Refer to Section 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.5 I/O memory of output ports Table 4.5.5.1 shows the I/O addresses and control bits for the output ports. Table 4.5.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00–R03: R0 output port data register (FF31H) R10–R13: R1 output port data register (FF33H) R20–R23: R2 output port data register (FF35H) Set the output data for the output ports. When "1" is written: High level output When "0" is written: Low level output Reading: Valid The output port terminals output the data written in the corresponding data registers without changing it.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.6 Programming notes (1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1" and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output). Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is written to the R02 and R03 registers when the special output has been selected.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00–P03, P10–P13 and P20–P23) 4.6.1 Configuration of I/O ports The S1C63466 has 12 bits general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O port. Data bus Address VDD Pull-up control register (PUL) Address Address Data register Address I/O control register (IOC) PXX Mask option Fig. 4.6.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.2 Mask option In the I/O ports P10–P13 and P20–P23, the output specification during output mode can be selected from either complementary output or N-channel open drain output by mask option. They are selected in 1-bit units or 4-bit units depending on the terminal group. Note that the P00–P03 can be only used as complementary output.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.5 Special outputs (CL, FR) The I/O ports P22 and P23 can be used as special output ports that output CL and FR signals by switching the function with software. Since P22 and P23 are set to I/O port (input mode) at initial reset, when using the special outputs, select the special output function using the EXLCDC register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.6 I/O memory of I/O ports Tables 4.6.6.1(a) and (b) show the I/O addresses and the control bits for the I/O ports. Table 4.6.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Table 4.6.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) (2) I/O port control P00–P03: P0 I/O port data register (FF42H) P10–P13: P1 I/O port data register (FF46H) P20–P23: P2 I/O port data register (FF4AH) I/O port data can be read and output data can be set through these registers. • When writing data When "1" is written: High level When "0" is written: Low level When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) PUL00–PUL03: P0 port pull-up control register (FF41H) PUL10–PUL13: P1 port pull-up control register (FF45H) PUL20–PUL23: P2 port pull-up control register (FF49H) The pull-up during the input mode are set with these registers. When "1" is written: Pull-up ON When "0" is written: Pull-up OFF Reading: Valid The built-in pull-up resistor which is turned ON during input mode is set to enable in 1-bit units.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7 LCD Driver (COM0–COM16, SEG0–SEG59) 4.7.1 Configuration of LCD driver The S1C63466 has 17 common terminals (COM0–COM16) and 60 segment terminals (SEG0–SEG59), so that it can drive a dot matrix type LCD with a maximum of 1,020 (60 × 17) dots. The driving method is 1/17 duty, 1/16 duty or 1/8 duty dynamic drive with four voltages (1/4 bias), VC1, VC2, VC4 and VC5 (1/5 bias driving can be set by impressing five voltages from outside).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7.3 Mask option Disconnecting the internal power supply for LCD driving will enable voltages to be supplied externally. In such case, the five voltages are entered in VC1, VC2, VC3, VC4 and VC5 terminals and 1/5 bias driving may then be set. Since 1/5 bias driving provides better display quality, when low power current consumption is not required (i.e., when power is supplied from AC outlet), select external power mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Figures 4.7.4.1 and 4.7.4.2 show the dynamic drive waveform for 1/4 bias and 1/5 bias. Drive duty 1/8 1/16 0 1 2 3 0 1 2 3 ..... ..... 7 0 1 2 3 15 0 1 2 3 ..... ..... 7 15 1/17 0 1 2 3 ..... 16 0 1 2 3 ..... 16 (LPAGE = 0) Frame signal 32 Hz ∗ ∗ When fOSC1 = 32.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Drive duty 1/8 0 1 2 3 1/16 1/17 0 1 2 3 0 1 2 3 ..... ..... ..... 7 0 1 2 3 15 0 1 2 3 16 0 1 2 3 ..... ..... ..... 7 (LPAGE = 0) 15 16 Frame signal 32 Hz ∗ ∗ When fOSC1 = 32.768 kHz VC5 VC4 VC3 VC2 VC1 COM0 VSS VC5 VC4 VC3 VC2 COM1 VC1 VSS VC5 VC4 VC3 VC2 COM2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS SEG0 VC5 VC4 VC3 VC2 VC1 VSS SEG1 Fig. 4.7.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7.5 Display memory The display memory is allocated to F000H–F276H in the data memory area and the addresses and the data bits correspond to COM and SEG outputs as shown in Figure 4.7.5.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) When a bit in the display memory is set to "1", the corresponding LCD dot goes ON, and when it is set to "0", the dot goes OFF. At 1/17 (1/16) duty drive, all data of COM0–COM16 (15) is output. At 1/8 duty drive, data only corresponding to COM0–COM7 is output. However, since the display memory has capacity for two screens, it is designed so that the memory for COM8–COM15 shown in Figure 4.7.5.1 (b) can also be used as COM0–COM7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7.7 I/O memory of LCD driver Table 4.7.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.7.1 shows the display memory map. Table 4.7.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VCCHG: LCD regulated voltage switching register (FF60H•D1) Selects the reference voltage for the LCD drive voltage. When "1" is written: VC2 When "0" is written: VC1 Reading: Valid When "1" is written to the VCCHG register, the LCD system voltage circuit generates the LCD drive voltage as VC2 standard. When "0" is written, it becomes VC1 standard. Select VC2 when power supply voltage is 2.6 V or more, otherwise, select VC1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LPAGE: LCD display memory selection register (FF61H•D0) Selects the display memory area at 1/8 duty drive. When "1" is written: F100H–F177H When "0" is written: F000H–F077H Reading: Valid By writing "1" to the LPAGE register, the data set in F100H–F177H (the second half of the display memory) is displayed, and when "0" is written, the data set in F000H–F077H (the first half of the display memory) is displayed.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8 Clock Timer 4.8.1 Configuration of clock timer The S1C63466 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of an 8-bit binary counter that serves as the input clock, fOSC1 divided clock output from the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software. Figure 4.8.1.1 is the block diagram for the clock timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8.3 Interrupt function The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz, 2 Hz and 1 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.8.3.1 is the timing chart of the clock timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8.4 I/O memory of clock timer Table 4.8.4.1 shows the I/O addresses and the control bits for the clock timer. Table 4.8.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TMRUN: Clock timer RUN/STOP control register (FF78H•D0) Controls RUN/STOP of the clock timer. When "1" is written: RUN When "0" is written: STOP Reading: Valid The clock timer enters the RUN status when "1" is written to the TMRUN register, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or the timer is reset.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8.5 Programming notes (1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4– TM7). (2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.9 Stopwatch Timer 4.9.1 Configuration of stopwatch timer The S1C63466 has 1/100 sec unit and 1/10 sec unit stopwatch timer built-in. The stopwatch timer is configured with a 2 levels 4-bit BCD counter which has an input clock approximating 100 Hz signal (signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by software. Figure 4.9.1.1 shows the configuration of the stopwatch timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWD0–SWD3 generates an approximated 10 Hz signal from the basic 256 Hz signal (fOSC1 dividing clock). The count-up intervals are 2/256 sec and 3/256 sec, so that finally two patterns are generated: 25/ 256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.9.4 I/O memory of stopwatch timer Table 4.9.4.1 shows the I/O addresses and the control bits for the stopwatch timer. Table 4.9.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) When data of the counter is read at run mode, proper reading may not be obtained due to the carry from low-order digits (SWD0–SWD3) into high-order digits (SWD4–SWD7) (i.e., in case SWD0–SWD3 and SWD4–SWD7 reading span the timing of the carry). To avoid this occurrence, perform the reading after suspending the counter once and then set the SWRUN to "1" again.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10 Programmable Timer 4.10.1 Configuration of programmable timer The S1C63466 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in. Timer 0 and timer 1 are composed of 8-bit presettable down counters and they can be used as 8-bit × 2 channel programmable timers. Timer 0 also has an event counter function using the K13 input port terminal. Figure 4.10.1.1 shows the configuration of the programmable timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.2 Setting of initial value and counting down Timers 0 and 1 each have a down counter and reload data register. The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial value to the down counter. By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the initial value set in the reload register RLD.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.3 Counter mode The programmable timer can operate in two counter modes, timer mode and event counter mode. It can be selected by software. (1) Timer mode The timer mode counts down using the prescaler output as an input clock. In this mode, the programmable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source. Timer 0 can operate in both the timer mode and the event counter mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 2,048 Hz ∗1 K13 input Counter input clock ∗2 Counter data n n-1 n-2 n-3 ∗1 When fOSC1 is 32.768 kHz ∗2 When PLPOL register is set to "0" Fig. 4.10.3.2 Count down timing with noise rejecter The operation of the event counter mode is the same as the timer mode except it uses the K13 input as the clock. Refer to Section 4.10.2, "Setting of initial value and counting down" for basic operation and control. 4.10.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.5 Interrupt function The programmable timer can generate an interrupt due to an underflow of the timer 0 and timer 1. See Figure 4.10.2.1 for the interrupt timing. An underflow of timer 0 and timer 1 sets the corresponding interrupt factor flag IPT0 (timer 0) or IPT1 (timer 1) to "1", and generates an interrupt. The interrupt can also be masked by setting the corresponding interrupt mask register EIPT0 (timer 0) or EIPT1 (timer 1).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.7 Transfer rate setting for serial interface The signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock source for the serial interface. The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state (PTRUN = "1"). It is not necessary to control with the PTOUT register. PTRUN1 Timer 1 underflow Source clock for serial I/F Fig. 4.10.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.8 I/O memory of programmable timer Table 4.10.8.1 shows the I/O addresses and the control bits for the programmable timer. Table 4.10.8.1 Control bits of programmable timer Address FFC0H FFC1H FFC2H FFC3H FFC4H FFC5H FFC6H FFC7H FFC8H FFC9H FFCAH FFCBH FFE2H FFF2H Register Name Init ∗1 1 0 ∗3 – ∗2 0 EVCNT FCSEL PLPOL EVCNT 0 Event ct.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) CKSEL0: Prescaler 0 source clock selection register (FFC1H•D0) CKSEL1: Prescaler 1 source clock selection register (FFC1H•D1) Selects the source clock of the prescaler. When "1" is written: OSC3 clock When "0" is written: OSC1 clock Reading: Valid The source clock for the prescaler is selected from OSC1 or OSC3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) FCSEL: Timer 0 function selection register (FFC0H•D1) Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode. When "1" is written: With noise rejecter When "0" is written: Without noise rejecter Reading: Valid When "1" is written to the FCSEL register, the noise rejecter is used and counting is done by an external clock (K13) with 0.98 msec* or more pulse width.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) PTRST0: Timer 0 reset (reload) (FFC2H•D1) PTRST1: Timer 1 reset (reload) (FFC3H•D1) Resets the timer and presets reload data to the counter. When "1" is written: Reset When "0" is written: No operation Reading: Always "0" By writing "1" to PTRST0, the reload data in the reload register PLD00–PLD07 is preset to the counter in timer 0. Similarly, the reload data in PLD10–PLD17 is preset to the counter in timer 1 by PTRST1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) EIPT0: Timer 0 interrupt mask register (FFE2H•D0) EIPT1: Timer 1 interrupt mask register (FFE2H•D1) These registers are used to select whether to mask the programmable timer interrupt or not. When "1" is written: Enabled When "0" is written: Masked Reading: Valid Timer 0 and timer 1 interrupts can be masked individually by the interrupt mask registers EIPT0 (timer 0) and EIPT1 (timer 1). At initial reset, these registers are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.9 Programming notes (1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first. Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec (when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY) 4.11.1 Configuration of serial interface The S1C63466 has a synchronous clock type 8 bits serial interface built-in. The configuration of the serial interface is shown in Figure 4.11.1.1. The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.11.2 Mask option (1) Terminal specification Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the mask option that selects the output specification for the I/O port is also applied to the serial interface.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) A sample basic serial input/output portion connection is shown in Figure 4.11.3.1. S1C63466 External serial device S1C63466 External serial device SCLK CLK SCLK CLK SOUT SOUT SOUT SOUT SIN SIN SIN Input terminal SIN SRDY READY (a) Master mode Input terminal (b) Slave mode Fig. 4.11.3.1 Sample basic connection of serial input/output section 4.11.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (2) Serial data input procedure and interrupt The S1C63466 serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is sequentially read in the 8-bit shift register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (5) Timing chart The S1C63466 serial interface timing charts are shown in Figures 4.11.4.2 and 4.11.4.3. SCTRG (W) SCTRG (R) SCLK SIN 8-bit shift register SOUT ISIF SRDY (Slave mode) (a) When SCPS = "1" SCTRG (W) SCTRG (R) SCLK SIN 8-bit shift register SOUT ISIF SRDY (Slave mode) (b) When SCPS = "0" Fig. 4.11.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.11.5 I/O memory of serial interface Table 4.11.5.1 shows the I/O addresses and the control bits for the serial interface. Table 4.11.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) PUL10: SIN (P10) pull-up control register (FF45H•D0) PUL12: SCLK (P12) pull-up control register (FF45H•D2) Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode). When "1" is written: Pull-up ON When "0" is written: Pull-up OFF Reading: Valid Sets the pull-up resistor built into the SIN (P10) and SCLK (P12) terminals to ON or OFF. (Pull-up resistor is only built in the port selected by mask option.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SDP: Data input/output permutation selection register (FF71H•D3) Selects the serial data input/output permutation. When "1" is written: MSB first When "0" is written: LSB first Reading: Valid Select whether the data input/output permutation will be MSB first or LSB first. At initial reset, this register is set to "0". SCTRG: Clock trigger/status (FF70H•D1) This is a trigger to start input/output of synchronous clock (SCLK).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) EISIF: Interrupt mask register (FFE3H•D0) Masking the interrupt of the serial interface can be selected with this register. When "1" is written: Enabled When "0" is written: Masked Reading: Valid With this register, it is possible to select whether the serial interface interrupt is to be masked or not. At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12 Sound Generator 4.12.1 Configuration of sound generator The S1C63466 has a built-in sound generator for generating buzzer signals. Hence, generated buzzer signals (BZ) can be output from the BZ terminal. Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12.3 Control of buzzer output The BZ signal generated by the sound generator is output from the BZ terminal by setting "1" for the buzzer output enable register BZE. When "0" is set to BZE register, the output terminal shifts to the low (VSS) level (negative polarity) or high (VDD) level (positive polarity). BZE register "0" "1" "0" BZ output/BZ terminal (Negative polarity) BZ output/BZ terminal (Positive polarity) Fig. 4.12.3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) TH TL TL TH Level 1 (Max.) Level 1 (Max.) Level 2 Level 2 Level 3 Level 3 Level 4 Level 4 Level 5 Level 5 Level 6 Level 6 Level 7 Level 7 Level 8 (Min.) Level 8 (Min.) (a) Negative polarity (b) Positive polarity Fig. 4.12.4.1 Duty ratio of the buzzer signal waveform Note: When a digital envelope has been added to the buzzer signal, the BDTY0–BDTY2 settings will be invalid due to the control of the duty ratio. 4.12.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12.6 One-shot output The sound generator has a one-shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects. Either 125 msec or 31.25 msec can be selected by SHTPW register for one-shot buzzer signal output time. The output of the one-shot buzzer is controlled by writing "1" into the one-shot buzzer trigger BZSHT.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12.7 I/O memory of sound generator Table 4.12.7.1 shows the I/O addresses and the control bits for the sound generator. Table 4.12.7.1 Control bits of sound generator Address Register D3 D2 ENRTM ENRST FF6CH R/W W 0 BZSTP R W 0 BZFQ2 FF6DH FF6EH R 0 FF6FH R BDTY2 Name Init ∗1 1 0 ENRTM 0 1 sec 0.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) BDTY0–BDTY2: Duty level selection register (FF6FH•D0–D2) Selects the duty ratio of the buzzer signal as shown in Table 4.12.7.3. Table 4.12.7.3 Duty ratio setting Level BDTY2 BDTY1 BDTY0 Level 1 (Max.) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min.) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Duty ratio by buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) SHTPW: One-shot buzzer pulse width setting register (FF6DH•D0) Selects the output time of the one-shot buzzer. When "1" is written: 125 msec When "0" is written: 31.25 msec Reading: Valid Writing "1" into SHTPW causes the one-short output time to be set at 125 msec, and writing "0" causes it to be set to 31.25 msec. It does not affect normal buzzer output. At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 4.13 SVD (Supply Voltage Detection) Circuit 4.13.1 Configuration of SVD circuit The S1C63466 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. It is possible to check an external voltage drop, other than the supply voltage, by mask option. Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be done with software. Figure 4.13.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) When the SVDON register is set to "1", source voltage or external voltage detection by the SVD circuit is executed. As soon as the SVDON register is reset to "0", the result is loaded to the SVDDT latch and the SVD circuit goes OFF. To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 4.13.5 Programming notes (1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4. Set SVDON to "1" Maintain for 100 µsec minimum Set SVDON to "0" Read SVDDT (2) The SVD circuit should normally be turned OFF because SVD operation increase current consumption.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14 Interrupt and HALT The S1C63466 provides the following interrupt functions.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) IPT0 NMI interrupt request Watchdog timer EIPT0 IPT1 EIPT1 ISIF Interrupt vector generation circuit EISIF K00 Program counter (low-order 4 bits) KCP00 SIK00 K01 KCP01 INT interrupt request SIK01 IK0 K02 EIK0 KCP02 Interrupt flag SIK02 K03 KCP03 SIK03 K10 KCP10 SIK10 K11 KCP11 Interrupt factor flag SIK11 IK1 K12 Interrupt mask register EIK1 KCP12 Input comparison register SIK12 Interrupt selection register K13 KCP13 SIK13
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.1 Interrupt factor Table 4.14.1.1 shows the factors for generating interrupt requests. The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are established. • The corresponding mask register is "1" (enabled) • The interrupt flag is "1" (EI) The interrupt factor flag is reset to "0" when "1" is written.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.2 Interrupt mask The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is set to "0". Table 4.14.2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.4 I/O memory of interrupt Tables 4.14.4.1(a) and (b) show the I/O addresses and the control bits for controlling interrupts. Table 4.14.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.14.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.5 Programming notes (1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt mask registers are set to "0". (2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset.
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CHAPTER 5: SUMMARY OF NOTES CHAPTER 5 SUMMARY OF NOTES 5.1 Notes for Low Current Consumption The S1C63466 contains control registers for each of the circuits so that current consumption can be reduced. These control registers reduce the current consumption through programs that operate the circuits at the minimum levels. The following lists the circuits that can control operation and their control registers. Refer to these when programming. Table 5.1.
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CHAPTER 5: SUMMARY OF NOTES 5.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. Memory and stack (1) Memory is not implemented in unused areas within the memory map. Further, some non-implementation areas and unused (access prohibition) areas exist in the display memory area and the peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed. Refer to Section 4.7.
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CHAPTER 5: SUMMARY OF NOTES Input port (1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate waiting time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression.
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CHAPTER 5: SUMMARY OF NOTES Stopwatch timer (1) When data of the counter is read at run mode, perform the reading after suspending the counter once and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976 µsec (1/4 cycle of 256 Hz). (2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequencies and times differ from the values described in this section because the oscillation frequency will be 60 kHz (Typ.).
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CHAPTER 5: SUMMARY OF NOTES Sound generator (1) Since it generates a BZ signal that is out of synchronization with the BZE register, hazards may at times be produced when the signal goes ON/OFF due to the setting of the BZE register. (2) The one-shot output is only valid when the normal buzzer output is OFF (BZE = "0") and will be invalid when the normal buzzer output is ON (BZE = "1"). (3) The buzzer signal is generated by dividing the OSC1 oscillation clock.
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CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM • When negative polarity is selected for buzzer output (mask option selection) SVD CA CB CC CD CE CF TEST VDD C2 C3 + CP C4 C9 VD1 VREF CGX OSC1 RCR1 P00–P03 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P20 S1C63466 P21 P22 (CL) [The potential of the substrate P23 (FR) (back of the chip) is VSS.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Rating (VSS=0V) Item Rated value Unit Symbol Supply voltage -0.5 to 7.0 V VDD Input voltage (1) VI -0.5 to VDD + 0.3 V Input voltage (2) VIOSC -0.5 to VD1 + 0.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.3 DC Characteristics Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF Min. Typ. Condition Item Symbol 0.8·VDD K00–03, K10–13 High level input voltage (1) VIH1 P00–03, P10–13, P20–23 RESET, TEST 0.9·VDD High level input voltage (2) VIH2 VIL1 K00–03, K10–13 0 Low level input voltage (1) P00–03, P10–13, P20–23 VIL2 RESET, TEST 0 Low level input voltage (2) IIH K00–03, K10–13 VIH=3.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.4 Analog Circuit Characteristics and Power Current Consumption Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF Condition Item Symbol Min. Typ. Max. Unit Connect 1 MΩ load resistor LC0–3="0" LCD drive voltage VC1 0.975 V (when VC1 standard is selected) LC0–3="1" between VSS and VC1 0.990 (without panel load) LC0–3="2" 1.005 LC0–3="3" 1.020 LC0–3="4" 1.035 LC0–3="5" 1.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, RCR1=600kΩ, RCR2=47kΩ, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF Item Symbol Min. Typ. Max. Unit Condition SVD voltage VSVD1 SVDS0–3="0" (internal) 1.85 V 1.90 SVDS0–3="1" 2.00 SVDS0–3="2" 2.10 SVDS0–3="3" 2.20 SVDS0–3="4" 2.30 SVDS0–3="5" 2.40 SVDS0–3="6" Typ. 2.50 Typ. SVDS0–3="7" ×0.93 2.60 ×1.07 SVDS0–3="8" 2.70 SVDS0–3="9" 2.80 SVDS0–3="10" 2.90 SVDS0–3="11" 3.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. OSC1 crystal oscillation circuit Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS OSC1 CR oscillation frequency-resistance characteristic The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values and evaluate the characteristics on the actual product. 120k VDD = 2.2 to 6.4 V VSS = 0 V Ta = 25°C Typ.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.6 Serial Interface AC Characteristics Clock synchronous master mode • During 32 kHz operation Condition: VDD=3.0V, VSS=0V, Ta=25°C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Min. Typ. Item Symbol tsmd Transmitting data output delay time 10 tsms Receiving data input set-up time tsmh 5 Receiving data input hold time Max. 5 Unit µs µs µs Max. 200 Unit ns ns ns Max. 10 Unit µs µs µs Max. 500 Unit ns ns ns • During 1 MHz operation Condition: VDD=3.
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CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.7 Timing Chart System clock switching ∗ 1 instruction execution time or longer ∗ VDC 2.5 msec min. ∗ OSCC 5 msec min. CLKCHG Note: When the OSC1 oscillation circuit has been selected as the CR oscillation circuit, it is not necessary to set the VDC register. Whether the VDC register value is "1" or "0" does not matter.
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CHAPTER 8: PACKAGE CHAPTER 8 PACKAGE 8.1 Plastic Package QFP8-144pin (Unit: mm) 31.2±0.4 28±0.1 108 73 31.2±0.4 72 28±0.1 109 INDEX 37 3.35±0.1 1 36 0.65 0.3±0.1 0.15±0.05 0° 10° 0.6±0.2 0.1 3.65max 144 1.6 The dimensions are subject to change without notice.
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CHAPTER 8: PACKAGE QFP17-144pin (Unit: mm) 22±0.4 20±0.1 108 73 20±0.1 22±0.4 72 109 INDEX 37 144 0.5 3max 2.7±0.1 1 +0.1 36 0.2–0.05 0.1 0.15±0.05 0° 10° 0.5±0.2 1 The dimensions are subject to change without notice.
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CHAPTER 8: PACKAGE QFP5-128pin (Unit: mm) 23.6±0.4 20±0.1 102 65 14±0.1 INDEX 39 128 1 38 0.2±0.05 0.1 2.7±0.1 0.5 3max 17.6±0.4 64 103 0.15±0.05 0° 10° 0.8±0.2 1.8 The dimensions are subject to change without notice.
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CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples QFP8-144pin (Unit: mm) 36.93±0.30 28.00±0.28 73 72 144 37 28.00±0.28 109 1 36 0.30±0.05 0.15 0.20 Typ. 3.05 Max. 0.65±0.05 120 36.93±0.30 108 1.20 Typ.
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CHAPTER 8: PACKAGE QFP17-144pin (Unit: mm) 22.00±0.25 19.20±0.19 73 72 144 37 19.20±0.19 109 1 22.00±0.25 108 36 0.20 0.15 2.80 Max 0.50 0.50±0.
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CHAPTER 8: PACKAGE QFP5-128pin (Unit: mm) 23.90 ±0.30 20.00 ±0.18 102 65 64 128 39 14.00 ±0.14 17.91 ±0.30 103 1 38 0.2 0.40 ±0.08 CERAMIC 0.15 0.95 ±0.08 0.76 ±0.08 2.79 MAX 0.5 122 0.20 TYP GLASS EPSON 0.80 ±0.
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CHAPTER 9: PAD LAYOUT CHAPTER 9 PAD LAYOUT 9.1 Diagram of Pad Layout 35 30 25 20 15 10 5 1 140 Die No. 40 135 45 130 125 55 X (0, 0) 120 5.14 mm Y 50 60 115 65 110 70 75 80 85 90 95 100 105 5.
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CHAPTER 9: PAD LAYOUT 9.2 Pad Coordinates Unit: µm No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 1 2 N.C. N.C. 2218 2058 2445 2445 36 37 N.C. N.C. -2440 -2595 2445 2293 71 72 N.C. N.C.
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) This manual describes how to use the Peripheral Circuit Board for the S1C63404/454/455/458/466/P466 (S5U1C63000P), which provides emulation functions when mounted on the debugging tool for the S1C63 Family of 4-bit single-chip microcomputers, the ICE (S5U1C63000H1/S5U1C63000H2).
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) (4) Register monitor pins These pins correspond one-to-one to the registers listed below. The pin outputs a high for logic "1" and a low for logic "0". Monitor LED Pin No. Name LED No.
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) (7) RESET switch This switch initializes the internal circuits of this board and feeds a reset signal to the ICE. (8) Monitor pins and external part connecting socket These parts are currently unused. (9) IOSEL2 When downloading circuit data, set IOSEL2 to the "E" position. Otherwise, set to the "D" position.
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) A.2 Connecting to the Target System This section explains how to connect the S5U1C63000P to the target system. To connect this board (S5U1C63000P) to the target system, use the I/O connecting cables supplied with the board (80-pin/40-pin × 2, flat type). Take care when handling the connectors, since they conduct electrical power (VDD = +3.3 V).
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) Table A.2.1 I/O connector pin assignment 40-pin CN1-1 connector 40-pin CN1-2 connector No. Pin name No. Pin name 1 VDD (=3.3 V) 1 VDD (=3.3 V) 2 VDD (=3.3 V) 2 VDD (=3.
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) A.3 Usage Precautions To ensure correct use of this board (S5U1C63000P), please observe the following precautions. A.3.1 Operational precautions (1) Before inserting or removing cables, turn off power to all pieces of connected equipment. (2) Do not turn on power or load mask option data if all of the input ports (K00–K03) are held low. Doing so may activate the multiple key entry reset function.
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) (3) Functional precautions - There is a finite delay time from the point at which the LCD power supply circuit (LPWR) turns on until an LCD drive waveform is output. On this board, this delay is set to approx. 125 msec, which differs from that of the actual IC. Refer to the technical manual for the S1C63404/454/455/458/466/ P466.
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APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) ∗1 When this tool is used for the S1C63404/458/466/P466: - Although the S1C63404/458/466/P466 has a function for detecting externally sourced voltages, this board is unable to detect externally sourced voltages. The SVD function is realized by artificially varying the power supply voltage using the VSVD control on this board.
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