MF1072-04 S1D13504 Series Technicl Manual Dot Matrix Graphics LCD Controller S1D13504 Series Technical Manual S1D13504 Series Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle papaer, and printed using soy-based inks.
NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
Tobira.
ll er o s r e t ri n 4 0 5 3 hic 1 D p S1 Gra x ri t a D M t o o e C S D i ct n u F LC wareation rd cific a H pe S l a n o
CONTENTS Contents Table of Contents 1 INTRODUCTION .........................................................................................................................1-1 1.1 Scope ............................................................................................................................................1-1 1.2 Overview Description ....................................................................................................................1-1 2 FEATURES ........................
CONTENTS FPM-DRAM Write Timing ........................................................................................................ 1-36 FPM-DRAM Read-Write Timing ............................................................................................. 1-37 FPM-DRAM CAS# Before RAS# Refresh Timing.................................................................... 1-38 FPM-DRAM Self-Refresh Timing............................................................................................. 1-38 7.
CONTENTS 13.4 Pin States in Power Save Modes ..............................................................................................1-100 14 MECHANICAL DATA ..............................................................................................................1-101 14.1 QFP15-128pin (S1D13504F00A) ..............................................................................................1-101 14.2 TQFP15-128pin (S1D13504F01A) ...............................................................
CONTENTS List of Figures Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 4-1 Figure 5-1 Figure 5-2 Figure 5-3 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11 Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 Figure 7-16 Figure 7-17 Figure 7-18 Figure 7-19 Figure 7-20 Figure 7-21 Figure 7-22 Figure 7-23 Figure 7-24 Figure 7-25 Figure 7-26 Figure 7-27 Figure 7-28 Figure 7-29 Figure 7-30 Figure 7-31 Figure 7-32 Figure 7-33 Figure 7-34
CONTENTS Figure 7-41 Figure 7-42 Figure 7-43 Figure 7-44 Figure 7-45 Figure 7-46 Figure 9-1 Figure 10-1 Figure 10-2 Figure 10-3 Figure 12-1 Figure 12-2 Figure 12-3 Figure 12-4 Figure 12-5 Figure 12-6 Figure 12-7 Figure 14-1 Figure 14-2 Figure 14-3 Dual Color 16-Bit Panel A.C. Timing ..................................................................................1-58 16-Bit TFT Panel Timing ....................................................................................................1-59 TFT A.C.
CONTENTS Table 7-14 Table 7-15 Table 7-16 Table 7-17 Table 7-18 Table 7-19 Table 7-20 Table 7-21 Table 7-22 Table 7-23 Table 7-24 Table 7-25 Table 7-26 Table 7-27 Table 7-28 Table 7-29 Table 7-30 Table 7-31 Table 7-32 Table 7-33 Table 7-34 Table 7-35 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table 8-7 Table 8-8 Table 8-9 Table 8-10 Table 8-11 Table 8-12 Table 8-13 Table 8-14 Table 8-15 Table 9-1 Table 11-1 Table 11-2 Table 11-3 Table 12-1 Table 13-1 Table 13-2 1-vi EDO DRAM Read-Write T
1: INTRODUCTION 1 INTRODUCTION 1.1 Scope This is the Functional Specification for the S1D13504 Color Graphics LCD/CRT Controller Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. 1.2 Overview Description The S1D13504 is a low cost, low power color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs.
2: FEATURES 2 FEATURES 2.1 Memory Interface • 16-bit DRAM interface: - EDO-DRAM up to 40MHz data rate (80M bytes per second). - FPM-DRAM up to 25MHz data rate (50M bytes per second). • Memory size options: - 512K bytes using one 256K×16 device. - 2M bytes using one 1M×16 device. • A configuration register can be programmed to enhance performance by tailoring the memory control output timing to the DRAM device. 2.2 CPU Interface • Supports the following interfaces: - 8/16-bit Hitachi SH-3 bus interface.
2: FEATURES 2.4 Display Modes • 1/2/4/8/16 bit-per-pixel modes supported on LCD. • 1/2/4/8 bit-per-pixel modes supported on CRT. • Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16 × 4 Look-Up Table is used to map 1/2/4 bit-per-pixel modes into these shades.
3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS 3 TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS Power Management Oscillator CSn# CS# A[20:0] AB[20:0] D[15:0] DB[15:0] WE1# SUSPEND# M/R# A21 CLKI SH-3 BUS WE1# BS# S1D13504 BS# RD/WR# RD/WR# RD# WE0# WAIT# WAIT# UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE RD# WE0# FPDAT[15:8] DRDY FPLINE MOD UCAS# UCAS# RAS# LCAS# LCAS# WE# RAS# MD[15:0] WE# RESET# MA[11:0] RESET# A[11:0] BUSCL
3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS Power Management Oscillator M/R# Decoder CS# Decoder A[20:0] AB[20:0] D[31:16] DB[15:0] DS# WE1# AS# BS# R/W# SUSPEND# A[31:21] FC0, FC1 CLKI MC68030 BUS S1D13504 RD/WR# SIZ1 RD# SIZ0 WE0# DSACK1# FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE DRDY FPLINE MOD WAIT# UCAS# UCAS# RAS# LCAS# WE# LCAS# RAS# MD[15:0] WE# RESET# MA[8:0] RESET# A[8:0] BUSCLK D[15:0] LC
4: BLOCK DESCRIPTION 4 BLOCK DESCRIPTION 4.1 Functional Block Diagram 16-bit FPM/EDO DRAM Memory Controller Register Power Save Clocks CPU R/W LCD Display FIFO Host CPU / MPU I/F I/F LCD DAC Data Look-Up Table DAC Control CRTC Bus Clock Memory Clock Pixel Clock Figure 4-1 System Block Diagram Showing Datapaths 4.2 Functional Block Descriptions 4.2.
5: PIN OUT 5 PIN OUT 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD0 MD14 5.
5: PIN OUT 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD0 MD14 5.
5: PIN OUT 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 S1D13504F02A 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 NC NC MD1 MD13 MD2 MD12 MD3 MD11 MD4 MD10 MD5 MD9 MD6 MD8 MD7 VSS LCAS# UCAS# WE# RAS# IOVDD MA9 MA11 MA8 MA10 MA7 MA0 MA6 MA1 MA5 MA2 MA4 MA3 COREVDD NC NC NC NC AB2 AB1 AB0 CS# M/R# BS# RD# WE0# WE1# RD/WR# RESET# GPIO0 WAIT# IOV
5: PIN OUT 5.4 Pin Description Key: I O I/O P C CD = Input = Output = Bi-Directional (Input/Output) = Power pin = CMOS level input = CMOS level input with pull-down resistor (typical values of 100KΩ/180KΩ at 5V/3.3V respectively) = CMOS level Schmitt input = CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) = Tri-state CMOS output driver, x denotes driver type (1=3/-1.
5: PIN OUT Table 5-1 Host Interface Pin Descriptions Pin Names Type Pin # F00A, F02A F01A 108 122 Driver Reset = 0 Value C Hi-Z BUSCLK I BS# I 6 8 CS Hi-Z RD/WR# I 10 12 CS Hi-Z RD# I 7 9 CS Hi-Z WE0# I 8 10 CS Hi-Z WAIT# O 13 15 TS2 Hi-Z RESET# I 11 13 CS Input 0 S1D13504 SERIES HARDWARE FUNCTIONAL SPECIFICATION (X19A-A-002-17) Description System bus clock. See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16. This pin has multiple functions.
5: PIN OUT 5.4.2 Memory Interface Pin Names Type LCAS# O UCAS# O WE# O RAS# MD[15:0] O I/O MA[8:0] O MA9 I/O MA10 I/O MA11 I/O Table 5-2 Memory Interface Pin Descriptions Pin # Reset F00A, Driver Description F02A = 0 Value F01A 50 56 CO1 Output 1 This pin has multiple functions. • For dual CAS# DRAM, this is the column address strobe for the lower byte (LCAS#). • For single CAS# DRAM, this is the column address strobe (CAS#).
5: PIN OUT 5.4.3 LCD Interface Table 5-3 LCD Interface Pin Descriptions Pin Names Type Pin # F00A, F02A F01A 88 98 82–75 92–85 95–89 105–99 Driver FPDAT[8:0] O FPDAT[15:9] O FPFRAME FPLINE FPSHIFT LCDPWR O O O O 69 70 73 71 79 80 83 81 CN3 CN3 CN3 CO1 DRDY O 72 82 CN3 Reset = 0 Value Description CN3 Output 0 Panel Data CN3 Output 0 These pins have multiple functions. • Panel Data for 16-bit panels . • Pixel Data for external RAMDAC support.
5: PIN OUT Pin Names Type DACRS0 I/O DACP0 I/O HRTC I/O VRTC I/O BLANK# I/O DACCLK O Table 5-5 CRT and RAMDAC Interface Pin Descriptions Pin # Reset F00A, Driver Description F02A = 0 Value F01A 100 114 C/TS1 Hi-Z / This pin has multiple functions. Output 0 • Register Select bit 0 for external RAMDAC support. (∗1) • General Purpose IO (GPIO8). See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,” on page 17. 98 112 C/CN3 Hi-Z / This pin has multiple functions.
5: PIN OUT 5.4.
5: PIN OUT 5.5 Summary of Configuration Options Pin Name MD0 MD[3:1] MD4 MD5 MD[7:6] MD8 MD9 MD10 MD[15:11] Table 5-8 Summary of Power On / Reset Options Value on this pin at rising edge of RESET# is used to configure: (1/0) 1 0 8-bit host bus interface 16-bit host bus interface Select host bus interface: 000 = SH-3 bus interface 001 = MC68K bus 1 (e.g. MC68000) 010 = MC68K bus 2 (e.g. MC68030) 011 = Generic bus interface (e.g.
5: PIN OUT Table 5-11 LCD, CRT, RAMDAC Interface Pin Mapping Monochrome Passive Panel S1D13504 Pin Names Single 4-bit FPFRAME FPLINE FPSHIFT DRDY FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 DACRD# BLANK# DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC DACCLK driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 8-bit Dual Single 8-bit 4-bit MOD D0 LD0 D1 LD1 D2 LD2 D3 LD3
6: D.C. CHARACTERISTICS 6 D.C. CHARACTERISTICS Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time Symbol CoreVDD IOVDD VIN TOPR Table 6-2 Recommended Operating Conditions Parameter Condition Min. Typ. Supply Voltage VSS = 0 V 2.7 3.0/3.3 Supply Voltage VSS = 0 V 2.7 3.0/3.3/5.0 Input Voltage VSS Operating Temperature -40 25 Symbol VIL VIH VT+ VT- IIZ CIN HRPD Symbol VOL VOH 1-18 Table 6-1 Absolute Maximum Ratings Rating VSS - 0.
7: A.C. CHARACTERISTICS 7 A.C. CHARACTERISTICS Conditions: IOVDD = 2.7V to 5.
7: A.C. CHARACTERISTICS 7.1 CPU Interface Timing 7.1.1 SH-3 Interface Timing t1 t2 t3 CKIO t4 t5 A[20:0], M/R# RD/WR# t6 t7 BS# t8 t12 CSn# t10 t9 WEn# RD# t12 t11 WAIT# t14 t13 D[15:0](write) t15 t16 D[15:0](read) Figure 7-1 SH-3 Interface Timing Note: The SH-3 Wait State Control Register for the area in which the S1D13504 resides must be set to a non-zero value.
7: A.C. CHARACTERISTICS TCKIO CKIO t1 A[20:0] Valid M/R# t3 t2 t4 CSn# t5 t5 RD/WR# WE0#, WE1# t7 t8 t9 Hi-Z Hi-Z Valid D[15:0] t10 t10 BS# t6 t11 t13 t12 Hi-Z t13 Hi-Z WAIT# Figure 7-2 SH-3 Write Bus Timing Note: The SH-3 Wait State Control Register for the area in which the S1D13504 resides must be set to a non-zero value.
7: A.C. CHARACTERISTICS 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000) t1 t2 t3 CLK t5 t4 A[20:1] M/R# t6 CS# t16 AS# UDS# LDS# t8 t7 R/W# t9 t10 DTACK# t12 t11 D[15:0](write) t13 t14 t15 D[15:0](read) Figure 7-3 MC68000 Bus 1 InterfaceTiming Table 7-3 MC68000 Bus 1 InterfaceTiming 3.3V Symbol Parameter Min. Max.
7: A.C. CHARACTERISTICS TCLK CLK A[20:1] CS# M/R# Valid t1 t2 AS# LDS# UDS# Invalid R/W# t3 DTACK# Hi-Z Hi-Z t7 t6 D[15:0] t5 t4 t8 Hi-Z Hi-Z Valid Figure 7-4 MC68000 Read Bus Timing Table 7-4 MC68000 Read Bus Timing 3.
7: A.C. CHARACTERISTICS 7.1.3 MC68K Bus 2 Interface Timing (e.g.
7: A.C.
7: A.C. CHARACTERISTICS 7.1.
7: A.C. CHARACTERISTICS TBCLK BCLK t1 t2 t2 t1 A[20:0] M/R# Valid t1 t2 t1 t2 t1 CS# t2 t3 t2 t1 WE0# WE1# t5 t4 Hi-Z Hi-Z Valid D[15:0] t6 t7 t8 Hi-Z Hi-Z WAIT# Figure 7-8 Generic Write Bus Synchronous Timing Table 7-8 Generic Write Bus Synchronous Timing Symbol 3.
7: A.C. CHARACTERISTICS 7.1.5 Generic MPU Interface Asynchronous Timing TBCLK BCLK A[20:0] M/R# Valid t1 CS# t2 t3 RD0#,RD1# WE0#,WE1# Hi-Z t5 t4 Hi-Z WAIT# t7 t6 D[15:0](write) Hi-Z t9 t8 D[15:0](read) Hi-Z Valid t10 Hi-Z Hi-Z Valid Figure 7-9 Generic MPU Interface Asynchronous Timing Table 7-9 Generic MPU Interface Asynchronous Timing Symbol 3.
7: A.C. CHARACTERISTICS TBCLK BCLK A[20:0] M/R# Valid t1 CS# t3 t2 WE0# WE1# t5 t4 Hi-Z Hi-Z Valid D[15:0] t7 t6 Hi-Z Hi-Z WAIT# Figure 7-10 Generic Write Bus Asynchronous Timing Table 7-10 Generic Write Bus Asynchronoud Timing Symbol 3.3V Parameter Min.
7: A.C. CHARACTERISTICS 7.2 Clock Input Requirements Clock Input Waveform tPWH tPWL VIH VIL TCLKI Figure 7-11 Clock Input Requirements Table 7-11 Clock Input Requirements Symbol Parameter TCLKI Input Clock Period (CLKI) TPCLK Pixel Clock Period (PCLK) not shown TMCLK Memory Clock Period (MCLK) not shown tPWH Input Clock Pulse Width High (CLKI) tPWL Input Clock Pulse Width Low (CLKI) Min. 12.5 25 25 45% 45% Typ. Max.
7: A.C. CHARACTERISTICS 7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read Timing t1 Memory Clock t2 t3 MA t4 t5 R C1 t7 t6 C2 t8 t9 C3 C4 RAS# CAS# t10 t11 t14 t12 t16 t15 t13 MD(Read) d1 d2 d3 d4 Figure 7-12 EDO-DRAM Read Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 Table 7-12 EDO DRAM Read Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.3.2 EDO-DRAM Write Timing t1 Memory Clock t2 MA t5 t4 t3 R C1 t6 t8 C2 C3 t9 C4 t7 RAS# CAS# WE# t13 t12 t10 t11 t14 MD(Write) d1 d2 t15 d3 d4 Figure 7-13 EDO-DRAM Write Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 1-32 Table 7-13 EDO DRAM Write Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.3.3 EDO-DRAM Read-Write Timing t1 Memory Clock t2 t3 MA t4 t5 R C1 t6 C2 C3 RAS# CAS# WE# t8 t7 t10 t9 MD(Read) d1 d2 MD(Write) d3 Figure 7-14 EDO-DRAM Read-Write Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Table 7-14 EDO DRAM Read-Write Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.3.4 EDO-DRAM CAS Before RAS Refresh Timing t1 Memory Clock t2 t3 RAS# CAS# t4 t5 t6 Figure 7-15 EDO-DRAM CAS Before RAS Refresh Timing Symbol t1 t2 t3 t4 t5 t6 Table 7-15 EDO-DRAM CAS Before RAS Refresh Timing Parameter Min. Memory clock period 25 RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) 1.45 t1 RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) 0.
7: A.C. CHARACTERISTICS 7.3.6 FPM-DRAM Read Timing t1 Memory Clock t2 t3 t5 t4 C1 R MA t8 t6 C2 C3 t9 C4 t7 RAS# CAS# t10 t11 t12 t15 t13 t14 MD(Read) d1 d2 d3 d4 Figure 7-17 FPM-DRAM Read Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Table 7-17 FPM DRAM Read Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.3.7 FPM-DRAM Write Timing t1 Memory Clock t2 t3 t5 t4 C1 R MA t6 t8 C2 C3 t9 C4 t7 RAS# CAS# WE# t12 t10 t13 t11 t14 MD(Write) d1 d2 t15 d3 d4 Figure 7-18 FPM-DRAM Write Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 1-36 Table 7-18 FPM-DRAM Write Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.3.8 FPM-DRAM Read-Write Timing t1 Memory Clock t2 t3 t4 t5 C1 R MA t6 C2 C3 RAS# CAS# WE# t8 t7 t10 t9 MD(Read) d1 d2 MD(Write) d3 Figure 7-19 FPM-DRAM Read-Write Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Table 7-19 FPM-DRAM Read-Write Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing t1 Memory Clock t2 t3 RAS# CAS# t5 t4 t6 Figure 7-20 FPM-DRAM CAS# Before RAS# Refresh Timing Symbol t1 t2 t3 t4 t5 t6 Table 7-20 FPM-DRAM CAS# Before RAS# Refresh Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.4 Display Interface 7.4.1 Power On / Reset Timing TRESET# RESET# LCD ENABLE (REG[0Dh] bit 0) Inactive LCDPWR Active Active FPFRAME FPLINE FPSHIFT FPDAT[15:0] DRDY Active t1 t2 Figure 7-22 LCD Panel Power On / Reset Timing Table 7-22 LCD Panel Power On / Reset Timing Symbol Parameter Min. TRESET# RESET# pulse time 100 LCD Enable bit high to FPLINE, FPSHIFT, FPDAT[15:0], DRDY active Typ.
7: A.C. CHARACTERISTICS 7.4.2 Suspend Timing SUSPEND# Software Suspend Note 1 t1 Note 2 CLKI t2 LCDPWR FPFRAME t3 Inactive Active Active t4 FPLINE DRDY Active FPSHIFT FPDAT[15:0] Active t5 Active Inactive Active t6 Memory Access t7 Allowed Allowed Not Allowed Figure 7-23 LCD Panel Suspend Timing Symbol t1 t2 t3 t4 t5 t6 t7 Table 7-23 LCD Panel Suspend Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.4.3 Single Monochrome 4-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD LINE1 UD[3:0], UD[3:0] LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-1 1-5 1-317 UD2 1-2 1-6 1-318 UD1 1-3 1-7 1-319 UD0 1-4 1-8 1-320 ∗ Example timing for a 320x240 panel. Diagram drawn with 2 FPLINE vertical blank period.
7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 t14 1 UD[3:0] 2 Figure 7-25 Single Monochrome 4-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-24 Single Monochrome 4-Bit Panel A.C. Timing Parameter Min. Typ.
7: A.C. CHARACTERISTICS 7.4.4 Single Monochrome 8-Bit Panel Timing VDP VNDP FPFRAME FPLINE MOD UD[3:0], LD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-1 1-9 1-633 UD2 1-2 1-10 1-634 UD1 1-3 1-11 1-635 UD0 1-4 1-12 1-636 LD3 1-5 1-13 1-637 LD2 1-6 1-14 1-638 LD1 1-7 1-15 1-639 LD0 1-8 1-16 1-640 ∗ Example timing for a 640x480 panel. Diagram drawn with 2 FPLINE vertical blank period.
7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 UD[3:0] LD[3:0] t14 1 2 Figure 7-27 Single Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-25 Single Monochrome 8-Bit Panel A.C. Timing Parameter Min. Typ.
7: A.C. CHARACTERISTICS 7.4.5 Single Color 4-Bit Panel Timing VNDP VDP FPFRAME FPLINE MOD UD[3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-R1 1-G2 1-B3 1-B319 UD2 1-G1 1-B2 1-R4 1-R320 UD1 1-B1 1-R3 1-G4 1-G320 UD0 1-R2 1-G3 1-B4 1-B320 ∗ Example timing for a 640x480 panel. Diagram drawn with 2 FPLINE vertical blank period.
7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 t14 1 UD[3:0] 2 Figure 7-29 Single Color 4-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-26 Single Color 4-Bit Panel A.C. Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.4.
7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t4 t3 FPLINE Data Timing FPLINE t5a t5b t6 t8a t7 t9 t10 t11 FPSHIFT t8b FPSHIFT2 t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-31 Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol t1 t2 t3 t4 t5a t5b t6 t7 t8a t8b t9 t10 t11 t12 t13 Table 7-27 Single Color 8-Bit Panel A.C. Timing (Format 1) Parameter Min. Typ.
7: A.C. CHARACTERISTICS 7.4.7 Single Color 8-Bit Panel Timing (Format 2) VDP VNDP FPFRAME FPLINE MOD LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 FPLINE MOD HDP HNDP FPSHIFT UD3 1-R1 1-B3 1-G6 1-G638 UD2 1-G1 1-R4 1-B6 1-B638 UD1 1-B1 1-G4 1-R7 1-R639 UD0 1-R2 1-B4 1-G7 1-G639 LD3 1-G2 1-R5 1-B7 1-B639 LD2 1-B2 1-G5 1-R8 1-R640 LD1 1-R3 1-B5 1-G8 1-G640 LD0 1-G3 1-R6 1-B8 1-B640 ∗ Example timing for a 640x480 panel.
7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-33 Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-28 Single Color 8-Bit Panel A.C. Timing (Format 2) Parameter Min. Typ.
7: A.C. CHARACTERISTICS 7.4.
7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t10 t11 FPSHIFT t12 UD[7:0] LD[7:0] t13 1 2 Figure 7-35 Single Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-29 Single Color 16-Bit Panel A.C. Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.4.9 Dual Monochrome 8-Bit Panel Timing VNDP VDP FPFRAME FPLINE MOD UD[3:0], LD[3:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 FPLINE MOD HNDP HDP FPSHIFT UD3 1-1 1-5 UD2 1-2 1-6 1-638 UD1 1-3 1-7 1-639 1-637 UD0 1-4 1-8 1-640 LD3 241-1 241-5 241-637 LD2 241-2 241-6 241-638 LD1 241-3 241-7 241-639 LD0 241-4 241-8 241-640 ∗ Example timing for a 640x480 panel.
7: A.C. CHARACTERISTICS t1 Sync Timing t2 FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t10 t11 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-37 Dual Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-30 Dual Monochrome 8-Bit Panel A.C. Timing Parameter Min. Typ.
7: A.C. CHARACTERISTICS 7.4.
7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-39 Dual Color 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-31 Dual Color 8-Bit Panel A.C. Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.4.
7: A.C. CHARACTERISTICS t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[7:0] LD[7:0] t13 1 2 Figure 7-41 Dual Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Table 7-32 Dual Color 16-Bit Panel A.C. Timing Parameter Min.
7: A.C. CHARACTERISTICS 7.4.12 16-Bit TFT Panel Timing VNDP VDP FPFRAME FPLINE R [5:1], G [5:0], B[5:1] LINE480 LINE1 LINE480 DRDY FPLINE HDP HNDP1 HNDP2 FPSHIFT DRDY R [5:1] G [5 :0] B[5 :1 ] 1-1 1-2 1-640 1-1 1-2 1-640 1-1 1-2 1-640 Note: Example Timing for 640x480 panel. DRDY is used to indicate the first pixel.
7: A.C. CHARACTERISTICS t8 t9 FPFRAME t12 FPLINE t6 FPLINE t15 t7 t17 DRDY t14 t1 t2 t3 t11 t13 t16 FPSHIFT t4 R[5:1] G[5:0] B[5:1] t5 1 2 639 640 t10 Note: DRDY is used to indicate the first pixel. Figure 7-43 TFT A.C. Timing Table 7-33 TFT A.C.
7: A.C. CHARACTERISTICS 7.4.
7: A.C. CHARACTERISTICS t8 t9 VRTC t12 HRTC t6 HRTC t15 t7 BLANK# t14 t1 t2 t3 t11 t13 t16 DACCLK t4 DACD[7:0] t5 1 2 639 640 t10 Figure 7-45 CRT A.C. Timing Table 7-34 CRT A.C.
7: A.C. CHARACTERISTICS 7.4.14 External RAMDAC Read / Write Timing Read t2 t1 AB[20:0] CS# M/R# DACRS[1:0] Valid RD# command (depends on CPU bus) t4 t3 DACRD# Write Valid WR# command (depends on CPU bus) t5 DACWR# t6 Figure 7-46 Generic Bus RAMDAC Read / Write Timing Table 7-35 Generic Bus RAMDAC Read / Write Timing Symbol Parameter Min. Typ.
8: REGISTERS 8 REGISTERS 8.1 Register Mapping The S1D13504 registers are all memory mapped. The system must provide the external address decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001.
8: REGISTERS 8.2 Register Descriptions Note: Unless specified otherwise, all register bits are reset to 0 during power up. Reserved bits should be written 0 when programming unless otherwise noted. 8.2.
8: REGISTERS 8.2.3 Panel/Monitor Configuration Registers Panel Type Register REG[02h] n/a n/a Panel Data Width Bit 1 Panel Data Width Bit 0 Panel Data Format Select Color/Mono Panel Select Dual/Single Panel Select RW TFT/Passive LCD Panel Select bits 5–4 Panel Data Width Bits [1:0] These bits select passive LCD/TFT panel data width size.
8: REGISTERS Horizontal Non-Display Period Register REG[05h] n/a n/a n/a Horizontal Non-Display Period Bit 4 Horizontal Non-Display Period Bit 3 Horizontal Non-Display Period Bit 2 Horizontal Non-Display Period Bit 1 RW Horizontal Non-Display Period Bit 0 bits 4–0 Horizontal Non-Display Period Bits [4:0] These bits specify the horizontal non-display period width in 8-pixel resolution. Horizontal non-display period width in number of pixels = ((ContentsOfThisRegister) + 1) × 8.
8: REGISTERS Vertical Display Height Register 0 REG[08h] RW Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Display Height Display Height Display Height Display Height Display Height Display Height Display Height Display Height Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Vertical Display Height Register 1 REG[09h] n/a n/a n/a n/a n/a n/a RW Vertical Vertical Display Height Display Height Bit 9 Bit 8 REG[08h] bits 7–0, REG[09h] bits 1–0 Vertical Display Height Bits [9:0] T
8: REGISTERS VRTC/FPFRAME Pulse Width Register REG[0Ch] VRTC Polarity Select FPFRAME Polarity Select n/a n/a n/a VRTC/ FPFRAME Pulse Width Bit 2 VRTC/ FPFRAME Pulse Width Bit 1 RW VRTC/ FPFRAME Pulse Width Bit 0 bit 7 VRTC Polarity Select For CRTs, this bit selects the polarity of the VRTC. When this bit = 1, the VRTC pulse is active high. When this bit = 0, the VRTC pulse is active low. bit 6 FPFRAME Polarity Select This bit selects the polarity of the FPFRAME for TFT and passive LCD.
8: REGISTERS 8.2.4 Display Configuration Registers Display Mode Register REG[0Dh] Simultaneous Simultaneous n/a Display Option Display Option Select Bit 1 Select Bit 0 RW Number Of Bits/Pixel Select Bit 2 Number Of Bits/Pixel Select Bit 1 Number Of Bits/Pixel Select Bit 0 CRT Enable LCD Enable bits 6–5 Simultaneous Display Option Select Bits [1:0] These bits are used to select one of four different simultaneous display mode options: Normal, Line Doubling, Interlace, or Even Scan Only.
8: REGISTERS bit 1 CRT Enable This bit enables the CRT control signals. Note: REG[02h] bit 1 must = 0 when in CRT only mode. bit 0 LCD Enable This bit enables the LCD control signals. Programming this bit from a 0 to a 1 starts the LCD power-on sequence. Programming this bit from a 1 to a 0 starts the LCD power-off sequence.
8: REGISTERS Screen 2 Display Start Address Register 0 REG[13h] Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 RW Start Address Bit 0 Screen 2 Display Start Address Register 1 REG[14h] Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 RW Start Address Bit 8 Start Address Bit 19 Start Address Bit 18 Start Addr
8: REGISTERS Pixel Panning Register REG[18h] RW Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel Screen 2 Pixel Screen 1 Pixel Screen 1 Pixel Screen 1 Pixel Screen 1 Pixel Panning Bit 3 Panning Bit 2 Panning Bit 1 Panning Bit 0 Panning Bit 3 Panning Bit 2 Panning Bit 1 Panning Bit 0 This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each screen can be independently panned to the left by programming its respective Pixel Panning Bits to a non-zero value.
8: REGISTERS 8.2.5 Clock Configuration Register Clock Configuration Register REG[19h] n/a bit 2 n/a n/a n/a n/a MCLK Divide Select PCLK Divide Select Bit 1 RW PCLK Divide Select Bit 0 MCLK Divide Select When this bit = 1 the memory clock (MCLK) frequency is half of the input clock frequency. When this bit = 0 the memory clock frequency is equal to the input clock frequency.
8: REGISTERS 8.2.6 Power Save Configuration Registers Power Save Configuration Register REG[1Ah] n/a n/a bit 3 n/a n/a LCD Power Disable RW Suspend Suspend Software Refresh Select Refresh Select Suspend Mode Bit 1 Bit 0 Enable LCD Power Disable When this bit = 1 the LCDPWR output is directly forced to the Off state. The LCDPWR “On/Off” state is configured by MD10 at the rising edge of RESET#. When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic.
8: REGISTERS 8.2.7 Miscellaneous Registers Miscellaneous Disable Register REG[1Bh] Host Interface n/a Disable n/a n/a n/a n/a n/a RW Half Frame Buffer Disable bit 7 Host Interface Disable This bit must be programmed to 0 to enable the Host Interface. This bit goes high on reset. When this bit is high, all memory and all registers except REG[1Ah] (read-only), REG[28h] through REG[2Fh], and REG[1Bh] are inaccessible. bit 0 Half Frame Buffer Disable This bit is used to disable the half frame buffer.
8: REGISTERS GPIO Configuration Register 0 REG[1Eh] GPIO7 Pin GPIO6 Pin GPIO5 Pin IO Config. IO Config. IO Config. GPIO4 Pin IO Config. GPIO3 Pin IO Config. GPIO2 Pin IO Config. GPIO1 Pin IO Config. RW GPIO0 Pin IO Config. bit 7 GPIO7 Pin IO Configuration When this bit = 1, GPIO7 is configured as an output. When this bit = 0 (default), GPIO7 is configured as an input.
8: REGISTERS GPIO Configuration Register 1 REG[1Fh] n/a n/a n/a n/a GPIO11 Pin IO Config. GPIO10 Pin IO Config. GPIO9 Pin IO Config. RW GPIO8 Pin IO Config. bit 3 GPIO11 Pin IO Configuration When this bit = 1, GPIO11 is configured as an output. When this bit = 0 (default), GPIO11 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO11, otherwise the VRTC pin is controlled automatically and this bit will have no effect on hardware.
8: REGISTERS GPIO Status / Control Register 0 REG[20h] GPIO7 Pin GPIO6 Pin GPIO5 Pin IO Status IO Status IO Status GPIO4 Pin IO Status GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status RW GPIO0 Pin IO Status bit 7 GPIO7 Pin IO Status When GPIO7 is configured as an output, a “1” in this bit drives GPIO7 to high and a “0” in this bit drives GPIO7 to low. When GPIO7 is configured as an input, a read from this bit returns the status of GPIO7.
8: REGISTERS GPIO Status / Control Register 1 REG[21h] GPO n/a n/a Control bit 7 n/a GPIO11 Pin IO Status GPIO10 Pin IO Status GPIO9 Pin IO Status RW GPIO8 Pin IO Status GPO Control This bit is used to control the state of the SUSPEND# pin when it is configured as GPO.
8: REGISTERS Performance Enhancement Register 0 REG[22h] EDO ReadWrite Delay RC Timing Value Bit 1 RC Timing Value Bit 0 RW RAS# to CAS# Delay RAS# Precharge Timing Bit 1 RAS# Precharge Timing Bit 0 n/a Reserved Note: Changing this register to non-zero value, or to a different non-zero value, should be done only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1).
8: REGISTERS REG[22h] Bit 4 0 1 Table 8-12 RAS#-to-CAS# Delay Timing Select NRCD RAS# - CAS# Delay (tRCD) 2 2 TM 1 1 TM bits 3–2 RAS# Precharge Timing (NRP) Bits [1:0] Minimum Memory Timing for RAS precharge These bits select the DRAM RAS# Precharge timing parameter, tRP. These bits specify the number (NRP) of MCLK periods (TM) used to create tRP - see the following formulae. Note, these formulae assume an MCLK duty cycle of 50 ± 5%. NRP = 1 = 1.5 =2 if (tRP/TM) < 1 if 1 ≤ (tRP/TM) < 1.
8: REGISTERS 8.2.8 Look-Up Table Registers The S1D13504 has three internal 16 position, 4-bit wide Look-Up Tables. The 4-bit value programmed into each table position determines the color weighting of display data; the output gray shade is derived from the Green Look-Up Table. These tables are bypassed in 15/16-bpp mode. These three 16 position Look-Up Tables can be arranged in many different configurations to accommodate all the gray shade / color display modes.
8: REGISTERS Look-Up Table Bank Select Register REG[27h] Red Bank n/a n/a Select Bit 1 Red Bank Select Bit 0 Blue Bank Select Bit 1 Blue Bank Select Bit 0 Green Bank Select Bit 1 RW Green Bank Select Bit 0 bits 5–4 Red Bank Select Bits [1:0] In 2-bpp mode, the 16 position Red LUT is arranged into four, 4 position “banks.” These two bits control which bank is currently selected. In 8-bpp mode, the 16 position Red LUT is arranged into two, 8 position “banks.
8: REGISTERS 8.2.9 External RAMDAC Control Registers Note: 1. In a Little-Endian system, the RAMDAC should be connected to the low byte of the CPU data bus and the following registers are accessed at the lower address given for each register (28h, 2Ah, 2Ch, and 2Eh). In a Big-Endian system, the RAMDAC should be connected to the high byte of the CPU data bus and the following registers are accessed at the higher address given for each register (29h, 2Bh, 2Dh, and 2Fh). 2.
9: DISPLAY BUFFER 9 DISPLAY BUFFER The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0] as shown in the following table.
9: DISPLAY BUFFER 9.1 Image Buffer The image buffer contains the formatted display data - see Section 10.1, “Display Mode Data Format” on page 88. The displayed image(s) may take up only a portion of the image buffer; the remaining area can be used for multiple images - possibly for animation or general storage. See Section 10, “Display Configuration” on page 88 for details on the relationship between the image buffer and the display. 9.
10: DISPLAY CONFIGURATION 10 DISPLAY CONFIGURATION 10.
10: DISPLAY CONFIGURATION 15-bpp: P0 P1 P2 P3 P4 P5 P6 P7 5-5-5 RGB bit 7 Byte 0 Byte 1 Byte 2 bit 0 G02 G01 G12 Byte 3 G00 B04 B03 B02 B01 B00 R04 R03 R02 R01 R00 G04 G11 G10 B14 B13 B12 B11 R14 R13 R12 R11 R10 G14 G13 G03 B10 TFT Pn = (Rn4-0, Gn4-0, Bn4-0) Passive Pn = (Rn4-1, Gn4-1, Bn4-1) Panel Display Display Buffer Host Address 16-bpp: 5-6-5 RGB bit 7 P0 P1 P2 P3 P4 P5 P6 P7 bit 0 Byte 0 G02 G01 G00 B04 B03 B02 B01 B00 Byte 1 R04 R03 R02 R01 R00 G05 G04 G03 Byte
10: DISPLAY CONFIGURATION 10.2 Image Manipulation The figure below shows how screen 1 and screen 2 images stored in the image buffer are positioned on the display. The screen 1 and screen 2 images can be parts of a larger virtual image or images. • (REG[17h], REG[16h]) defines the width of the virtual image(s). • (REG[12h], REG[11h], REG[10h]) defines the starting word of the screen 1, (REG[15h], REG[14h], REG[13h]) defines the starting word of the screen 2.
11: CLOCKING 11 CLOCKING 11.1 Maximum MCLK : PCLK Ratios Table 11-1 Maximum PCLK Frequency with EDO-DRAM Maximum PCLK Allowed Display Type NRC 1 bpp 2 bpp 4 bpp 8 bpp • Single Panel. • CRT. • Dual Monochrome/Color Panel with Half Frame Buffer Disabled. • Simultaneous CRT + Single Panel. • Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. • Dual Monochrome Panel with Half Frame Buffer Enabled. • Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable.
11: CLOCKING 11.
11: CLOCKING Note: 1. Must set NRC = 4MCLK. See REG[22h], “Performance Enhancement Register 0”. 2. 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types. 3. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled. 4. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too high for a panel, MCLK should be reduced or PCLK should be divided down. 5. Half Frame Buffer disabled by REG[1Bh] bit 0.
12: LOOK-UP TABLE ARCHITECTURE 12 LOOK-UP TABLE ARCHITECTURE Table 12-1 Look-Up Table Configurations 4-Bit Wide Look-Up Table RED GREEN 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 1 bank of 2 entries 1 bank of 2 entries 4 banks of 4 entries 4 banks of 4 entries 1 bank of 16 entries 1 bank of 16 entries 2 banks of 8 entries 2 banks of 8 entries Display Mode Black & White 4-level gray 16-level gray 2 color 4 color 16 color 256 color BLUE 1 bank of 2 entries 4 banks of 4 entries 1 bank of
12: LOOK-UP TABLE ARCHITECTURE 4 Bit-Per-Pixel Mode Green Look-Up Table 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F Entry Select Logic 4-bit display data output 4-bit pixel data Figure 12-3 4 Bit-Per-Pixel – 16-Level Gray-Shade Mode Look-Up Table Architecture 12.
12: LOOK-UP TABLE ARCHITECTURE 2 Bit-Per-Pixel Color Mode Red Look-Up Table Bank 0 0 1 2 3 00 Bank 1 4 5 6 7 Bank 2 8 9 A B 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Red data output Bank 3 C D E F 2-bit pixel data 11 Bank Select bits [1:0] REG[27h] bits [5:4] Green Look-Up Table Bank 0 0 1 2 3 00 Bank 1 4 5 6 7 Bank 2 8 9 A B 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Green data output Bank 3 C D E F 11 Bank Select bits [1:0
12: LOOK-UP TABLE ARCHITECTURE 4 Bit-Per-Pixel Color Mode Red Look-Up Table 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F Entry Select Logic 4-bit Red data output 4-bit pixel data Green Look-Up Table 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F Entry Select Logic 4-bit Green data output Blue Look-Up Table 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11
12: LOOK-UP TABLE ARCHITECTURE 8 Bit-Per-Pixel Color Mode 256 Color Data Format: 7 6 5 4 3 Red Look-Up Table 2 1 0 Bank 0 R2 R1 R0 G2 G1 G0 B1 B0 0 1 2 3 4 5 6 7 0 Selected Bank 000 001 010 Entry 011 100 Select 101 Logic 110 111 Bank Select Logic Bank 1 8 9 A B C D E F 4-bit Red data output 1 Bank Select bit REG[27h] bit 4 3-bit pixel data Green Look-Up Table Bank 0 0 1 2 3 4 5 6 7 0 Selected Bank 000 001 010 Entry 011 100 Select 101 Logic 110 111 Bank Select Logic Bank 1 8 9 A B C D E
13: POWER SAVE MODES 13 POWER SAVE MODES Two Power Save Modes have been incorporated into the S1D13504 to accommodate the important need for power reduction in the hand-held devices market. These modes are hardware suspend and software suspend. 13.1 Hardware Suspend • Register read/write disallowed. • Memory read/write disallowed. • LCD outputs are forced low (see Note 1 of Section 13.4, “Pin States in Power Save Modes” on page 100). • LCDPWR forced to Off state. • CRT outputs are disabled.
13: POWER SAVE MODES 13.3 Power Save Mode Function Summary Function Display Active? Register Access Possible? Memory Access Possible? Host Bus Interface Running? Memory Interface Running? Table 13-1 Power Save Mode Function Summary Power Save Mode (PSM) Normal (Active) Software Suspend Yes No Yes Yes (1) Yes No Yes Yes Yes No (2) Hardware Suspend No No No No No (2) Note: 1. Except for RAMDAC registers. 2. Yes if CBR suspend mode refresh is selected. 13.
14: MECHANICAL DATA 14 MECHANICAL DATA 14.1 QFP15-128pin (S1D13504F00A) Unit: mm QFP15-128pin 16±0.4 14±0.1 96 65 16±0.4 64 14±0.1 97 INDEX 128 33 32 1.4±0.1 0.4 +0.1 0.16 –0.05 +0.05 0.125–0.025 0° 10° 0.5±0.2 0.1 1.
14: MECHANICAL DATA 14.2 TQFP15-128pin (S1D13504F01A) Unit: mm TQFP15-128pin 16±0.4 14±0.1 96 65 16±0.4 64 14±0.1 97 INDEX 128 33 1 32 +0.05 1±0.1 0.16–0.03 +0.05 0.125 –0.025 0° 10° 0.5±0.2 0.1 1.2max 0.
14: MECHANICAL DATA 14.3 QFP20-144pin (S1D13504F02A) Unit: mm QFP20-144pin 22±0.4 20±0.1 108 73 22±0.4 72 20±0.1 109 INDEX 144 37 1 +0.1 36 1.4±0.1 0.2 –0.05 +0.05 0.125–0.025 0° 10° 0.5±0.2 0.1 1.7max 0.
14: MECHANICAL DATA THIS PAGE IS BLANK.
ll er o s r e t ri n o e C S D 4 C 0 5 L 3 hic 1 D p S1 Gra x ri t a D M t o es t No g in es m pl m ra am g o x Pr nd E a
CONTENTS Contents Table of Contents 1 INTRODUCTION .........................................................................................................................2-1 2 PROGRAMMING THE S1D13504 REGISTERS ...............................................................................2-2 2.1 Registers Requiring Special Consideration ...................................................................................2-2 2.1.1 REG[01] bit 0 - Memory Type ................................................
CONTENTS 8.2 API for 13504HAL ....................................................................................................................... 2-27 8.2.1 Initialization.................................................................................................................... 2-27 8.2.2 Screen Manipulation...................................................................................................... 2-29 8.2.3 Color Manipulation.........................................................
CONTENTS List of Figures Figure 4-1 Figure 4-2 Viewport Inside a Virtual Display........................................................................................2-13 320x240 Single Panel For Split Screen..............................................................................
1: INTRODUCTION 1 INTRODUCTION This guide demonstrates how to program the S1D13504 Color Graphics LCD/CRT Controller. The first half of this guide presents the basic concepts of the LCD controller and provides methods to directly program the registers. The second half of this guide introduces the Hardware Abstraction Layer (HAL), designed to make programming the S1D13504 as easy as possible.
2: PROGRAMMING THE S1D13504 REGISTERS 2 PROGRAMMING THE S1D13504 REGISTERS This section describes how to program the S1D13504 registers that require special consideration. It also provides the correct sequence for initializing the S1D13504 and disabling the half frame buffer. For further information on the any of the registers described below, refer to the “S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx. 2.1 Registers Requiring Special Consideration 2.1.
2: PROGRAMMING THE S1D13504 REGISTERS 2.2 Register Initialization 2.2.1 Initialization Sequence To initialize the S1D13504 after POWER-ON or a HARDWARE RESET, do the following: 1. Enable the host interface (REG[1Bh] bit 7 = 0). 2. Disable the display FIFO (REG[23h] bit 7 = 1) after stopping FIFO accesses to the DRAM. 3. Set memory type (REG[01h] bit 0). 4. Set performance register (REG[22h]). 5. Set dual/single panel (REG[02h] bit 1). 6. Program all other registers as required. 7.
2: PROGRAMMING THE S1D13504 REGISTERS Table 2-1 Initializing the S1D13504 Registers Operation Description REG[1Bh] = 0x00 Enable Host Interface REG[23h] = 0x80 Disable the Display FIFO REG[01h] = 0x30 Set Memory Type REG[22h] = 0x24 Set Performance Register REG[02h] = 0x26 Set Dual/Single Panel REG[03h] = 0x00 MOD Rate REG[04h] = 0x4F Horizontal Display Width REG[05h] = 0x1F Horizontal Non-Display Period REG[06h] = 0x00 HSYNC Start Position REG[07h] = 0x00 HSYNC Pulse Width REG[08h] = 0xEF Vertical Display
2: PROGRAMMING THE S1D13504 REGISTERS 2.3 Disabling the Half Frame Buffer Sequence The Half Frame Buffer can be ENABLED asynchronously. To DISABLE the Half Frame Buffer, do the following: 1. Disable the display FIFO REG[23] bit 7 = 1. 2. Set the horizontal resolution to 0 (REG[04] = 0). Setting the horizontal resolution = 0 will shut-off any Half Frame Buffer DRAM accesses within 1024 PCLK's or less (1024 PCLK’s is the worst case). 3. Wait for VNDP 1→0→1 transitions (REG[0A] bit 7).
3: DISPLAY BUFFER 3 DISPLAY BUFFER This section discusses how the S1D13504 stores pixels in the display buffer and where the display buffer is located. 3.1 Display Buffer Location The S1D13504 requires either a 512K byte or a 2M byte block of memory to be decoded by the system. System logic will determine the location of this memory block; the S5U13504P00C evaluation board decodes the display buffer at the 12M byte location of system memory. 3.2 Display Buffer Organization 3.2.
3: DISPLAY BUFFER 3.2.4 Memory Organization for Eight Bit-per-pixel (256 Colors) One pixel is stored in one byte of display buffer as shown below: Bit 7 Red Bit 2 Table 3-4 Pixel Storage for 8 bpp (256 Colors) in One Byte of Display Buffer Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Red Bit 1 Red Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 1 Bit 0 Blue Bit 0 As shown above, the 256 color pixel is divided into three parts: three bits for red, three bits for green, and two bits for blue.
3: DISPLAY BUFFER 3.3 Look-Up Table (LUT) This section provides a description of the LUT registers, followed by a description of the color and gray shade LUTs and a discussion of the banks available in the 2 and 8 bit-per-pixel (bpp) modes. The S1D13504 LUT is only used for the panel interface. The optional RAMDAC is used to determine the colors for the CRT. See Section 6, “CRT Considerations” on page 23. 3.3.
3: DISPLAY BUFFER In 8 bpp mode, the 16 entry LUTs are logically split into 2 groups of 8 entries for both Red and Green as follows: Bank 0 = Indexes 00–07h Bank 1 = Indexes 08–0Fh For Blue the 16 entry LUT is logically split into 4 groups of 4 entries as follows: Bank 0 = Indexes 00–03h Bank 1 = Indexes 04–07h Bank 2 = Indexes 08–0Bh Bank 3 = Indexes 0C–0Fh The bank select bits only affect data output.
3: DISPLAY BUFFER The following table shows the recommended values for obtaining a Black-and-White mode while on a color panel.
3: DISPLAY BUFFER This recommended palette assumes that you are using only bank 0 of the three color components.
3: DISPLAY BUFFER 8 bpp Gray Shade When the S1D13504 is configured for 8 bpp gray shade mode, bits [7:5] are ignored, bits [4:2] represent the green LUT index, and bits [1:0] are ignored. Only 3 bits of the 8 that actually represent any shade value, therefore the maximum gray shade combination is 8 shades.
4: ADVANCED TECHNIQUES 4 ADVANCED TECHNIQUES This section presents information on the following: • virtual display • panning and scrolling • split screen display 4.1 Virtual Display A virtual display is when the image to be displayed is larger than the physical display device in either the horizontal dimension, the vertical dimension, or both. To view the image, the physical display is used as a window or viewport into the display buffer, allowing the user to see a portion of the entire image.
4: ADVANCED TECHNIQUES 4.1.2 Examples Example 2 Determine the offset value required for 800 pixels at a color depth of 8 bpp. A color depth of 8 bpp means each pixel requires one byte therefore each word contains two pixels. offset = pixels_per_line / pixels_per_word = 800 / 2 = 400 = 0x190 words Register [17h] would be set to 0x01 and register [16h] would be set to 0x90. Example 3 Program the Memory Address Offset Registers to support a 16 color (4 bpp) 640x480 virtual display on a 320x240 LCD panel.
4: ADVANCED TECHNIQUES 4.2 Panning and Scrolling Panning and scrolling are typically used to navigate within an image which is too large to be shown completely on the display device. Although the image is stored entirely in display buffer, only a portion is actually visible at any given time. Panning and scrolling refers to the direction the viewport appears to move. Panning describes the action where the viewport moves horizontally.
4: ADVANCED TECHNIQUES 4.2.
4: ADVANCED TECHNIQUES 4.2.2 Examples For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x200 viewport. Refer to Section 2.2, “Register Initialization” on page 3 and Section 4.1, “Virtual Display” on page 13 for assistance with these settings. Example 4 Panning - Right and Left To pan to the right, increment the pixel pan value.
4: ADVANCED TECHNIQUES 4.3 Split Screen Occasionally the need arises to display two distinct images on the display. For example, we may want to write a game where the main play area will be rapidly updated and we want an unchanging status display at the bottom of the screen. The Split Screen feature of the S1D13504 allows a programmer to set up a display for such an application.
4: ADVANCED TECHNIQUES Screen 1 memory is always the first memory displayed at the top of the screen followed by screen 2 memory. However, the start address for the screen 2 image may in fact be lower in memory than that of screen 1 (i.e. screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into display buffer). While not particularly useful, it is possible to set screen 1 and screen 2 to the same address. 4.3.
5: LCD POWER SEQUENCING AND POWER SAVE MODES 5 LCD POWER SEQUENCING AND POWER SAVE MODES 5.1 Introduction to LCD Power Sequencing LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD signals. Power sequencing is required to prevent long term damage to the panel and to avoid unsightly “lines” on power down and start-up. LCD Power Sequencing is performed on the S1D13504 through a software procedure even when using hardware power save modes.
5: LCD POWER SEQUENCING AND POWER SAVE MODES 5.4 Suspend Sequencing Care must be taken when enabling Suspend Mode with respect to the external Power Supply used to provide the LCD Drive voltage. The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage. Controlling the LCD Drive Power Supply can be done using the S1D13504 LCDPWR# output signal or by 'other' means. The following example assumes that the LCDPWR# pin is being used. 5.4.
5: LCD POWER SEQUENCING AND POWER SAVE MODES 5.5 LCD Enable/Disable Sequencing (REG[0D] bit 0) In an LCD only product, the LCD Enable bit should only be disabled automatically by using a Power Save Mode. In a product having both a CRT and LCD, this bit will need to be controlled manually - examples for both situations are given below.
6: CRT CONSIDERATIONS 6 CRT CONSIDERATIONS 6.1 Introduction The CRT timing is based on both the “VESA Monitor Timing Standards Version 1.0” and “Clocking” (Chapter 11) in the “S1D13504 Hardware Functional Specification”. The following sections describe CRT considerations. 6.1.1 CRT Only For CRT only, the Dual/Single Panel Select bit of Panel Type Register (REG[02h]) must first be set to single passive LCD panel. The monitor configuration registers then need to be set to follow the VESA timing standard.
6: CRT CONSIDERATIONS 6.1.2 Simultaneous Display For Simultaneous Display, only 4/8-bit single passive LCD panels and 9-bit active matrix TFT panels can be used. Simultaneous Display requires that the panel timing be taken from the CRT timing registers and thereby limits the number of useful modes supported. The configuration of both CRT and panel must not violate the limitations as described in “Clocking” (Chapter 11) of the “S1D13504 Hardware Functional Specification”.
6: CRT CONSIDERATIONS Address 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F R 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F Register REG[04h] REG[05h] REG[06h] REG[07h] REG[08h] REG[09h] REG[0Ah] REG[0Bh] REG[0C
7: IDENTIFYING THE S1D13504 7 IDENTIFYING THE S1D13504 Unlike previous generations of S1D1350x products, the S1D13504 can be identified at any time after power on / reset. The S1D13504 and future S1D1350x products can be identified by reading REG[00h]. The value of this register for the S1D13504 is 04h.
8: HARDWARE ABSTRACTION LAYER (HAL) 8 HARDWARE ABSTRACTION LAYER (HAL) 8.1 Introduction The HAL is a processor independent programming library provided by Seiko Epson. HAL provides an easy method to program and configure the S1D13504. HAL allows easy porting from one S1D1350x product to another and between system architectures. HAL is included in the utilities provided with the S1D13504 evaluation system. 8.2 API for 13504HAL The following is a description of the HAL library.
8: HARDWARE ABSTRACTION LAYER (HAL) int seInitHal(void) Description: Initializes HAL library variables. Must be called once when application starts (see note below). Parameter: None Return Value: ERR_OK - operation completed with no problems. Note: For Intel platforms, seRegisterDevice() automatically calls seInitHal() once. Consecutive calls to seRegisterDevice() will not call seInitHal() again.
8: HARDWARE ABSTRACTION LAYER (HAL) 8.2.2 Screen Manipulation int seDisplayEnable(int device, BYTE NewState) Description: Performs the necessary power sequencing to enable or disable the display. Parameter: device NewState - registered device ID - use the predefined definitions ENABLE and DISABLE. Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_FAILED - unable to complete operation because registers have not been initialized.
8: HARDWARE ABSTRACTION LAYER (HAL) int seGetScreenSize(int device, int *width, int *height) Description: Determines the width and height of the active display device (LCD or CRT). Parameter: device width height - registered device ID - width of display in pixels - height of display in pixels Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
8: HARDWARE ABSTRACTION LAYER (HAL) int seSplitInit(int device, DWORD Scrn1Addr, DWORD Scrn2Addr) Description: Sets the relevant registers for split screen. Parameter: device Scrn1Addr Scrn2Addr - registered device ID - starting address of top image (addr = 0 refers to beginning of the display buffer) - starting address of bottom image (addr = 0 refers to beginning of the display buffer) Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
8: HARDWARE ABSTRACTION LAYER (HAL) int seVirtMove(int device, BYTE WhichScreen, int x, int y) Description: Pans or scrolls the virtual display. Parameter: device WhichScreen x y - registered device ID - Use one of the following definitions: SCREEN1 or SCREEN2. SCREEN1 is the top screen. - new starting X position in pixels - new starting Y position in pixels Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
8: HARDWARE ABSTRACTION LAYER (HAL) 8.2.3 Color Manipulation int seGetDac(int device, BYTE *pDac) Description: Reads the entire DAC into an array. Parameter: device pDac - registered device ID - pointer to an array of BYTE dac[256][3] dac[x][0] == RED component dac[x][1] == GREEN component dac[x][2] == BLUE component Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
8: HARDWARE ABSTRACTION LAYER (HAL) int seSetDac(int device, BYTE *pDac) Description: Writes the entire DAC from an array into the DAC registers. Parameter: device pDac - registered device ID - pointer to an array of BYTE dac[256][3] dac[x][0] == RED component dac[x][1] == GREEN component dac[x][2] == BLUE component Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
8: HARDWARE ABSTRACTION LAYER (HAL) int seGet15BppInfo(int device, unsigned *RedMask, unsigned *GreenMask, unsigned *BlueMask) Description: Determines the bit fields for the red, green, and blue components of a 15 bpp stored in a WORD. Parameter: device RedMask GreenMask BlueMask - registered device ID - all bits set to 1 are used by the red component. - all bits set to 1 are used by the green component. - all bits set to 1 are used by the blue component.
8: HARDWARE ABSTRACTION LAYER (HAL) int seFillRect(int device, int x1, int y1, int x2, int y2, DWORD color) Description: Draws a solid rectangle on the display. Parameter: device (x1, y1) (x2, y2) color - registered device ID - top left corner of rectangle - bottom right corner of rectangle (see note below) - color of rectangle For 1, 2, 4, and 8 bpp, color refers to the pixel value which points to the respective LUT/DAC entry.
8: HARDWARE ABSTRACTION LAYER (HAL) 8.2.5 Register Manipulation int seGetReg(int device, int index, BYTE *pVal) Description: Reads a register value. Parameter: device index pVal - registered device ID - register index - returns value of the register Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. int seSetReg(int device, int index, BYTE val) Description: Writes a register value.
9: SAMPLE CODE 9 SAMPLE CODE 9.1 Introduction The following code samples demonstrate two approaches to initializing the S1D13504 color graphics controller with/without using the 13504HAL API. These code samples are for example purposes only. 9.1.1 Sample Code Using 13504HAL API /* **------------------------------------------------------------------------** ** Sample Code using 1354HAL API ** ** Copyright (c) Seiko Epson Corp. 1998. All rights reserved.
9: SAMPLE CODE 9.1.2 Sample Code Without Using 13504HAL API /* **=========================================================================== ** INIT1354.C - sample code demonstrating the initialization of the S1D13504. ** Beta release 2.0 98-10-22 ** ** The code in this example will perform initialization to the following ** specification: ** ** - 320 x 240 single 8-bit color passive panel. ** - 75 Hz frame rate. ** - 8 BPP (256 colors). ** - 33 MHz input clock. ** - 2 MB of 60 ns FPM memory.
9: SAMPLE CODE ** Register 1B: Miscellaneous Disable - host interface enabled, half frame ** buffer enabled.
9: SAMPLE CODE */ *(pRegs + 0x0A) = 0x01; /* 0000 0001 */ /* ** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only. */ *(pRegs + 0x0B) = 0x00; /* 0000 0000 */ /* ** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only. */ *(pRegs + 0x0C) = 0x00; /* 0000 0000 */ /* ** Registers E-F: Screen 1 Line Compare - unless setting up for ** split screen operation use 0x3FF.
9: SAMPLE CODE ** In 8BPP mode only the first 8 red, first 8 green ** and first 4 blue values are used. ** ** Setup the pointer to the LUT data and reset the LUT index register. ** Then, loop writing each of the RGB LUT data elements. */ pLUT = LUT8; *(pRegs + 0x24) = 0; for (idx = 0; idx < 8; idx++) { for (rgb = 0; rgb < 3; rgb++) { *(pRegs + 0x26) = *pLUT; pLUT++; } } /* ** Registers 28-2E: RAMDAC - not used in this example. Programmed very ** similarly to the LUT but all 256 entries are used.
APPENDIX: SUPPORTED PANEL VALUES APPENDIX SUPPORTED PANEL VALUES The following tables show related register data for different panels. All the examples are based on 8 bpp, 40MHz pixel clock and 2M bytes of 60ns EDO-DRAM.
APPENDIX: SUPPORTED PANEL VALUES THIS PAGE IS BLANK.
ll er o s r e t ri n o e C S D 4 C 0 5 L 13 hic D rap 1 S G x ri t o D t a M s Ut ie ilit
CONTENTS Contents Table of Contents 1 13504CFG.EXE CONFIGURATION PROGRAM ............................................................................3-1 1.1 1.2 1.3 1.4 1.5 Program Requirements .................................................................................................................3-1 Installation .....................................................................................................................................3-1 Usage ...........................................
CONTENTS 7 13504PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY ...............................................3-26 7.1 7.2 7.3 7.4 7.5 3-ii S1D13504 Supported Evaluation Platforms................................................................................ 3-26 Installation ................................................................................................................................... 3-26 Usage..........................................................................................
CONTENTS List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 1-7 Figure 1-8 Figure 1-9 Figure 1-10 Figure 1-11 Figure 1-12 Figure 1-13 Figure 1-14 Figure 1-15 Figure 1-16 Figure 1-17 Figure 1-18 Figure 1-19 Figure 1-20 Figure 1-21 Figure 1-22 Figure 1-23 Figure 1-24 13504CFG Menu Bar ...........................................................................................................3-3 13504CFG Open File ..........................................................
1: 13504CFG.EXE CONFIGURATION PROGRAM 1 13504CFG.EXE CONFIGURATION PROGRAM 13504CFG gives a software/hardware developer an easy way to modify panel types, modes, etc. for the S1D13504 utilities without recompiling. Once the correct operating environment has been determined, the software/hardware developer can modify the source code manually for a permanent change.
1: 13504CFG.EXE CONFIGURATION PROGRAM 1.3 Usage At the DOS Prompt, type 13504cfg. 13504cfg [filename.exe script.ini] [/?] Where: filename.exe is the 13504 utility to be modified script.ini is the list of HAL configuration changes (see Section 1.4, “Script Mode” ) /? displays the usage screen no argument runs 13504CFG in the interactive mode 1.4 Script Mode In script mode, a file provides 13504CFG with all the information necessary to reconfigure the selected 13504 utility.
1: 13504CFG.EXE CONFIGURATION PROGRAM 1.5 Interactive Mode 1.5.1 13504CFG Menu Bar Menu Bar Figure 1-1 13504CFG Menu Bar 13504CFG has four main menus: Files, View, Device, and Help. Menu contents can be viewed by using either the mouse or the keyboard. Viewing 13504CFG Menu Contents Mouse Move the on-screen arrow with the mouse and point at the desired menu. Click the left mouse button and the contents of the menu will be displayed. Keyboard Press: to select the Files menu.
1: 13504CFG.EXE CONFIGURATION PROGRAM 1.5.2 Files Menu Figure 1-3 13504CFG Files Menu The Files menu contains these functions: • Open - reads the HAL configuration for a given utility. Note:A utility must be opened before any other menu command can be executed. • Save - saves the current changes to the opened file. • Save As - saves a file to a different name and/or different location. • Save All - saves modifications to all 13504 files that are in the same directory as the file being saved.
1: 13504CFG.EXE CONFIGURATION PROGRAM 1.5.3 View Menu Figure 1-4 13504CFG View Menu The View menu displays the Current Configuration and the Advanced Configuration of an opened utility. In the Current or Advanced Configuration window, the configuration of an opened file can be viewed only, not edited. Configuration parameters must be edited in the Panel, CRT, Advanced Memory, Power Management, Look-Up Table, and Setup sub-menus in the Device menu.
1: 13504CFG.EXE CONFIGURATION PROGRAM 1.5.
1: 13504CFG.EXE CONFIGURATION PROGRAM Panel Panel Setup When Panel is selected from the Device menu, the Panel Setup dialog box is displayed. To select a panel assignment, highlight it (in the example window below, “STN 4 Bit Mono Single 320 x 240” is highlighted) and click OK. If the highlighted panel assignment needs changes, click Edit and see the next section “Edit Panel Setup.
1: 13504CFG.EXE CONFIGURATION PROGRAM CRT CRT Setup When CRT is selected from the Device menu, the CRT Setup window is displayed. To select a CRT assignment, highlight it (in the example window below, “CRT 640 x 400 @ 85Hz, CLKI = 33.333 MHz” is highlighted) and click OK. If the highlighted CRT assignment needs changes, click Edit and see the next section “Edit CRT Setup.” Whenever a CRT assignment is edited or selected in the CRT Setup dialog box, the setup is copied to Current Configuration.
1: 13504CFG.EXE CONFIGURATION PROGRAM Advanced Memory Memory Setup When Advanced Memory is selected from the Device menu, the Memory Setup dialog box is displayed. To select a memory assignment, highlight it ( in the example window below, “Memory Type 0” is highlighted) and click OK. If the highlighted memory assignment needs changes, click Edit and see the next section “Edit Memory Setup.
1: 13504CFG.EXE CONFIGURATION PROGRAM Power Management Power Setup When Power Management is selected from the Device menu, the Power Setup dialog box is displayed. To select a power assignment, highlight it (in the example window below, “Power Type 0” is highlighted) and click OK. If the highlighted power assignment needs changes, click Edit and see the next section “Edit Power Setup.
1: 13504CFG.EXE CONFIGURATION PROGRAM Lookup Table (LUT) LUT Setup When Lookup Table is selected from the Device menu, the LUT Setup dialog box is displayed. To select a LUT assignment, highlight it (in the example window below, “LUT Internal 4 Color” is highlighted) and click OK. If the highlighted LUT assignment needs changes, click Edit and see the next section “Edit LUT Setup.” Whenever a LUT assignment is edited or selected in the LUT Setup dialog box, the setup is copied to Current Configuration.
1: 13504CFG.EXE CONFIGURATION PROGRAM Setup When Setup is selected from the Device menu, the Setup dialog box is displayed. To select either Register Location, Memory Location, or Memory Size, highlight it (in the example window below, “Register Location: 00C00000 (hex)” is highlighted) and click OK. If the highlighted Setup assignment needs changes, click Edit and see the next section “Setup Parameter Edit.” In addition to OK, Cancel, and Edit commands, a Help command is listed in the Setup windows.
1: 13504CFG.EXE CONFIGURATION PROGRAM 1.6 Comments It is assumed that the 13504CFG user is familiar with S1D13504 hardware and software. Refer to the “S1D13504 Hardware Functional Specification,” document number S19A-A-002-xx, and the “S1D13504 Programming Notes and Examples,” document number S19A-G-002-xx for information. In addition, the 13504CFG user must know the hardware setup for the panel and CRT, and the setup for the given hardware platform (such as memory addresses and memory speed). 1.
2: 13504SHOW DEMONSTRATION PROGRAM 2 13504SHOW DEMONSTRATION PROGRAM 13504SHOW demonstrates S1D13504 display capabilities by drawing a pattern image at different pixel depths (i.e. 16 bits-per-pixel, 2 bits-per-pixel, etc.) on the display. The 13504SHOW display utility must be configured and/or compiled to work with your hardware platform. Consult documentation for the program 13504CFG.EXE which can be used to configure 13504SHOW.
2: 13504SHOW DEMONSTRATION PROGRAM 2.4 Comments • 13504SHOW cannot show a greater color depth than the display allows. • The PC must not have more than 12M bytes of system memory when used with the S5U13504P00C board. • Follow simultaneous display guidelines for correct simultaneous display operation. • To determine if the CRT will operate correctly when using a dual panel, refer to the “Maximum Frame Rates” table in the “S1D13504 Hardware Functional Specification,” document number S19A-A-002-xx.
3: 13504SPLT DISPLAY UTILITY 3 13504SPLT DISPLAY UTILITY 13504SPLT demonstrates S1D13504 split screen capability by showing two different areas of display memory on the screen simultaneously. Screen 1 shows horizontal bars, and Screen 2 shows vertical bars. Screen 1 memory is located at the start of the display buffer. Screen 2 memory is located immediately after Screen 1 in the display buffer.
3: 13504SPLT DISPLAY UTILITY 3.4 13504SPLT Example 1. Type “13504splt /a” to automatically move the split screen. 2. Press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel. 3. Repeat step 2 for the remaining bits-per-pixel colour depths: 1, 2, 4, 8, 15, and 16. 4. Press to exit the program. 3.5 Comments • The PC must not have more than 12M bytes of system memory when used with the S5U13504P00C board.
4: 13504VIRT DISPLAY UTILITY 4 13504VIRT DISPLAY UTILITY 13504VIRT shows the virtual display capability of the S1D13504. A virtual display is where the image to be displayed is larger than the physical display device (CRT or LCD) and can be viewed by panning and scrolling. 13504VIRT allows the display device to be used as a “window” to view the entire image. The 13504VIRT display utility must be configured and/or compiled to work with your hardware platform. Consult documentation for the program 13504CFG.
4: 13504VIRT DISPLAY UTILITY The following keyboard commands are for navigation within the program.
5: 13504PLAY DIAGNOSTIC UTILITY 5 13504PLAY DIAGNOSTIC UTILITY 13504PLAY allows the user to read/write to all S1D13504 registers/look up tables and display memory. 13504PLAY is similar to the DOS DEBUG program; commands are received from the standard input device, and output is sent to the standard output device (console for Intel, terminal for embedded platforms). This utility requires the target platform to support standard IO (stdio).
5: 13504PLAY DIAGNOSTIC UTILITY The following commands are valid within the 13504PLAY program. X index [data] - Reads/writes the registers. - Writes data to the register specified by the index when “data” is specified; otherwise the register is read. XA - Reads all registers. D index [data1 data2 data3] - Reads/writes DAC values. - Writes data to the DAC index when “data” is specified; otherwise the register is read. - Data consists of 3 bytes: 1 red, 1 green, 1 blue. DA - Reads all DAC values.
5: 13504PLAY DIAGNOSTIC UTILITY 5.4 13504PLAY Example 1. Type "13504PLAY" to start the program. 2. Type "?" for help. 3. Type "i" to initialize the registers. 4. Type "xa" to display the contents of the registers. 5. Type "x 5" to read register 5. 6. Type "x 3 10" to write 10 hex to register 3. 7. Type "f 0 ffff aa" to fill the first FFFF hex bytes of display memory with AA hex. 8. Type "f 0 1fffff aa" to fill 2M bytes of display memory. 9. Type "r 0 ff" to read the first 100 hex bytes of display memory.
5: 13504PLAY DIAGNOSTIC UTILITY 5.7 Program Messages ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register S1D13504F00A device. A 13504 device was not found at the configured addresses. Check the configuration address using the 13504CFG configuration program.
6: 13504BMP DEMONSTRATION PROGRAM 6 13504BMP DEMONSTRATION PROGRAM 13504BMP demonstrates S1D13504 display capabilities by rendering bitmap images on the display. The 13504BMP display utility is designed to operate in a personal computer (PC) DOS environment and must be configured to work with your display hardware. Consult documentation for the program 13504CFG.EXE which can be used to configure 13504BMP. 13504BMP is not supported on non-PC platforms. 6.1 Installation Copy the file 13504BMP.
6: 13504BMP DEMONSTRATION PROGRAM 6.4 Program Messages ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register S1D13504F00A device. A 13504 device was not found at the configured addresses. Check the configuration address using the 13504CFG configuration program. ERROR: Did not detect S1D13504. The HAL was unable to read the revision code register on the S1D13504.
7: 13504PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY 7 13504PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY The 13504PWR Software Suspend Power Sequencing Utility enables or disables the S1D13504 software suspend mode and LCD. Refer to the section titled “LCD Power Sequencing and Power Save Modes” in the “S1D13504 Programming Notes and Examples,” document number S19A-G-002-xx. Also, refer to the “S1D13504 Hardware Functional Specification,” document number S19A-A-002-xx for further information.
7: 13504PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY Examples: To enable software suspend mode, use the following arguments: /software /enable To disable software suspend mode, use the following arguments: /software /disable To enable the LCD, use the following arguments: /lcd /enable To disable the LCD, use the following arguments: /lcd /disable 7.4 Comments • • • • The /i argument is to be used when the registers have not been previously initialized.
7: 13504PWR SOFTWARE SUSPEND POWER SEQUENCING UTILITY THIS PAGE IS BLANK.
ll er o s r e t ri n o e C S D 4 C 0 5 L 3 hic 1 D p S1 Gra x ri t a D M t o C 0 P0 rd 4 a 0 35 s n Boal 1 U u o u S5 A B uati an IS val ’s M E ser U
CONTENTS Contents Table of Contents 1 INTRODUCTION .........................................................................................................................4-1 1.1 Features ........................................................................................................................................4-1 2 INSTALLATION AND CONFIGURATION ...........................................................................................4-2 3 LCD/RAMDAC INTERFACE PIN MAPPING...................
CONTENTS List of Figures Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 S5U13504P00C Schematic Diagram (1 of 6) .................................................................... 4-11 S5U13504P00C Schematic Diagram (2 of 6) .................................................................... 4-12 S5U13504P00C Schematic Diagram (3 of 6) .................................................................... 4-13 S5U13504P00C Schematic Diagram (4 of 6) .....................................
1: INTRODUCTION 1 INTRODUCTION This manual describes the setup and operation of the S5U13504P00C Rev. 1.0 Evaluation Board when used with the S1D13504 Color Graphics LCD/CRT Controller in the ISA bus environment. For more information regarding the S1D13504, refer to the “S1D13504 Hardware Functional Specification,” document number S19A-A-002-xx. 1.1 Features • • • • • • • • • • • • 128 pin QFP15 package. SMT technology for all appropriate devices. 4/8-bit monochrome passive LCD panels support.
2: INSTALLATION AND CONFIGURATION 2 INSTALLATION AND CONFIGURATION The S1D13504 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. S1D13504 configuration inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one five-position DIP switch is provided for this purpose. All remaining configuration inputs are hard-wired. See the “S1D13504 Hardware Functional Specification,” document number S19A-A-002-xx for more information.
3: LCD/RAMDAC INTERFACE PIN MAPPING 3 LCD/RAMDAC INTERFACE PIN MAPPING Table 3-1 LCD Signal Connector (J6) S1D13504 Connector Pin Names Pin No.
4: CPU/BUS INTERFACE CONNECTOR PINOUTS 4 CPU/BUS INTERFACE CONNECTOR PINOUTS Table 4-1 CPU/BUS Connector (H1) Pinout Connector Comments Pin No.
4: CPU/BUS INTERFACE CONNECTOR PINOUTS Table 4-2 CPU/BUS Connector (H2) Pinout Connector Comments Pin No.
5: HOST BUS INTERFACE PIN MAPPING 5 HOST BUS INTERFACE PIN MAPPING Table 5-1 Host Bus Interface Pin Mapping S1D13504 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# 4-6 SH-3 MC68K Bus 1 MC68K Bus 2 Generic MPU A[20:1] A0 D[15:0] WE1# External Decode CSn# CKIO BS# RD/WR# RD# WE0# WAIT# RESET# A[20:1] LDS# D[15:0] UDS# External Decode External Decode CLK AS# R/W# Connect to IO VDD Connect to IO VDD DTACK# RESET# A[20:1] A0 D[31:16] DS# External Decode External De
6: TECHNICAL DESCRIPTION 6 TECHNICAL DESCRIPTION 6.1 ISA Bus Support The S5U13504P00C directly supports the 16-bit ISA bus environment. All the configuration options [MD15:0] are either hard-wired or selectable through the five-position DIP Switch S1. Refer to Table 2-1, “Configuration DIP Switch Settings,” on page 2 for details. Note: 1. The 8-bit ISA bus is not supported by the S5U13504P00C board design. 2.
6: TECHNICAL DESCRIPTION 6.4 Decode Logic This board design utilizes the Generic MPU Interface of the S5U13504P00C (see the “S1D13504 Hardware Functional Specification,” document number S19A-A-002-xx). All required decode logic between the ISA bus and the S1D13504 is provided through a TIBPAL22V10 PAL (U3, socketed). 6.5 Clock Input Support The input clock frequency can be up to 40.0MHz for the S1D13504. A 40.0MHz oscillator (U4, socketed) is provided as the clock (CLKI) source. 6.
6: TECHNICAL DESCRIPTION 6.10 Power Save Modes The S1D13504 supports one hardware and one software suspend Power Save Mode. The hardware suspend mode is not supported by the S5U13504P00C. The software suspend mode is controlled by the utility 1354PWR Software Suspend Power Sequencing. 6.11 Core VDD Power Supply An independent fixed 3.3V power supply for Core VDD is provided. A National LP2960AIN-3.3 voltage regulator is used for the power supply and is capable of supplying 500mA @ 3.3V. 6.
7: PARTS LIST 7 PARTS LIST No. Qty. 1 4 C13, C14, C19, C28 10µF Designation Part Value 10µF/25V Tantalum D-Size Description 2 16 C1–C12, C15–C18 0.01µF 0.01µF, 1206 package 3 3 C20, C21, C30 0.1µF 0.1µF, 1206 package 4 3 C23–C25 10µF/63V Electrolytic/Radial (LXF63VB10RM5X11LL) 5 3 C22, C26, C27 56µF/35V LXF35VB56RM6X11LL 6 1 C29 33µF 33µF/10V Tantalum D-Size 7 1 D7 LM385BZ-1.2 TO-92 PTH Zener Diode 0.1" spc.
S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05) EPSON D C B A 3.3V +12V VCC VSS +12V VCC GND IOVDD 3.3V IOVDD READY CLKI BUSCLK CS# M/R# RESET# RD1# WE1# WE0# RD0# BS# SD[0..15] A20 SA[0..19] 3.3V 1 1 2 2 R1 SD[0..15] SA[0..
EPSON D C B A WE# RAS# UCAS# LCAS# MA9 MA10 MA11 +12V VCC VSS +12V VCC GND 1 3.3V 3.3V CLKI BALE /MEMR /MEMW /SBHE /REFRESH RESET SA[0..19] LA[17..23] BS# MA[0..8] MD[0..15] SA[0..19] 2 LA[17..23] 2 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 29 11 12 32 13 14 30 31 17 18 19 20 23 24 25 26 27 28 16 15 LA23 LA22 LA21 LA20 SA0 3 2 1 8 1 12 GND VCC 22 37 42 1 6 21 2 3 4 5 7 8 9 10 33 34 35 36 38 39 40 41 3 40.
S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05) EPSON D C B A 3.3V +12V VCC VSS +12V VCC GND VCC SD[0..15] 3.3V 1 /MEMR /MEMW /SBHE LA[17..23] SA[0..19] READY SD[0..15] 1 R15 10K 2 VCC VCC 2 3 2 1 HEADER 3 JP2 R16 10K R12 10K VCC + VCC VCC 3.3V LA[17..23] SA[0..19] C13 10uF 10K R14 C6 .01 3 + +12V C14 10uF C7 .01 C8 .01 IOVDD BY-PASS CAPACITORS (1/POWER PIN) 3 VCC C9 .
EPSON D C B +12V VCC VSS +12V VCC GND IOVDD 3.3V VRTC HRTC BLANK# DACRS0 DACRS1 DACRD# DACWR# SD[0..15] DACP0 3.3V 1 DACCLK FPD AT[8..15] R18 10K SD[0..15] 2 FPD AT[8..
S5U13504P00C REV1.0 ISA BUS EVALUATION BOARD USER’S MANUAL (S19A-G-004-05) EPSON D C B A 3.3V +12V VCC VSS 3.3V +12V VCC GND 1 1 +12V WE0# CS# WE1# SD12 SD14 RESET# SD8 SD10 SD4 SD6 SD0 SD2 FPDAT[0..7] 2 FPSHIFT PSHIFT2 FPLINE FPFRAME FPD AT[8..15] MOD/DRDY/F 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 H1 3 FPD AT[8..15] F PDAT[0..
D C B +12V VCC VSS VCC GND 2 +12V L9 L8 L7 3.3V 1 1 1 3.3V 1 VCC IOVDD LCDPWR# 2 2 PSGND PSVCC PSIOVDD 2 3 PSVCC 3 VCC + C26 56uF/35V C22 C28 10uF Tantulum 56uF/35V PSVCC + 4 U8 EPN001 2 REMOTE 3 DC_IN U7 RD-0412 2 R37 100K 3 2 8 9 1 14 15 GND GND 4 VOUT_ADJ 6 3 1 DC_IN DC_IN 11 10 GND GND GND GND GND GND GND 4 5 6 7 8 10 11 LP29 60AIN-3.
ll er o s r e t ri n o e C S D 4 C 0 5 L 3 hic 1 D p S1 Gra x ri t a D M t o p Ap l t ica i on s N e ot
CONTENTS Contents Table of Contents 1 INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR .......................................5-1 1.1 Introduction....................................................................................................................................5-1 1.1.1 General Description .........................................................................................................5-1 1.2 Direct Connection to the Philips PR31500/PR31700 ................................
CONTENTS 4.5.1 Documents .................................................................................................................... 5-34 4.5.2 Document Sources ........................................................................................................ 5-34 5 INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR ................................................5-35 5.1 Introduction ...........................................................................................................
CONTENTS List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 4-1 Figure 4-2 Figure 4-3 Figure 5-1 Figure 5-2 Figure 5-3 Figure 6-1 Figure 6-2 Figure 6-3 S1D13504 to PR31500/PR31700 Direct Connection...........................................................5-2 S1D13504 to PR31500/PR31700 Connection using One IT8368E .....................................5-4 S1D13504 to PR31500/PR31700 Connection using Two IT8368E .....................................
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1 INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1.1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13504 Color Graphics LCD / CRT Controller and the Philips MIPS PR31500 / PR31700 Processor. For further information on the S1D13504, refer to the “S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx.
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1.2 Direct Connection to the Philips PR31500/PR31700 1.2.1 Hardware Description The S1D13504 is easily interfaced to the Philips PR31500/PR31700 processor. In the direct connection implementation, the S1D13504 occupies PC Card slot #1 of the PR31500/PR31700. Although the address bus of the PR31500/PR31700 is multiplexed, it can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373).
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1.2.2 Memory Mapping and Aliasing The S1D13504 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the registers. This is divided into two address ranges by connecting A23 (demultiplexed from the PR31500/PR31700) to the M/R# input of the S1D13504. Using A23 makes this implementation software compatible with the two implementations that use the ITE IT8368E (see Section 1.
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1.3 System Design Using the IT8368E PC Card Buffer If the system designer uses an ITE IT8368E PC Card and multiple-function IO buffer, the S1D13504 can be interfaced with the PR31500/PR31700 without using a PC Card slot. Instead, the S1D13504 is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the S1D13504 virtually transparent to PC Card devices that use the same slot. 1.3.
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: • pixel and frame rates. • power budget. • part count.
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1.3.3 IT8368E Configuration The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E (or the first in a twoIT8368E implementation) must have both “Fix Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide control signals needed by the S1D13504 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13504.
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1.3.5 S1D13504 Configuration The S1D13504 latches MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the “S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx. The partial table below only shows those configuration settings relevant to the IT8368E implementation.
1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR 1.4 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source. The Windows CE v2.
2: INTERFACING TO THE NEC VR4102TM MICROPROCESSOR 2 INTERFACING TO THE NEC VR4102TM MICROPROCESSOR 2.1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the NEC VR4102TM Microprocessor (µPD30102). For further information on either device refer to the respective technical specification. 2.1.
2: INTERFACING TO THE NEC VR4102TM MICROPROCESSOR 2.2 Hardware Description 2.2.1 S1D13504 Configuration The S1D13504 is configured on power-up by latching the power-on state of the DRAM data pins, MD[15:0]. Refer to the “S1D13504 Hardware Functional Specification”, document number S19AA-002-xx for details. The “partial” table below only shows those configuration settings important to this specific CPU interface.
2: INTERFACING TO THE NEC VR4102TM MICROPROCESSOR 2.3 Software Epson provides software source code for both the test utilities and the Windows CE 2.0TM display driver. The test utilities are configurable for different panel types using an MS-DOS program called 13504CFG, or by modifying the source. The Windows CE 2.0TM display driver is customized by the OEM at the source level for different panel types, resolutions and color depths. This software is available from your sales support contact.
3: INTERFACING TO THE PC CARD BUS 3 INTERFACING TO THE PC CARD BUS 3.1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Research and Development Website at http://www.
3: INTERFACING TO THE PC CARD BUS 3.2 Interfacing to the PC Card Bus 3.2.1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness. This section is an overview of the operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1 Standard (or later).
3: INTERFACING TO THE PC CARD BUS Figure 3-1 and Figure 3-2 illustrate typical memory access cycles on the PC Card bus.
3: INTERFACING TO THE PC CARD BUS 3.3 S1D13504 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13504 and offers some detail on the Generic MPU host bus interface used to implement the interface to the PC Card bus. 3.3.1 Bus Interface Modes The S1D13504 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families.
3: INTERFACING TO THE PC CARD BUS 3.3.2 Generic MPU Host Bus Interface Generic MPU host bus interface is the least processor-specific interface mode supported by the S1D13504. The Generic MPU host bus interface was chosen to implement this interface due to the simplicity of its timing. The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
3: INTERFACING TO THE PC CARD BUS 3.4 PC Card to S1D13504 Interface 3.4.1 Hardware Description The S1D13504 is interfaced to the PC Card bus with a minimal amount of glue logic. A PAL is used to decode the write and read signals of the PC Card bus which generate RD#, RD/WR#, WE0#, WE1#, and CS# for the S1D13504. The also PAL inverts the reset signal of the PC card since it is active high and the S1D13504 uses an active low reset. For PAL equations for this implementation refer to Section 3.4.
3: INTERFACING TO THE PC CARD BUS 3.4.2 S1D13504 Hardware Configuration The S1D13504 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Refer to the “S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx for details. The tables below show only those configuration settings important to the PC Card host bus interface.
3: INTERFACING TO THE PC CARD BUS 3.4.4 Register/Memory Mapping The S1D13504 is a memory mapped device. The internal registers mapped in the lower PC Card memory address space starting at zero. The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card memory address space (ranging from 200000h to 3fffffh). The PC Card socket provides 64M bytes of address space.
3: INTERFACING TO THE PC CARD BUS 3.5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source.
3: INTERFACING TO THE PC CARD BUS 3.6 References 3.6.1 Documents • PCMCIA/JEIDA, “PC Card Standard -- March 1997” • “S1D13504 Hardware Functional Specification”, Document Number S19A-A-002-xx. • “S1D13504 Programming Notes and Examples”, Document Number S19A-G-002-xx. • “S5U13504P00C Rev. 1.0 ISA Bus Evaluation Board User’s Manual”, Document Number S19AG-004-xx. 3.6.2 Document Sources • PC Card Website: http://www.pc-card.com. • Epson Research and Development Website: http://www.erd.epson.com.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4 INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.1 Introduction This applications note describes the hardware and software required to implement an interface between the S1D13504 Color Graphics LCD / CRT Controller and the Motorola MPC821 Processor.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.2 Interfacing to the MPC821 4.2.1 The MPC8xx System Bus The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern RISC microprocessors. This section is an overview of the operation of the CPU bus to establish interface requirements. 4.2.2 Overview The MPC8xx microprocessor family uses a synchronous address and data bus.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR Normal (Non-Burst) Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: • TSIZ[0:1] (Transfer Size), which indicate whether the bus cycle is 8, 16, or 32 bits in width. • RD/WR, which is high for read cycles and low for write cycles.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is aborted. The peripheral device may assert TEA, for example, if a parity error was detected; or the MPC821’s bus controller may assert TEA itself if no peripheral device responds at the addressed memory location within a bus time-out period.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.2.3 Memory Controller Module General-Purpose Chip Select Module (GPCM) The General-Purpose Chip Select Module (GPCM) is used to control memory and peripheral devices which do not require special timing or address multiplexing. In addition to the chip select output, it can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible with most memory and x86-style peripherals.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.3 S1D13504 Bus Interface This section is summary of the bus interface modes available on the S1D13504, and offers some detail on the General Purpose Bus mode used to implement the interface to the MPC821. 4.3.1 Bus Interface Modes The S1D13504 implements a general-purpose 16-bit interface to the host microprocessor, which may operate in one of several modes compatible with most of the popular embedded microprocessor families.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.3.2 Generic Bus Interface Mode Generic Bus Interface Mode is the most general and least processor-specific interface mode on the S1D13504. Although the Power PC bus is similar in many respects to the M68K bus, the generic bus interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the control signals available from the MPC821’s General-Purpose Chip Select Module.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.4 MPC821/S1D13504 Interface 4.4.1 Hardware Connections Due to the flexibility of the MPC821 and S1D13504 bus interfaces no glue logic is required. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle. Figure 4-3 shows a block diagram of the interface.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR Table 4-1 List of Connections from MPC821ADS to S1D13504 MPC821 Signal Name#1 Vcc A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SRESET SYSCLK CS4 TA WE0 WE1 OE Gnd MPC821ADS Connector and Pin Name S1D13504 Signal Name P6-A1, P6-B1 P6-C23 P6-A22 P6-B22 P6-C21 P6-C20 P6-D20 P6-B24 P6-C24 P6-D23 P6-D22 P6-D19 P6-A19 P6-D28 P6-A28 P6-C27 P6-A26 P6-C26 P6-A25 P6-
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.4.2 S1D13504 Hardware Configuration The S1D13504 uses MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Table 4-2 shows the settings used for the S1D13504 in this interface. These are very similar to the ISA bus, except that the WAIT# signal is set to active high rather than active low, and the Power PC is big endian rather than little endian.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.4.3 MPC821 Chip Select Configuration The DRAM on the MPC821 ADS board extends from address 0 through 0x3fffff, so the S1D13504 is addressed starting at 0x400000. A total of 4M bytes of address space is used, where the lower 2M bytes is reserved for the S1D13504 on-chip registers and the upper 2M bytes is used to access the S1D13504 display buffer. Chip select 4 is used to control the S1D13504.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.4.4 Test Software The test software to exercise this interface is very simple. It configures chip select 4 on the MPC821 to map the S1D13504 to an unused 4M byte block of address space; loads the appropriate values into the option register for CS4; and then writes the value 0 to the S1D13504 register REG[1Bh], to enable the S1D13504 host interface.
4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR 4.5 References 4.5.1 Documents • Motorola Inc., “Power PC MPC821 Portable Systems Microprocessor User’s Manual”; Motorola Publication no. MPC821UM/AD; available on the Internet at http://www.mot.com/SPS/ADC/pps/ _subpgs/_documentation/821/821UM.html. • “S1D13504 Hardware Functional Specification”; Document Number S19A-A-002-xx • “S5U13504P00C Rev. 1.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5 INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.1 Introduction This application note describes the hardware required to implement an interface between the S1D13504 Color Graphics LCD/CRT Controller and the Motorola MCF5307 Processor. The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.2 Interfacing to the MCF5307 5.2.1 The MCF5307 System Bus The MCF5200/5300 family of processors feature a high-speed synchronous system bus typical of modern microprocessors. This section is an overview of the operation of the CPU bus to establish interface requirements. 5.2.2 Overview The MCF5307 microprocessor family uses a synchronous address and data bus, very similar in architecture to the MC68040 and MPC8xx.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR BCLK0 TS TA TIP A[31:0] R/W SIZ[1:0], TT[1:0] D[31:0] Valid Transfer Start Wait States Transfer Complete Next Transfer Starts Figure 5-2 MCF5307 Memory Write Cycle Burst Cycles Burst cycles are very similar to normal cycles, except that they occur as a series of four back-toback, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output asserted continuously through the burst.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.3 S1D13504 Bus Interface This section is summary of the bus interface modes available on the S1D13504, and offers some detail on the General Purpose Bus mode used to implement the interface to the MCF5307. 5.3.1 Bus Interface Modes The S1D13504 implements a general-purpose 16-bit interface to the host microprocessor, which may operate in one of several modes compatible with most of the popular embedded microprocessor families.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.3.2 Generic Bus Interface Mode Generic Bus Interface Mode is the most general and least processor-specific interface mode on the S1D13504. The generic bus interface mode was chosen for this interface, due to the simplicity of its timing and compatibility with the control signals available from the MCF5307’s General-Purpose Chip Select Module.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.4 MCF5307 To S1D13504 Interface 5.4.1 Hardware Connections The S1D13504 requires a 2M byte address space for the display buffer RAM, plus a few more locations to access its internal registers. Chip selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes, however these chip selects would normally be needed to control system RAM and ROM.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.4.2 S1D13504 Hardware Configuration The S1D13504 uses MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Table 4-2 shows the settings used for the S1D13504 in this interface. These settings are very similar to the ISA bus, except that the WAIT# signal is set to active high rather than active low, and the Coldfire is big endian rather than little endian.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.4.3 MCF5307 Chip Select Configuration In the example interface, chip selects 4 and 5 are used to control the S1D13504. CS4 selects a 2M byte address space for the S1D13504’s control registers, while CS5 selects the 2M byte display RAM buffer. The CSBAR register should be set to the upper 8 bits of the desired base address.
5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR 5.5 References 5.5.1 Documents • Motorola Inc., “MCF5307 ColdFire® Integrated Microprocessor User’s Manual”; Motorola Publication no. MCF5307UM/AD; available on the Internet at http://www.mot.com/SPS/HPESD/ prod/coldfire/5307UM.html. • “S1D13504 Hardware Functional Specification”; Document Number S19A-A-002-xx • “S5U13504P00C Rev. 1.
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6 INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6.1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the Toshiba MIPS TX3912 Processor. For further information on the S1D13504, refer to the “S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx.
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6.2 Direct Connection to the Toshiba TX3912 6.2.1 Hardware Description The S1D13504 is easily interfaced to the Toshiba TX3912 processor. In the direct connection implementation, the S1D13504 occupies PC Card slot #1 of the TX3912. Although the address bus of the TX3912 is multiplexed, it can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373).
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6.2.2 Memory Mapping and Aliasing The S1D13504 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the registers. This is divided into two address ranges by connecting A23 (demultiplexed from the TX3912) to the M/R# input of the S1D13504. Using A23 makes this implementation software compatible with the two implementations that use the ITE IT8368E (see Section 1.3, “System Design Using the IT8368E PC Card Buffer” on page 4).
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6.3 System Design Using the IT8368E PC Card Buffer If the system designer uses an ITE IT8368E PC Card and multiple-function IO buffer, the S1D13504 can be interfaced with the TX3912 without using a PC Card slot. Instead, the S1D13504 is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the S1D13504 virtually transparent to PC Card devices that use the same slot. 6.3.
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR The Generic MPU host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: • pixel and frame rates. • power budget. • part count.
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6.3.3 IT8368E Configuration The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E (or the first in a twoIT8368E implementation) must have both “Fix Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide control signals needed by the S1D13504 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13504.
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6.3.5 S1D13504 Configuration The S1D13504 latches MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the “S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx. The partial table below only shows those configuration settings relevant to the IT8368E implementation.
6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR 6.4 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13504. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13504CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source.
7: POWER CONSUMPTION 7 POWER CONSUMPTION 7.1 S1D13504 Power Consumption S1D13504 power consumption is affected by many system design variables. • Input clock frequency (CLKI): the CLKI frequency determines the LCD frame-rate, CPU performance to memory, and other functions – the higher the input clock frequency, the higher the frame-rate, performance and power consumption.
7: POWER CONSUMPTION 7.1.1 Conditions The Table 7-1 “S1D13504 Total Power Consumption” below gives an example of a particular environment and its effects on power consumption. Table 7-1 S1D13504 Total Power Consumption Test Condition Total Power Consumption Core VDD = 3.3V, IO VDD = 5.0V Gray Shades / Colors Power Save Mode Active ISA Bus (8MHz) Software Hardware 1 Input Clock = 6MHz Black-and-White 38.7mW 20mW ∗1 7.59µW ∗2 LCD Panel Connected = 320x240 Monochrome 4 Grays 43.9mW 16 Grays 46.
International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 SHANGHAI BRANCH 4F, Bldg., 27, No. 69, Gui Jing Road Caohejing, Shanghai, CHINA Phone: 21-6485-5552 Fax: 21-6485-0775 - SALES OFFICES West 1960 E.
In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
MF1072-04 S1D13504 Series Technicl Manual Dot Matrix Graphics LCD Controller S1D13504 Series Technical Manual S1D13504 Series Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle papaer, and printed using soy-based inks.