User`s manual

4: ADVANCED TECHNIQUES
S1D13504 PROGRAMMING NOTES EPSON 2-13
AND EXAMPLES (S19A-G-002-06)
4ADVANCED TECHNIQUES
This section presents information on the following:
• virtual display
• panning and scrolling
• split screen display
4.1 Virtual Display
A virtual display is when the image to be displayed is larger than the physical display device in
either the horizontal dimension, the vertical dimension, or both. To view the image, the physical dis-
play is used as a window or viewport into the display buffer, allowing the user to see a portion of the
entire image. This viewport can be panned and scrolled, enabling the user to view the entire image.
The size of the virtual display is limited by the amount of available display buffer. In the case of an
S1D13504 with 2M byte of display buffer, the maximum virtual width ranges from 16,368 pixels in
1 bpp mode to 1023 pixels in 16 bpp mode. The maximum vertical size at the horizontal maximum
is 1025 lines. By trading off horizontal size a greater vertical size can be achieved.
Seldom are the maximum sizes required. Figure 4-1 “Viewport Inside a Virtual Display,” depicts a
more typical use of a virtual display. An image of 640x480 pixels can be viewed by navigating a
320x240 pixel viewport around the image using panning and scrolling.
Figure 4-1 Viewport Inside a Virtual Display
4.1.1 Registers
Registers [16h] and [17h] form a ten bit value referred to as the memory offset. This offset is the
number of words from the first byte of one line of display buffer to the first byte in the next line. This
value takes into account the number of non-displayed pixels on each line.
Different color depths have different numbers of pixels per word. To represent an offset of a given
number of pixels the offset registers will contain different values at different color depths. The for-
mula to calculate the offset to write to these registers is:
offset_register = pixels_per_line / pixels_per_word
REG[16h] Memory Address Offset Register 0
Memory
Address Offset
Bit 7
Memory
Address Offset
Bit 6
Memory
Address Offset
Bit 5
Memory
Address Offset
Bit 4
Memory
Address Offset
Bit 3
Memory
Address Offset
Bit 2
Memory
Address Offset
Bit 1
Memory
Address Offset
Bit 0
REG[17h] Memory Address Offset Register 1
n/a n/a n/a n/a n/a n/a
Memory
Address Offset
Bit 9
Memory
Address Offset
Bit 8
320x240
Viewport
640x480
“Virtual” Display