User`s manual

5: LCD POWER SEQUENCING AND POWER SAVE MODES
2-20 EPSON S1D13504 PROGRAMMING NOTES
AND EXAMPLES (S19A-G-002-06)
5 LCD POWER SEQUENCING AND POWER
SAVE MODES
5.1 Introduction to LCD Power Sequencing
LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD
signals. Power sequencing is required to prevent long term damage to the panel and to avoid
unsightly “lines” on power down and start-up.
LCD Power Sequencing is performed on the S1D13504 through a software procedure even when
using hardware power save modes. Most “green” systems today use some sort of software power
down procedure in conjunction with external circuitry to set hardware suspend modes. These proce-
dures typically save/restore state information, or provide a timer prior to initiating power down. The
S1D13504 requires a timer between the time the LCD power is disabled and the time the LCD sig-
nals are shut down. Conversely, the LCD signals must be active prior to the power supply starting
up. For simplicity, we have chosen to use the same time value for power up and power down proce-
dures.
The time interval required varies depending on the power supply design. The power supply on the
S5U13504P00C Evaluation board requires 0.5 seconds to fully discharge. Your power supply design
may vary.
Below are the procedures for all cases in which power sequencing is required.
5.2 Introduction to Power Save Modes
The S1D13504 has two power save modes. One is hardware-initiated via the SUSPEND# pin, the
other is software-initiated through REG[1A] bit 0. Both require power sequencing as described
above.
5.3 Registers
Register bits discussed in this section are highlighted.
Suspend Refresh Select bits [1:0] should be set on power up depending on the type of DRAM avail-
able. See the “S1D13504 Hardware Functional Specification”, document number S19A-A-002-xx.
All other bits should be masked into the register on a write. i.e. do a read, modify with mask, and
write to set the bits.
REG[0D] Display Mode Register
n/a
Simultaneous
Display Option
Select Bit 1
Simultaneous
Display Option
Select Bit 0
Number of
BPP Select
Bit 2
Number of
BPP Select
Bit 1
Number of
BPP Select
Bit 0
CRT Enable
LCD Enable
REG[1A] Power Save Configuration Register
n/a n/a n/a n/a
LCD Power
Disable
Suspend
Refresh Select
Bit 1
Suspend
Refresh Select
Bit 0
Software
Suspend Mode
Enable