User`s manual

6: CRT CONSIDERATIONS
S1D13504 PROGRAMMING NOTES EPSON 2-25
AND EXAMPLES (S19A-G-002-06)
Address R G B Address R G B Address R G B Address R G B
80 24 00 00 A0 2D 00 00 C0 36 00 00 E0 3F 00 00
81 24 00 15 A1 2D 00 15 C1 36 00 15 E1 3F 00 15
82 24 00 2A A2 2D 00 2A C2 36 00 2A E2 3F 00 2A
83 24 00 3F A3 2D 00 3F C3 36 00 3F E3 3F 00 3F
84 24 09 00 A4 2D 09 00 C4 36 09 00 E4 3F 09 00
85 24 09 15 A5 2D 09 15 C5 36 09 15 E5 3F 09 15
86 24 09 2A A6 2D 09 2A C6 36 09 2A E6 3F 09 2A
87 24 09 3F A7 2D 09 3F C7 36 09 3F E7 3F 09 3F
88 24 12 00 A8 2D 12 00 C8 36 12 00 E8 3F 12 00
89 24 12 15 A9 2D 12 15 C9 36 12 15 E9 3F 12 15
8A 24 12 2A AA 2D 12 2A CA 36 12 2A EA 3F 12 2A
8B 24 12 3F AB 2D 12 3F CB 36 12 3F EB 3F 12 3F
8C 24 1B 00 AC 2D 1B 00 CC 36 1B 00 EC 3F 1B 00
8D 24 1B 15 AD 2D 1B 15 CD 36 1B 15 ED 3F 1B 15
8E 24 1B 2A AE 2D 1B 2A CE 36 1B 2A EE 3F 1B 2A
8F 24 1B 3F AF 2D 1B 3F CF 36 1B 3F EF 3F 1B 3F
90 24 24 00 B0 2D 24 00 D0 36 24 00 F0 3F 24 00
91 24 24 15 B1 2D 24 15 D1 36 24 15 F1 3F 24 15
92 24 24 2A B2 2D 24 2A D2 36 24 2A F2 3F 24 2A
93 24 24 3F B3 2D 24 3F D3 36 24 3F F3 3F 24 3F
94 24 2D 00 B4 2D 2D 00 D4 36 2D 00 F4 3F 2D 00
95 24 2D 15 B5 2D 2D 15 D5 36 2D 15 F5 3F 2D 15
96 24 2D 2A B6 2D 2D 2A D6 36 2D 2A F6 3F 2D 2A
97 24 2D 3F B7 2D 2D 3F D7 36 2D 3F F7 3F 2D 3F
98 24 36 00 B8 2D 36 00 D8 36 36 00 F8 3F 36 00
99 24 36 15 B9 2D 36 15 D9 36 36 15 F9 3F 36 15
9A 24 36 2A BA 2D 36 2A DA 36 36 2A FA 3F 36 2A
9B 24 36 3F BB 2D 36 3F DB 36 36 3F FB 3F 36 3F
9C 24 3F 00 BC 2D 3F 00 DC 36 3F 00 FC 3F 3F 00
9D 24 3F 15 BD 2D 3F 15 DD 36 3F 15 FD 3F 3F 15
9E 24 3F 2A BE 2D 3F 2A DE 36 3F 2A FE 3F 3F 2A
9F 24 3F 3F BF 2D 3F 3F DF 36 3F 3F FF 3F 3F 3F
Table 6-4 Related Register Data for Simultaneous Display
Register
640X480@75Hz
PCLK=40.0MHz
640X480@60Hz
PCLK=40.0MHz
Notes
REG[04h] 0100 1111 0100 1111 set horizontal display width
REG[05h] 0001 1101 0001 0011 set horizontal non-display period
REG[06h] 0000 0011 0000 0001 set HSYNC start position
REG[07h] 0000 0111 0000 1011 set HSYNC polarity and pulse width
REG[08h] 1000 1111 1101 1111 set vertical display height bits 7–0
REG[09h] 0000 0001 0000 0001 set vertical display height bits 9–8
REG[0Ah] 0010 1100 0010 1100 set vertical non-display period
REG[0Bh] 0000 0000 0000 1001 set VSYNC start position
REG[0Ch] 1000 0010 0000 0001 set VSYNC polarity and pulse width
REG[0Dh] 0000 1111 0000 1111 set 8 bpp and CRT enable
REG[19h] 0000 0000 0000 0000 set MCLK and PCLK divide
REG[24h] 0000 0000 0000 0000 set look-up table address to 0
REG[26h] load look-up table
REG[27h] 0000 0000 0000 0000 set look-up table to bank 0
REG[2Ch] program RAMDAC program RAMDAC set write mode address to 0
REG[2Eh] load RAMDAC palette data