User`s manual

9: SAMPLE CODE
S1D13504 PROGRAMMING NOTES EPSON 2-41
AND EXAMPLES (S19A-G-002-06)
*/
*(pRegs + 0x0A) = 0x01; /* 0000 0001 */
/*
** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x0B) = 0x00; /* 0000 0000 */
/*
** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x0C) = 0x00; /* 0000 0000 */
/*
** Registers E-F: Screen 1 Line Compare - unless setting up for
** split screen operation use 0x3FF.
*/
*(pRegs + 0x0E) = 0xFF; /* 1111 1111 */
*(pRegs + 0x0F) = 0x03; /* 0000 0011 */
/*
** Registers 10-12: Screen 1 Display Start Address - start at the
** first byte in display memory.
*/
*(pRegs + 0x10) = 0x00; /* 0000 0000 */
*(pRegs + 0x11) = 0x00; /* 0000 0000 */
*(pRegs + 0x12) = 0x00; /* 0000 0000 */
/*
** Register 13-15: Screen 2 Display Start Address - not applicable
** unless setting up for split screen operation.
*/
*(pRegs + 0x13) = 0x00; /* 0000 0000 */
*(pRegs + 0x14) = 0x00; /* 0000 0000 */
*(pRegs + 0x15) = 0x00; /* 0000 0000 */
/*
** Register 16-17: Memory Address Offset - this address represents the
** starting WORD. At 8BPP our 320 pixel width is 160
** WORDS
*/
*(pRegs + 0x16) = 0xA0; /* 1010 0000 */
*(pRegs + 0x17) = 0x00; /* 0000 0000 */
/*
** Register 18: Pixel Panning -
*/
*(pRegs + 0x18) = 0x00; /* 0000 0000 */
/*
** Register 19: Clock Configuration - In this case we must divide
** MCLK by 4 to arrive at the best frequency to set
** our desired panel frame rate.
*/
*(pRegs + 0x19) = 0x03; /* 0000 0011 */
/*
** Register 1A: Power Save Configuration - enable LCD power, CBR refresh,
** not suspended.
*/
*(pRegs + 0x1A) = 0x00; /* 0000 0000 */
/*
** Register 1C-1D: MD Configuration Readback - don't write anything to
** these registers.
*/
/*
** Register 1E-1F: General I/O Pins Configuration - these values
** may need to be changed according to your system
*/
*(pRegs + 0x1E) = 0x00; /* 0000 0000 */
*(pRegs + 0x1F) = 0x00; /* 0000 0000 */
/*
** Register 20-21: General I/O Pins Control - these values
** may need to be changed according to your system
*/
*(pRegs + 0x20) = 0x00; /* 0000 0000 */
*(pRegs + 0x21) = 0x00; /* 0000 0000 */
/*
** Registers 24-27: LUT control.
** For this example do a typical 8BPP LUT setup.