User`s manual

1: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR
5-2
EPSON
APPLICATION NOTES (S19A-G-005-05)
1.2 Direct Connection to the Philips PR31500/PR31700
1.2.1 Hardware Description
The S1D13504 is easily interfaced to the Philips PR31500/PR31700 processor. In the direct connec-
tion implementation, the S1D13504 occupies PC Card slot #1 of the PR31500/PR31700. Although
the address bus of the PR31500/PR31700 is multiplexed, it can be demultiplexed using an advanced
CMOS latch (e.g., 74ACT373). The direct connection implementation makes use of the Asynchro-
nous Generic MPU host bus interface capability of the S1D13504.
The following diagram demonstrates a typical implementation of the interface.
Figure 1-1 S1D13504 to PR31500/PR31700 Direct Connection
The host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504
bus clock. This gives the system designer full flexibility in choosing the appropriate source (or
sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to
use DCLKOUT (divided) as the clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.
/RD
/WE
/CARD1CSL
/CARD1CSH
ALE
A[12:0]
D[31:24]
D[23:16]
/CARD1WAIT
DCLKOUT
IO VDD, CORE VDD
RD0#
RD1#
WE0#
WE1#
CS#
M/R#
RESET#
AB[20:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
BUSCLK
CLKI
PR31500/PR31700 S1D13504
Latch
Clock
divider
Oscillator
15K pull-up
... or ...
A23
A20:13
V
DD
System RESET
See text
+3.3V
ENDIAN